Prosecution Insights
Last updated: July 23, 2026
Application No. 19/019,432

TIME-INTERLEAVED ADC ERROR PARAMETER EXTRACTION AND CORRECTION METHOD

Non-Final OA §102§103
Filed
Jan 13, 2025
Priority
May 08, 2024 — CN 202410559425.X
Examiner
MAI, LAM T
Art Unit
Tech Center
Assignee
Chengdu Sino Microelectronics Technology Co. Ltd.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allowance Rate
979 granted / 1020 resolved
+36.0% vs TC avg
Minimal +1% lift
Without
With
+0.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 6m
Avg Prosecution
19 currently pending
Career history
1031
Total Applications
across all art units

Statute-Specific Performance

§101
16.2%
-23.8% vs TC avg
§103
22.4%
-17.6% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1020 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain (USP 9,437,212). Regarding claim 2, Jain discloses a system architecture in figures 2 and 6 that teaches: converting a time domain signal output from each channel into a frequency domain signal (208) ; calculating one or more error parameters according to the frequency domain signal (212, see 608, 610 for details); correcting the frequency domain signal in one or more different channels according to the one or more error parameters (212, 608,610 for details); and converting the corrected frequency domain signal into one or more corrected time domain signals (218) (see figures 2, 6 and their descriptions). Regarding claim 2, Jain teaches in figures 2 and 6 there is one channel (Yt). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2006/0232460) and further in view of Chao (US 2024/0196149). Regarding claim 1, Huang et al. discloses a time-interleave ADC architecture in figure 1 that teaches: converter circuit (120), error calculation circuit (130) and error correcting or compensating circuit (140) and outputting corrected outputs (see figures 1-2 and their descriptions). However, Huang fails to teach or suggest input domain be time to frequency and converting back from frequency to time domain after error correcting or compensating function. While, Chao discloses signal processing architecture in figure 5 that teaches time domain be converting to frequency domain (510) then converting back from frequency domain to time domain (530) after error correcting or compensating function (see figure 5 and its descriptions). Therefore, it would be obvious to an ordinary skill in the art at the effective filing time of the invention to implement Chao’s teaching into Huang’s discloses to satisfy the invention needed. Regarding claim 2, Huang further teaches the calibrating or correcting or compensation channel is 1 (see figures 1-2). Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2006/0232460) and further in view of Jain (USP 9,437,212) Regarding claim 1, Huang et al. discloses a time-interleave ADC architecture in figure 1 that teaches: converter circuit (120), error calculation circuit (130) and error correcting or compensating circuit (140) and outputting corrected outputs (see figures 1-2 and their descriptions). However, Huang et al. fails to teach or suggest input domain be time to frequency and converting back from frequency to time domain after error correcting or compensating function. While, Jain discloses signal processing architecture in figure 2 that teaches time domain be converting to frequency domain (208) then converting back from frequency domain to time domain (218) after error correcting or compensating function (see figure 2 and its descriptions). Therefore, it would be obvious to an ordinary skill in the art at the effective filing time of the invention to implement Jain’s teaching into Huang’s discloses to satisfy the invention needed. Regarding claim 2, Huang further teaches the calibrating or correcting or compensation channel is 1 (see figures 1-2). Allowable Subject Matter Claims 3 and 4 is objected to as being dependent upon a rejected base claim, but they would be considered for allowable if they are rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein calculating the one or more error parameters according to the frequency domain signal also includes correcting the one or more error parameters according to a change in a process-voltage-temperature (PVT) parameter. Claims 5-9 are objected to as being dependent upon a rejected base claim, but they would be considered for allowable if they are rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the one or more error parameters include a DC offset error parameter, an amplitude error parameter, and a phase error parameter. Cited References The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM T MAI whose telephone number is (571)272-1807. The examiner can normally be reached Monday-Friday 6am-2pm eastern time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571 272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAM T MAI/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Jan 13, 2025
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
97%
With Interview (+0.9%)
1y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1020 resolved cases by this examiner. Grant probability derived from career allowance rate.

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