DETAILED ACTION
This Office Action, based on application 19/019,470 filed 14 January 2025, is filed in response to applicant’s amendment and remarks filed 23 March 2026. Claims 1-20 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 23 March 2026 in response to the Office Action filed 16 January 2026, have been fully considered below.
Specification Objection
The Office withdraws the previously issued objection in view of applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection alleging cited prior art fails to disclose the elements of Claim 1 as amended. The amendment Claim 1 includes “physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later physical addresses, and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions”. The Office concedes the combination of KOBAYASHI and CAMP do not explicitly disclose repair techniques for replacing bad memory units with memory units in a redundant or spare area of memory and as such do not explicitly disclose the amended subject matter. After new search and consideration, the Office introduces new grounds of rejection to Claim 1 (and accordingly Claim 11 and respective dependent claims) in view of GUNNAM which discloses repair techniques replacing bad pages of a block with auxiliary pages.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 9, 11-14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI (US PGPub 2006/0282754) in further view of CAMP et al (US PGPub 2016/0179412) and GUNNAM et al (US PGPub 2018/0307431).
With respect to Claim 1, KOBAYASHI discloses a memory management method, comprising:
selecting a target bad block of a rewritable non-volatile memory module to write first data (¶[0002] – “FIG. 14 shows the data path used when writing data from host 100 onto memory module 110, and shows the data path when transferring read data from memory module 110 to host 100”; Fig 14 describes memory module 110 as a general purpose DIMM);
obtaining second data from the target bad block and comparing the first data and the second data to determine one or more error byte positions (¶[0004] – “When host 100 makes a request, read data 111 and read ECC code 112 belonging to data 111 are read out from memory module 110. ECC check circuit 113 makes an error check. If an error is detected, then read data 111 and read ECC code 112 are input to syndrome generator circuit 114, and a syndrome is generated to show the error location (i.e., the location needing correction)”);
establishing a bad byte table according to the one or more error byte positions (¶[0046] – “data recovery circuit 13 may specify the error byte from the check results of a plurality of check circuits (e.g., two check circuits 14 and 15), write what byte position of the data will be error-corrected in error byte table 16, and temporarily store read data 12 and read parity data 11 in temporary buffer 17 while the error is detected”);
KOBAYASHI may not explicitly disclose resetting a plurality of physical addresses of a plurality of storage units owned by each bad block of a target plane to which the target bad block belongs according to the bad byte table, wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions; and setting bad blocks of the target plane as normal physical blocks.
However, CAMP discloses resetting a plurality of physical addresses of a plurality of storage units owned by each bad block of a target plane to which the target bad block belongs according to the bad byte table (¶[0060] – “units of non-volatile memory which exhibit program errors, erase errors, a raw bit error rate (RBER) above a threshold for a given read operation, etc., may be assigned to a designated table (e.g., a bad block table) thereby retiring the portion of non-volatile memory from any future use”; ¶[0069] – “the unit of memory may include at least one block of non-volatile memory a single block, multiple blocks, a block-stripe, etc.) and/or a portion of a block of the non-volatile memory (e.g., one or more pages); Fig 5, Step 500 – “Determine that a unit of memory meets a retirement condition” => Step 506 – “Indicate that the unit of memory remains usable” {analogous to ‘resetting’}); and setting bad blocks of the target plane as normal physical blocks (¶[0070] – “operation 506 may include … list the unit of memory in a table of good blocks …”).
KOBAYASHI and CAMP are analogous art because they are from the same field of endeavor of lifecycle management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOBAYASHI and CAMP before him or her, to modify the data recovery circuit or controller of KOBAYASHI to include a process to restore an indicated bad block as a normal block as taught by CAMP. A motivation for doing so would have been to enable the reuse of individual blocks, through a reverification process, irreversibly marked as retired due to previously detected errors associated with the blocks thus extending the life of the memory (¶[0004]). Therefore, it would have been obvious to combine KOBAYASHI and CAMP to obtain the invention as specified in the instant claims.
KOBAYASHI and CAMP may not explicitly disclose wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions.
However, GUNNAM discloses wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions (¶[0148] – “a primary page is evaluated and the determination of whether the primary page is bad is performed for each access request for the primary page … and in response to the determining that the one primary page is bad, remapping a physical address of the one bad page to a physical address of one auxiliary page. ¶[0147] – “The remapping techniques described herein can be used after employing ROM fuses, if available, which physically connect auxiliary pages to control lines such as word lines in place of bad primary pages of memory cells”. Remapping a physical address of a page to an auxiliary page via hardwiring redirects the access of a physical address from the page to the auxiliary page effectively ‘skipping’ access to the original page and directs the access to an auxiliary or redundant page).
KOBAYASHI, CAMP, and GUNNAM are analogous art because they are from the same field of endeavor of lifecycle management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOBAYASHI, CAMP, and GUNNAM before him or her, to modify the data recovery circuit or controller of the combination of KOBAYASHI and CAMP to include replacing bad pages of a block with auxiliary pages on a per-page basis as taught by GUNNAM. A motivation for doing so would have been to maintain the total capacity of a memory device comprising memory cells that are no longer suitable for storing data in memory devices configured to include extra or auxiliary cells (¶[0037]). Therefore, it would have been obvious to combine KOBAYASHI, CAMP, and GUNNAM to obtain the invention as specified in the instant claims.
With respect to Claim 11, KOBAYASHI discloses a memory controller, adapted for controlling a storage device disposed with a rewritable non-volatile memory module (Fig 1, Memory Module 10), wherein the memory controller comprises:
a memory interface control circuit, is configure to electrically connect to the rewritable non-volatile memory module (Fig 14, ¶[0039] – “Fig 14 is an exemplary block diagram of a data processor circuit of the related art”);
a processor, electrically connected to the memory interface control circuit and a connection interface circuit of the storage device for electrically connecting to a host system (Fig 14, ¶[0039] – “Fig 14 is an exemplary block diagram of a data processor circuit of the related art”);
wherein the processor is configured to:
select a target bad block of the rewritable non-volatile memory module to write first data (¶[0002] – “FIG. 14 shows the data path used when writing data from host 100 onto memory module 110, and shows the data path when transferring read data from memory module 110 to host 100”; Fig 14 describes memory module 110 as a general purpose DIMM);
obtain second data from the target bad block and compare the first data and the second data to determine one or more error byte positions (¶[0004] – “When host 100 makes a request, read data 111 and read ECC code 112 belonging to data 111 are read out from memory module 110. ECC check circuit 113 makes an error check. If an error is detected, then read data 111 and read ECC code 112 are input to syndrome generator circuit 114, and a syndrome is generated to show the error location (i.e., the location needing correction)”);
establish a bad byte table according to the one or more error byte positions (¶[0046] – “data recovery circuit 13 may specify the error byte from the check results of a plurality of check circuits (e.g., two check circuits 14 and 15), write what byte position of the data will be error-corrected in error byte table 16, and temporarily store read data 12 and read parity data 11 in temporary buffer 17 while the error is detected”).
KOBAYASHI may not explicitly disclose reset a plurality of physical addresses of a plurality of storage units owned by each bad block of a target plane to which the target bad block belongs according to the bad byte table, wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions; and set bad blocks of the target plane as normal physical blocks.
However, CAMP discloses reset a plurality of physical addresses of a plurality of storage units owned by each bad block of a target plane to which the target bad block belongs according to the bad byte table (¶[0060] – “units of non-volatile memory which exhibit program errors, erase errors, a raw bit error rate (RBER) above a threshold for a given read operation, etc., may be assigned to a designated table (e.g., a bad block table) thereby retiring the portion of non-volatile memory from any future use”; ¶[0069] – “the unit of memory may include at least one block of non-volatile memory a single block, multiple blocks, a block-stripe, etc.) and/or a portion of a block of the non-volatile memory (e.g., one or more pages); Fig 5, Step 500 – “Determine that a unit of memory meets a retirement condition” => Step 506 – “Indicate that the unit of memory remains usable” {analogous to ‘resetting’}); and set bad blocks of the target plane as normal physical blocks (¶[0070] – “operation 506 may include … list the unit of memory in a table of good blocks …”).
KOBAYASHI and CAMP are analogous art because they are from the same field of endeavor of lifecycle management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOBAYASHI and CAMP before him or her, to modify the data recovery circuit or controller of KOBAYASHI to include a process to restore an indicated bad block as a normal block as taught by CAMP. A motivation for doing so would have been to enable the reuse of individual blocks, through a reverification process, irreversibly marked as retired due to previously detected errors associated with the blocks thus extending the life of the memory (¶[0004]). Therefore, it would have been obvious to combine KOBAYASHI and CAMP to obtain the invention as specified in the instant claims.
KOBAYASHI and CAMP may not explicitly disclose wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions.
However, GUNNAM discloses wherein in the resetting, physical addresses of each minimum operation unit skip the one or more error byte positions and are postponed to later addresses and physical addresses of a redundant area of each physical block compensate for physical addresses that were postponed due to skipping the error byte positions (¶[0148] – “a primary page is evaluated and the determination of whether the primary page is bad is performed for each access request for the primary page … and in response to the determining that the one primary page is bad, remapping a physical address of the one bad page to a physical address of one auxiliary page. ¶[0147] – “The remapping techniques described herein can be used after employing ROM fuses, if available, which physically connect auxiliary pages to control lines such as word lines in place of bad primary pages of memory cells”. Remapping a physical address of a page to an auxiliary page via hardwiring redirects the access of a physical address from the page to the auxiliary page effectively ‘skipping’ access to the original page and directs the access to an auxiliary or redundant page).
KOBAYASHI, CAMP, and GUNNAM are analogous art because they are from the same field of endeavor of lifecycle management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOBAYASHI, CAMP, and GUNNAM before him or her, to modify the data recovery circuit or controller of the combination of KOBAYASHI and CAMP to include replacing bad pages of a block with auxiliary pages on a per-page basis as taught by GUNNAM. A motivation for doing so would have been to maintain the total capacity of a memory device comprising memory cells that are no longer suitable for storing data in memory devices configured to include extra or auxiliary cells (¶[0037]). Therefore, it would have been obvious to combine KOBAYASHI, CAMP, and GUNNAM to obtain the invention as specified in the instant claims.
With respect to Claims 2 and 12, the combination of KOBAYASHI, CAMP, and GUNNAM disclose the method/controller according to each respective parent claim.
CAMP further discloses wherein the rewritable non-volatile memory module has a plurality of planes, and a target bad block is selected from each plane to establish a corresponding bad byte table (¶[0039] – “the organization of memory blocks into block-stripes allows for adding RAID-like parity protection schemes among memory blocks from different memory chips, memory planes and/or channels as well as significantly enhancing performance through higher parallelism”).
With respect to Claims 3 and 13, the combination of KOBAYASHI, CAMP, and GUNNAM disclose the method/controller according to each respective parent claim.
CAMP further discloses wherein the target bad block is selected by a random manner (¶[0047] – “Write allocation includes placing data of write operations into free locations of open block-stripes. As soon as all pages in a block-stripe have been written, the block-stripe is closed and placed in a pool holding occupied block-stripes. Typically, block-stripes in the occupied pool become eligible for garbage collection. The number of open block-stripes is normally limited and any block-stripe being closed may be replaced, either immediately or after some delay, with a fresh block-stripe that is being opened.”); and
KOBAYASHI further discloses content of the first data is a plurality of predetermined bit values (¶[0002] – “FIG. 14 shows the data path used when writing data from host 100 onto memory module 110” – writing data is provided by the host thus is ‘predetermined’).
KOBAYASHI, CAMP, and GUNNAM may not explicitly disclose the plurality of bit values are set to be one of following patterns: all being a same first value or second value; and the first value and the second value being randomly arranged.
However, KOBAYASHI states at ¶[0042] that “To transfer data from host 1 to memory module 10, host 1 sends write data 3 via host bus 2. Write data 3 is transferred from write buffer 6 to write-back selector 7, and then to memory module 10” and ¶[0055] that “Host 1 sends data (e.g., transfers write data) to memory module 10 (S61). When storing data in memory module 10, CRC generator circuit 4 generates an eight-byte CRC check code each time 512 bytes of write data 35 are sent from host 1” which at least suggests a host may specify any combination of ‘1’s and ‘0’s as write data to be stored in the memory module including a data pattern wherein all bits are the same value. As such, with the suggestions asserted by KOBAYASHI, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration KOBAYASHI’s explicit teachings and suggestions to have been able to modify the combination of KOBAYASHI, CAMP, and GUNNAM such that data written to memory may include a data pattern where all bits are either ‘1’s or ‘0’s with a reasonable expectation of success. A motivation for doing so may be due to an application executing on the host requesting to store that particular value.
With respect to Claims 4 and 14, the combination of KOBAYASHI, CAMP, and GUNNAM disclose the method/controller according to each respective parent claim.
KOBAYASHI further discloses establishing the bad byte table according to the plurality of groups of error byte positions and the error byte pattern (¶[0046] – “data recovery circuit 13 may specify the error byte from the check results of a plurality of check circuits (e.g., two check circuits 14 and 15), write what byte position of the data will be error-corrected in error byte table 16, and temporarily store read data 12 and read parity data 11 in temporary buffer 17 while the error is detected”).
CAMP further discloses writing a plurality of first data with different patterns to the target bad block (¶[0084] – “However, when decision 562 determines that the unit of memory has been successfully erased at least the predetermined number of times, method 500 proceeds to operation 564 which includes writing data to each subset of the unit of memory. For example, if the unit of memory corresponds to a block of non-volatile memory, operation 564 may include writing data to all pages of the block of memory. Furthermore, in some approaches operation 564 may also include only writing data to each subset of valid pages in the block, e.g., when page-level retirement is used. Depending on the approach, the data written to each subset of the unit of memory may be predefined, random, pseudo random, etc.”); obtaining a plurality of second data corresponding to the plurality of first data from the target bad block to obtain a plurality of groups of error byte positions (¶[0086] – “After completing operation 564, method 500 advances to decision 566 which determines whether the write procedure of operation 564 was performed successfully. When decision 566 determines that one or more write error occurs during the write procedure (the write procedure was unsuccessful), method 500 proceeds to operation 508 whereby the result of the re-evaluation is to retire the unit of memory from any future use. An unsuccessful write procedure may result when a number of write errors for one or more of the subunits of the unit of memory is greater than an accepted threshold.”), analyzing the plurality of groups of error byte positions to determine whether an error byte pattern of the target bad block is a regular pattern or an irregular pattern (¶[0061] – “Additional examples in which the errors exhibited by a unit of non-volatile memory may be temporary include instances in which the retirement error count limit for the unit of memory has been reached by coincidence (e.g., due to a particular data pattern)”).
With respect to Claims 9 and 19, the combination of KOBAYASHI, CAMP, and GUNNAM disclose the method/controller according to each respective parent claim.
GUNNAM further discloses comparing a plurality of physical addresses already set to the plurality of storage units and the one or more target error byte positions to obtain one or more first physical addresses corresponding to the one or more target error byte positions and a plurality of second physical addresses not corresponding to the one or more target error byte positions; and sequentially setting the plurality of second physical addresses and one or more third physical addresses to the plurality of storage units, wherein the one or more third physical addresses belong to a plurality of redundant physical addresses of a redundant area of each physical block (Fig 7B; ¶[0121-0222] – “A first column of the table lists the logical address as in FIG. 7A. A second column of the table lists a primary block/page physical address, e.g., in terms of a block identifier and a page identifier. The memory structure 126 may be divided into a region of primary memory cells comprising primary blocks and primary pages, and a region of auxiliary memory cells comprising auxiliary blocks and auxiliary pages, in one approach. The primary block/page physical addresses are in block p0 as pages 0-127. A third column of the table in the listing 700 lists physical addresses of an auxiliary block/page for the bad primary pages. In this example, block p0, page 4 is remapped to block s0, page 0, and block p0, page 7 is remapped to block s0, page 1.”).
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI in further view of CAMP, GUNNAM, and CASADO et al (US PGPub 2014/0258805).
With respect to Claims 10 and 20, the combination of KOBAYASHI, CAMP, and GUNNAM disclose the method/controller according to each respective parent claim.
KOBAYASHI, CAMP, and GUNNAM may not explicitly disclose according to a total number of one or more fourth physical addresses that are not the one or more third physical addresses among the plurality of redundant physical addresses, upgrading a first error correction capability of each physical block of the target plane to a second error correction capability, so as to adjust a size of generated error correction data from a first size to a second size.
However, CASADO discloses according to a total number of one or more fourth physical addresses that are not the one or more third physical addresses among the plurality of redundant physical addresses, upgrading a first error correction capability of each physical block of the target plane to a second error correction capability, so as to adjust a size of generated error correction data from a first size to a second size (¶[0031] – “Accordingly, if it is determined that the next level of errors in a unit of memory (e.g., a memory page) may not be correctable by the ECC device 150, the MC 104 (error correction block 108) may generate new error correction codes with increased error correction capabilities. In some embodiments, the MC 104 may perform a "boost error correction capability" routine 212”).
KOBAYASHI, CAMP, GUNNAM, and CASADO are analogous art because they are from the same field of endeavor of lifecycle management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOBAYASHI, CAMP, GUNNAM, and CASADO before him or her, to modify the data recovery circuit of the combination of KOBAYASHI, CAMP, and GUNNAM to include a second level of error correction capabilities as taught by CASADO. A motivation for doing so would have been to provide memory integrity protection solutions for mission-critical devices including the ability to correct multi-bit errors (¶[0003]). Therefore, it would have been obvious to combine KOBAYASHI, CAMP, GUNNAM, and CASADO to obtain the invention as specified in the instant claims.
Allowable Subject Matter
Claim 5-8 and 15-18 are allowed over prior art.
Exemplary Claim 5 (and similarly Claim 15) further limits Claim 4 directed to a method of managing a bad byte table including establishing the table based on error byte positions and error byte pattern. The Office maintains cited prior art including the combination of KOBAYASHI and CAMP disclose the management of a bad block/unit table meeting the features of Claim 4 above based on reasons presented in the rejection of record. However, the Office has not found prior art that anticipates or renders obvious the establishment of the table based on regular or irregular error byte patterns as limited in the claims (e.g. if address differences between adjacent two error byte positions in each group of error byte positions are all a fixed value or not a fixed value).
Claims 5-8 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC T LOONAN/Examiner, Art Unit 2137
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