DETAILED ACTION
This Office Action, based on application 19/019,543 filed 14 January 2025, is entered responsive to applicant’s amendment and remarks filed 23 September 2026. Claims 1-18 are currently pending and have been fully considered below.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 September 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 23 September 2026 in response to the Office Action mailed 7 July 2026, have been fully considered below.
Claim Rejections under 35 U.S.C. § 102/103
The applicant traverses the prior art rejection alleging cited prior art fails to disclose the limitations of Claim 1 as amended. While the applicant notes the teachings of KOMAKI at ¶[0031], ¶[0042], and ¶[0076], the applicant alleges KOMAKI “fails to disclose the condition of a signal received by the system controller 11 for supplying power to the XDR DRAMs 13a to 13d during resetting”. In response, the Office asserts Claim 1 is not limited as alleged by the applicant as Claim 1 is not limited to receiving the signal during resetting (or during a reset period). The applicant submits cited prior art fails to disclose “maintains a power supply to the memory array according to a time length of a first voltage level of the trigger signal …” as amended. The Office presents new grounds of rejection in further view of LIN for teaching the amended subject matter.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Exemplary Claim 1 was amended to recite “the controller maintains a power supply to the memory array according to a time length of a first voltage level of the trigger signal during a reset period”. Applicant’s remarks filed 23 September 2026 indicate support for the amendment may be found on ¶[0018], ¶[0019], and Fig. 3. ¶[0019] recites “The time length of the reset signal S1 may be used to determine whether to trigger the operation of the controller circuit 120 maintaining the power supply to the memory array 110 during the reset period”. While the specification further recites “The reset signal S1 with the longer time length may be used as the trigger signal S2 to trigger the operation of maintaining the power supply”, the Office submits a time length, as recited in the teachings, is used to determine between reset signals S1 and S1’ which signal is used as the trigger signal S2. Once the trigger signal is determined, the time length of the signal provides no basis to maintaining a power supply to the memory array. As such, the Office submits the claims, as amended, recite new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim is directed to “one of the first reset signal and the second reset signal with a short time length is used as the trigger signal”. The term ‘short’ is a relative term; the metes and bounds as to what time lengths constitute a ‘short’ time length cannot be determined by the claim or the specification rendering the term indefinite.
Claim 17 is directed a similar limitation where the ‘longer’ of the two signals is used as the trigger signal. The term is definite since the term ‘longer’ is understood to be relative to the two signals (opposed to the term ‘short’ which is understood to be relative to a particular time length). For prior art evaluation purposes, the term ‘short’ is understood to be ‘shorter’.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 5, 6, 9, 10, 13, 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOMAKI (US PGPub 2010/0138597) in further view of LIN et al (US PGPub 2007/0165428)
With respect to Claim 1, KOMAKI discloses a memory storage apparatus, comprising:
a memory array, configured to store data (Fig 1, XRD DRAM 13); and
a controller circuit (Fig 1, STR Control Circuit 14, Memory Control Circuit 12, System Controller 11), coupled to the memory array and configured to receive a reset signal and a trigger signal, wherein the controller circuit performs a reset operation according to the reset signal, and the controller circuit maintains a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level; ¶[0042] – “The system controller 11 sets the GPO1 terminal (RST) to the low level in response to the low level of the GP10 terminal”).
KOMAKI may not explicitly disclose the trigger signal comprising a time length of a first voltage level.
However, LIN discloses the trigger signal comprising a time length of a first voltage level (¶[0024] – “the micro-control unit 34 outputs a trigger signal Trigger having a pulse width of a minimum value”).
KOMAKI and LIN are analogous art because they are from the same field of endeavor of controlling an application circuit. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI and LIN before him or her, to modify the generation of the GPO1 signal of KOMAKI to include a micro-control circuit as taught by LIN. A motivation for doing so would have been to avoid an erroneous result that may occur due to signal noise such that the signal is correctly interpreted (¶[0026]). Therefore, it would have been obvious to combine KOMAKI and LIN to obtain the invention as specified in the instant claims.
With respect to Claim 9, KOMAKI discloses a method for operating a memory storage apparatus, wherein the memory storage apparatus comprises a memory array (Fig 1, XRD DRAM 13), the method for operating comprising:
receiving a reset signal (Fig 2, RST of Memory Controller 12) and a trigger signal (Fig 2, GP01);
performing a reset operation according to the reset signal; and
maintaining a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level; ¶[0042] – “The system controller 11 sets the GPO1 terminal (RST) to the low level in response to the low level of the GP10 terminal”).
KOMAKI may not explicitly disclose the trigger signal comprising a time length of a first voltage level.
However, LIN discloses the trigger signal comprising a time length of a first voltage level (¶[0024] – “the micro-control unit 34 outputs a trigger signal Trigger having a pulse width of a minimum value”).
KOMAKI and LIN are analogous art because they are from the same field of endeavor of controlling an application circuit. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI and LIN before him or her, to modify the generation of the GPO1 signal of KOMAKI to include a micro-control circuit as taught by LIN. A motivation for doing so would have been to avoid an erroneous result that may occur due to signal noise such that the signal is correctly interpreted (¶[0026]). Therefore, it would have been obvious to combine KOMAKI and LIN to obtain the invention as specified in the instant claims.
With respect to Claim 16, KOMAKI discloses a memory storage apparatus, comprising:
a memory array (Fig 1, XRD DRAM 13), configured to store data; and
a controller circuit (Fig 2, RST of Memory Controller 12), coupled to the memory array and configured to receive a reset signal (Fig 2, GP01), wherein the reset signal is used as a trigger signal, and
wherein the controller circuit performs a reset operation according to the reset signal, and the controller circuit maintains a power supply to the memory array according to the trigger signal during a reset period (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level).
KOMAKI may not explicitly disclose the trigger signal comprising a time length of a first voltage level.
However, LIN discloses the trigger signal comprising a time length of a first voltage level (¶[0024] – “the micro-control unit 34 outputs a trigger signal Trigger having a pulse width of a minimum value”).
KOMAKI and LIN are analogous art because they are from the same field of endeavor of controlling an application circuit. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI and LIN before him or her, to modify the generation of the GPO1 signal of KOMAKI to include a micro-control circuit as taught by LIN. A motivation for doing so would have been to avoid an erroneous result that may occur due to signal noise such that the signal is correctly interpreted (¶[0026]). Therefore, it would have been obvious to combine KOMAKI and LIN to obtain the invention as specified in the instant claims.
With respect to Claims 2 and 10, the combination of KOMAKI and LIN disclose the apparatus/method according to each respective parent claim.
KOMAKI further discloses performing a self-refresh operation on the memory array after executing the reset operation (¶[0049] – “ the memory controller 12 firmware executes "Power-down Sequence" of the XDR DRAM 13. As a result, the XDR DRAM 13 is brought into a self-refresh mode with less power consumption”).
With respect to Claims 5 and 13, the combination of KOMAKI and LIN disclose the apparatus/method according to each respective parent claim.
KOMAKI further discloses wherein the trigger signal is a combination of an external signal input to a pin of the memory storage apparatus (Fig 2, GP01 drives RST input of each DRAMx).
With respect to Claims 6 and 14, the combination of KOMAKI and LIN disclose the apparatus/method according to each respective parent claim.
KOMAKI further discloses wherein the combination of the external signal comprises signal type or voltage level (Fig 2, GP01 drives RST input of each DRAMx).
Claim(s) 3, 8, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOMAKI in further view of LIN and ISHIHARA (US PGPub 2005/0283572).
With respect to Claims 3 and 11 the combination of KOMAKI and LIN disclose the apparatus/method according to each respective parent claim.
KOMAKI and LIN may not explicitly disclose stopping the self-refresh operation according to a reference signal.
However, ISHIHARA discloses stopping the self-refresh operation according to a reference signal (¶[0047] – “the CPU 11 issues a self-refresh release command to the DRAM control circuit 15. At time T13, the DRAM control circuit 15 outputs a clock control signal CKEI at a low level, and outputs a chip select signal CSI, a row address select signal RASI, a column address select signal CASI, a write control signal WEI, and data output mask signals DQMI3 to DQMI0 at a high level, on the basis of the self-refresh release command. The self-refresh state of the SDRAM 40 is thereby released.”).
KOMAKI, LIN, and ISHIHARA are analogous art because they are from the same field of endeavor of management and control of volatile memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI, LIN, and ISHIHARA before him or her, to modify the controller of the combination of KOMAKI and LIN to include controlling start and release self-refresh mode signals as taught by ISHIHARA. A motivation for doing so would have been to enable the interruption and resuming of application programs (¶0048]) which may be performed for power-saving purposes. Therefore, it would have been obvious to combine KOMAKI, LIN, and ISHIHARA to obtain the invention as specified in the instant claims.
With respect to Claim 8, the combination of KOMAKI and LIN disclose the memory storage apparatus according to claim 1.
KOMAKI further discloses a power supply circuit, coupled to the memory array and the controller circuit, and configured to provide a power supply to the memory array during the reset period (¶[0049] – “ the memory controller 12 firmware executes "Power-down Sequence" of the XDR DRAM 13. As a result, the XDR DRAM 13 is brought into a self-refresh mode with less power consumption”).
KOMAKI and LIN may not explicitly disclose wherein the power supply circuit determines whether to maintain the power supply to the memory array during the reset period according to a command of the controller circuit.
However, ISHIHARA discloses wherein the power supply circuit determines whether to maintain the power supply to the memory array during the reset period according to a command of the controller circuit (¶[0047] – “the CPU 11 issues a self-refresh release command to the DRAM control circuit 15. At time T13, the DRAM control circuit 15 outputs a clock control signal CKEI at a low level, and outputs a chip select signal CSI, a row address select signal RASI, a column address select signal CASI, a write control signal WEI, and data output mask signals DQMI3 to DQMI0 at a high level, on the basis of the self-refresh release command. The self-refresh state of the SDRAM 40 is thereby released.”).
Claim(s) 4, 7, 12, 15, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOMAKI in further view of LIN and PALMER (US PGPub 2020/0210073).
With respect to Claims 4 and 12, the combination of KOMAKI and LIN disclose the apparatus/method according to each respective parent claim.
KOMAKI and LIN may not explicitly disclose wherein the self-refresh operation is performed on the memory array after the reset period is greater than a preset time length.
However, PALMER discloses wherein the self-refresh operation is performed on the memory array after the reset period is greater than a preset time length (¶[0023] – “ the control logic 150 can also include one or more circuits to initialize the timer 155 with an indicated value, such as a number of timer ticks or units of time that must pass before the reset logic 145 executes a reset”).
KOMAKI, LIN, and PALMER are analogous art because they are from the same field of endeavor of management and control of volatile memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of KOMAKI, LIN, and PALMER before him or her, to modify the controller of the combination of KOMAKI and LIN to include a timer circuit controlling a reset signal as taught by PALMER. A motivation for doing so would have been to cause the storage device to execute a reset even when a storage controller is deadlocked or otherwise malfunctioning (¶[0029]). Therefore, it would have been obvious to combine KOMAKI, LIN, and PALMER to obtain the invention as specified in the instant claims.
With respect to Claims 7, 15, 17, and 18, the combination of KOMAKI and LIN disclose the apparatus/methods according to each respective parent claim.
KOMAKI further discloses wherein the trigger signal comprises a second reset signal (Abstract – “When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.”. The signal provided from the memory controller to the system controller analogous to ‘the reset signal’ as the signal initiates a ‘Cold Boot’ mode {Fig 3} and a ‘Enter-To-Suspend’/’Warm Boot’ mode {Figs 4 and 5}. ¶[0076]; ¶[0031] - The GPO1 signal provided by the system controller analogous to ‘the trigger signal’ as the signal resets DRAMs or suspends the DRAMs based on the terminal level).
KOMAKI and LIN may not explicitly disclose a time length of the second reset signal is used to determine whether to trigger an operation of maintaining the power supply to the memory array during the reset period.
However, PALMER discloses a time length of the second reset signal is used to determine whether to trigger an operation of maintaining the power supply to the memory array during the reset period (¶[0023] – “ the control logic 150 can also include one or more circuits to initialize the timer 155 with an indicated value, such as a number of timer ticks or units of time that must pass before the reset logic 145 executes a reset”).
Conclusion
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/ERIC T LOONAN/Primary Examiner, Art Unit 2137
