Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 12, and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Regarding Claim 1:
Ambiguous Structure: The claim recites “wherein the first processor and the second processor each comprise: a plurality of function blocks; a first interface circuit… a second interface circuit… a bridge circuit…” It is unclear if the electronic device includes two separate bridge circuits (one in each processor) or a single shared bridge circuit. Later, the claim recites “the bridge circuit is configured to…” (singular), which creates confusion regarding the physical architecture being claimed.
Confusing Terminology: The claim recites “in response to receiving a bus command of the second interface scheme that comprises a security indicator, convert, address information in the received bus command to comprise security information.” It is unclear if the “security indicator” and “security information” are the same element or distinct elements. Furthermore, the punctuation (“convert, address information”) renders the sentence grammatically confusing.
Lack of Antecedent Basis and Contradiction: The claim recites “convert an external address, comprised in the address information with the security information removed, to an internal address…”
There is no antecedent basis for “an external address” or “an internal address.”
The phrase “with the security information removed” lacks antecedent basis and logically contradicts the preceding limitation. The previous step explicitly requires converting the address information to comprise (i.e., add or include) security information. There is no intervening step where the security information is removed, making it impossible to understand the state of the data packet at this stage.
Regarding Claim 12:
Lack of Antecedent Basis for Processors: The preamble recites a method for controlling an electronic device comprising “a plurality of processors.” However, the final limitation recites converting an address to an internal address of “one of the first processor and the second processor.” There is no antecedent basis in the claim for a “first processor” or a “second processor.”
Contradictory Triggers: The claim recites a first step of “receiving… a bus command of a second interface scheme.” Immediately following this, the claim recites “in response to receiving a bus command of the first interface scheme, converting address information in the received bus command.” It is entirely unclear which bus command is being converted. The phrase “the received bus command” appears to refer to the command of the second interface scheme, but the action is triggered by receiving a command of the first interface scheme.
Repetitive/Conflicting Limitations: The claim recites the conditional phrase “in response to receiving a bus command of the first interface scheme” twice in the same claim, applying completely different actions to each instance. It is unclear if the method requires receiving two separate commands of the first interface scheme, or if this is a typographical error intended to refer to the second interface scheme.
Grammatical Awkwardness: The claim recites “outputting… by converting the received bus command…” It is unclear how the act of outputting is performed by converting.
Missing Antecedent Basis for Address States: Similar to Claim 1, the final limitation recites “an external address,” “an internal address,” and “with the security information removed” without any prior introduction or antecedent basis in the method steps.
Regarding Claim 14:
Lack of Antecedent Basis for Processors: Like Claim 12, the preamble recites “a plurality of processors,” but the final limitation introduces “the first processor and the second processor” without antecedent basis.
Lack of Antecedent Basis for Security Indicator: The claim recites “based on determining the bus command as having a security indicator indicating that the bus command is a request requiring security.” There is no antecedent basis for a “security indicator.” The preceding limitations only discuss “security information.” It is unclear if these terms are intended to be interchangeable.
Repetitive Triggers: The claim begins with the step of “receiving a bus command of a first interface scheme.” Later, it recites “and in response to receiving a bus command of the first interface scheme, converting an external address…” It is unclear if this latter limitation refers back to the initially received bus command from step one, or if it introduces a second, separate bus command.
Missing Antecedent Basis for Address States: The claim recites “converting an external address… to an internal address” without antecedent basis for either term.
Convoluted Syntax: The limitation “converting and outputting the bus command, based on determining the bus command as having a security indicator… and the address information, with the security information removed, through a second interface scheme” is grammatically disjointed. It is unclear if the bus command and the address information are outputted as separate entities, or if the address information is a component of the outputted bus command.
Here are suggested amendments for independent claims 1, 12, and 14 that would resolve the 35 U.S.C. § 112(b) indefiniteness issues identified above. Please note that adopting these suggestions overcomes the § 112(b) rejections but does not overcome the § 103 prior art rejections below.
Suggested Amendments to Overcome 35 U.S.C. § 112(b)
Claim 1: An electronic device comprising: a first processor; a second processor; and wherein the first processor comprises: a plurality of function blocks; a first interface circuit configured to transfer a bus command between the first processor and the second processor through a first interface scheme; a second interface circuit configured to transfer a bus command between the plurality of function blocks through a second interface scheme different from the first interface scheme; a bridge circuit configured to convert data format through any of the first interface scheme and the second interface scheme, wherein the bridge circuit is configured to: in response to receiving a first bus command of the second interface scheme that comprises a security indicator, convert address information in the received first bus command to comprise security information; output to the first interface circuit by converting the first bus command having the converted address information through the first interface scheme; and in response to receiving a second bus command of the first interface scheme comprising an external address and security information, remove the security information, and convert the external address with the security information removed, to an internal address of one of the first processor and the second processor.
Claim 12: A method for controlling an electronic device comprising a plurality of processors including a first processor and a second processor, the method comprising: receiving, through a second interface circuit in a processor of the plurality of processors, a first bus command of a second interface scheme comprising a security indicator; in response to receiving the first bus command of the second interface scheme, converting address information in the received first bus command to comprise security information; outputting, to a first interface circuit in the electronic device, first bus command comprising the converted address information through a first interface scheme; and in response to receiving a second bus command of the first interface scheme comprising an external address and security information, removing the security information, and converting the external address
Claim 14: A method for controlling an electronic device comprising a plurality of processors including a first processor and a second processor, the method comprising: receiving a bus command of a first interface scheme comprising an external address and security information; confirming the security information of the bus command based on a pre-set bit location from among a plurality of bits that configure address information in the received bus command; removing the security information from the address information based on determining that the bus command is confirmed as information requiring security; converting and outputting the bus command, based on determining the bus command as having a security indicator indicating that the bus command is a request requiring security, and the address information, with the security information removed, through a second interface scheme; and the external address, comprised in the address information with the security information removed, to an internal address of one of the first processor and the second processor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Arberl et al.(WO 2016007358), referred hereon Arberl in view of Byrne et al. (U.S. patent 8,489,791), hereinafter referred to as Byrne.
Regarding Claim 1, Arberl teaches an electronic device (Arberl, FIG. 1, System 100), comprising:
a first processor; a second processor; and wherein the first processor and the second processor each comprise: a plurality of function blocks; Arberl teaches a first set of master and slave circuits 102 and a second set of master and slave circuits 112, wherein the master circuits include microprocessors and DSPs having various logic and function blocks (Arberl, FIG. 1; FIG. 3 showing CLBs 302 and DSPs 306).
a first interface circuit configured to transfer a bus command between the first processor and the second processor through a first interface scheme; Arberl teaches a second bus 110 (e.g., PCIe) and bus controller 108 transferring access requests (bus commands) (Arberl, FIG. 1).
a second interface circuit configured to transfer a bus command between the plurality of function blocks through a second interface scheme different from the first interface scheme; Arberl teaches a first bus 104 utilizing a different protocol/interface scheme (e.g., AXI) transferring access requests (Arberl, FIG. 1).
a bridge circuit configured to convert data format through any of the first interface scheme and the second interface scheme, Arberl teaches a bridge circuit 106 that translates requests between the first bus 104 and the second bus 110 (Arberl, FIG. 1).
wherein the bridge circuit is configured to: in response to receiving a bus command of the second interface scheme that comprises a security indicator, convert, address information in the received bus command to comprise security information; output to the first interface circuit by converting the bus command having the converted address information through the first interface scheme; Under BRI, Arberl teaches an ingress circuit 124 that receives access requests from the non-secure second bus 110 which include a requested address 152. The ingress circuit 124 translates the requested address 152 into a translated address 154 using address range maps 126, and communicates the translated address 154 along with a security indicator 156 to the secure first bus 104 (Arberl, FIG. 1). (Note: Translating an address and appending a security indicator to the translated request reads on “converting address information to comprise security information”).
and in response to receiving a bus command of the first interface scheme, convert an external address, comprised in the address information with the security information removed, to an internal address of one of the first processor and the second processor. Arberl teaches an egress circuit 122 that receives an access request from the secure first bus 104 including a requester security indicator 142 and an address 144. The egress circuit 122 translates the address (converting between external/internal address spaces) and outputs the translated address 146 to the non-secure second bus 110 (Arberl, FIG. 1).
While Arberl teaches translating the request from a secure protocol to a non-secure protocol, it does not explicitly detail the mechanical removal of the security information from the converted address packet.
Byrne teaches a bus bridge 306 between a first interface scheme (AXI bus 304) and a second interface scheme (PLB 310) that performs a Write/Read Access Security Check using an identification/security field (AWID/ARID 622) attached to the incoming address (Byrne, FIG. 4; FIG. 6; FIG. 9, WASC block 904; Paragraphs [117]-[121]). Byrne teaches that once the request is validated, the bridge generates the converted command and address for the destination bus. Because the destination bus protocol utilizes different packet structures, the original AXI identification/security field is stripped and removed from the converted address/command (Byrne, FIG. 5, PCC command pipeline 542; Paragraph [90], teaching the generated command includes the address and byte enable parity, omitting the AWID; Paragraphs [101]-[102], teaching the ID is used internally for ordering/security but not passed to the destination bus).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to incorporate the granular access security check and protocol conversion mechanism of Byrne into the bridge circuit 106 of Arberl. The motivation to do so would be to provide more robust, hardware-enforced security at the bridge by allowing or denying specific master devices access to specific memory addresses (as taught by Byrne, Paragraph [7]), and to ensure strict protocol compatibility by actively removing the unsupported security/ID bits when formatting the converted address for the destination bus to avoid transmission errors.
Regarding Claims 2 and 13, Arberl teaches the security information is provided as a distinct signal/bit indicator alongside the address (Arberl, FIG. 1, showing Requester Security Indicator 142 and Security Indicator 156). Byrne further teaches that the security/identification information occupies specific pre-set bit fields within the command structure (AWID/ARID 622) (Byrne, FIG. 6; Paragraphs [118]-[119]).
Regarding Claim 3, Arberl illustrates the security indicator as a singular discrete input/output line (Arberl, FIG. 1, elements 142, 156), and it would have been obvious to implement this indicator as a bit size of one to efficiently flag secure versus non-secure status.
Regarding Claim 4, Arberl teaches configuring the bridge via a configuration input (Arberl, FIG. 1, Configuration 130). Byrne further teaches a register configured to store information on the bit locations and masks, specifically teaching General Control and Status registers (GCS) 440 and access tables 902 that store masks (TADDRM, SMIDM) to identify and evaluate the specific bit locations for security checks (Byrne, FIG. 5; FIG. 9; Paragraph [118]).
Regarding Claim 17, Byrne teaches the function block is configured to change the pre-set bit location/configuration, teaching that the GCS 440 registers are programmable and “may be modified over the Device Control Register Slave channel (DCR_S) 434 to reconfigure the bridge 306” (Byrne, FIG. 4; FIG. 5; Paragraph [46]; Paragraph [112]).
Regarding Claims 5, 18, and 19, Arberl teaches utilizing address range maps (Arberl, FIG. 1, Address Range Maps 126). Byrne teaches programming the bridge via the DCR_S channel 434 to set specific address ranges and master IDs in the configuration registers (GCS 440) to define where security checks apply (Byrne, FIG. 5; Paragraphs [46], [112], [118]). It would have been obvious to a person of ordinary skill in the art that configuring these memory-mapped registers inherently requires confirming which address values are available (not being used by other system resources) to determine the appropriate bit locations for the security data, thereby avoiding memory conflicts.
Regarding Claim 6, Byrne teaches transmitting this configuration information between processors, teaching that the configuration registers are “accessed by privileged configuration transactions via channel 434 from a host processor” (Byrne, FIG. 4; Paragraph [118]).
Regarding Claim 7, Arberl teaches the egress circuit 122 evaluates the address 144 and requester indicator 142, and translates/outputs the command as translated address 146 to the second bus 110 (Arberl, FIG. 1). As established in the independent claims, Byrne teaches removing the security information via PCC command pipeline 542 during this conversion (Byrne, FIG. 5; Paragraph [90]).
Regarding Claims 8 and 15, Arberl teaches the egress circuit 122 processes requests from the first bus 104 to the second bus 110 (Arberl, FIG. 1). It would have been obvious that requests lacking the security requirement (non-secure requests) are similarly translated and outputted to the second bus 110 to maintain general system communication.
Regarding Claim 10, Arberl teaches master and slave circuits 102, 112 communicating through the bridge 106 (Arberl, FIG. 1). Byrne further teaches a memory manager block (MMB) 140 and teaches the bridge 306 determines whether to allow access to specific memory areas using the security indicator (SMID) and access table 902 (Byrne, FIG. 1; FIG. 9; Paragraphs [24], [113]-[114]).
Regarding Claim 11, Arberl teaches bridging a first bus 104 and a second bus 110 (Arberl, FIG. 1). Byrne explicitly teaches the exact interface schemes claimed, teaching a bridge architecture that connects an Advanced eXtensible Interface (AXI) bus 304 and further teaches a Peripheral Component Interconnect Express (PCI-E) interface 308 for external processor communication (Byrne, FIG. 3; Paragraph [32]). It would have been obvious to implement Arberl’s first and second buses 104, 110 as AXI and PCIe schemes as taught by Byrne to standardize communication.
Regarding Claim 12, Arberl teaches a method for controlling an electronic device comprising a plurality of processors, the method comprising:
Arberl teaches a method of bridging communication in an electronic device (Arberl, FIG. 1, System 100) comprising a plurality of processors, such as master and slave circuits 102, 112 which include microprocessors and DSPs (Arberl, FIG. 1; FIG. 3 showing CLBs 302 and DSPs 306; Paragraph [0018]).
receiving, through a second interface circuit in a processor of the plurality of processors, a bus command of a second interface scheme comprising a security indicator;
Arberl teaches receiving an access request (bus command) from a secure first bus 104 (second interface scheme, e.g., AXI) that includes a requester security indicator 142 (Arberl, FIG. 1; Paragraph [0021]).
in response to receiving a bus command of the first interface scheme, converting address information in the received bus command to comprise security information; outputting, to a first interface circuit in the electronic device, by converting the received bus command comprising the converted address information through a first interface scheme;
Under BRI, Arberl teaches receiving an access request from a non-secure second bus 110 (first interface scheme, e.g., PCIe) which includes a requested address 152. The ingress circuit 124 translates the requested address 152 into a translated address 154 using address range maps 126, and outputs the translated address 154 along with a security indicator 156 to the secure bus 104 (Arberl, FIG. 1; Paragraph [0022]). (Note: Translating an address and appending a security indicator to the translated request reads on “converting address information to comprise security information”).
and in response to receiving a bus command of the first interface scheme, converting an external address, comprised in the address information with the security information removed, to an internal address of one of the first processor and the second processor.
Arberl teaches an egress circuit 122 that receives an access request from the secure bus 104 which includes a requester security indicator 142 and an address 144. The egress circuit 122 translates the address into a translated address 146 for the non-secure bus 110 (Arberl, FIG. 1; Paragraph [0021]). Arberl teaches that the non-secure bus does not support the security mechanisms of the secure bus, meaning the translated request lacks the security indicator.
While Arberl teaches translating the request from a secure protocol to a non-secure protocol, it does not explicitly detail the mechanical removal of the security information from the converted address packet.
Byrne teaches a bus bridge (306) between a first interface scheme (AXI) and a second interface scheme (PLB) that performs a Write/Read Access Security Check using an identification/security field (AWID/ARID) attached to the incoming address (Byrne, Paragraphs [117]-[121]). Byrne teaches that once the request is validated, the bridge generates the converted command and address for the destination bus. Because the destination bus protocol utilizes different packet structures, the original AXI identification/security field is stripped and removed from the converted address/command (Byrne, Paragraph [90], teaching the generated command includes the address and byte enable parity, omitting the AWID; Paragraphs [101]-[102], teaching the ID is used internally for ordering/security but not passed to the destination bus).
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to incorporate the granular access security check and protocol conversion mechanism of Byrne into the method of Arberl. The motivation to do so would be to provide more robust, hardware-enforced security at the bridge by allowing or denying specific master devices access to specific memory addresses (as taught by Byrne, Paragraph [7]), and to ensure strict protocol compatibility by actively removing the unsupported security/ID bits when formatting the converted address for the destination bus to avoid transmission errors.
Regarding Claim 14, Arberl teaches a method for controlling an electronic device comprising a plurality of processors, the method comprising:
Arberl teaches a method of bridging communication in an electronic device (Arberl, FIG. 1, System 100) comprising a plurality of processors, such as master and slave circuits 102, 112, CLBs 302, and DSPs 306 (Arberl, FIG. 1; FIG. 3).
receiving a bus command of a first interface scheme;
Arberl teaches receiving an access request (bus command) from a secure first bus 104 (Arberl, FIG. 1).
confirming security information of the bus command based on a pre-set bit location from among a plurality of bits that configure address information in the received bus command;
Arberl teaches receiving the access request which includes an address 144 and a requester security indicator 142 (Arberl, FIG. 1).
Byrne further details this process, teaching that the bridge 306 receives a command having an address field and an identification/security field comprising specific pre-set bit locations (AWID/ARID 622) and confirms the security information by comparing these bits against an access table 902 via WASC block 904 to determine if the command is allowed (Byrne, FIG. 6; FIG. 9; Paragraphs [117]-[121]).
removing the security information from the address information based on determining that the bus command is confirmed as information requiring security;
Byrne teaches that once the security check is validated (confirmed), the bridge 306 generates the converted command via PCC command pipeline 542 with the original AXI identification/security field (AWID/ARID 622) stripped and removed (Byrne, FIG. 5; Paragraphs [90], [101]-[102]).
converting and outputting the bus command, based on determining the bus command as having a security indicator indicating that the bus command is a request requiring security, and the address information, with the security information removed, through a second interface scheme;
Arberl teaches that based on the requester security indicator 142, the egress circuit 122 translates (converts) the access request and communicates (outputs) the translated address 146 to the second bus 110 (Arberl, FIG. 1). As modified by Byrne, this outputted command has the security information removed via the PCC command pipeline 542 to comply with the destination bus protocol (Byrne, FIG. 5; Paragraph [90]).
and in response to receiving a bus command of the first interface scheme, converting an external address, comprised in the address information with the security information removed, to an internal address of one of the first processor and the second processor.
Arberl teaches that during the translation process via egress circuit 122 and ingress circuit 124, the address is converted between the address space of the first bus 104 and the address space of the second bus 110 (Arberl, FIG. 1). As modified by Byrne, the converted address packet has the security information removed.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to incorporate the granular access security check (using specific ID bit locations) and the protocol conversion mechanism of Byrne into the method of Arberl. The motivation to do so would be to provide more robust, hardware-enforced security at the bridge by allowing or denying specific master devices access to specific memory addresses (as taught by Byrne, Paragraph [7]), and to ensure strict protocol compatibility by actively removing the unsupported security/ID bits when formatting the converted address for the destination bus to avoid transmission errors.
Regarding Claim 16, Arberl teaches converting the address information to comprise the security information by outputting the translated address 154 alongside the security indicator 156 (Arberl, FIG. 1). Byrne teaches the specific bit locations (AWID/ARID 622) used to embed this security information into the command structure (Byrne, FIG. 6). It would have been obvious to embed the security indicator at the determined bit location to comply with the strict packet formatting rules of the secure bus protocol.
Response to Arguments
Though reference Morais is withdrawn from rejection but applicant argues that that Byrne operates entirely within a single network processor chip and therefore does not teach converting an external address to an internal address between separate processors via an external interface scheme (e.g., PCIe) as claimed.
This argument is not persuasive for the following reasons:
Byrne explicitly teaches communication with external processors via PCIe. Even if evaluated individually, Applicant argues that Byrne operated solely within a closed, internal chip environment. Examiner respectfully disagrees. Byrne explicitly teaches that bridge architecture is designed to facilitate communication between internal processors and external processors via an external interface scheme. Specifically, Byrne teaches a PCI-E interface 308 that “allows for any external device operating in conformance with the PCI-E protocol to be attached to Network Processor 100… [and] allow one or more external processors to access shared memory 110” (Byrne, Paragraph [30]; FIG. 3). Byrne further teaches that the bridge 306 “allows processors 114_1-114_M to communicate with AXI bus 304, and thus external processors (via AXI-to-PCI-E controller 308)” (Byrne, Paragraph [32]). Therefore, Byrne explicitly contemplates and teaches that the address conversion occurring at the bridge facilitates communication between external processors (via PCIe) and internal processors.
As for the 103 rejection for combining of Byrne to Arbel is a new ground of rejection. The Examiner relies on Arberl as the primary reference to teach the external-to-internal address conversion. Arberl explicitly teaches a bridge circuit that translates requests between a first bus (AXI) and a second bus (PCIe) (Arberl, Paragraph [0019]). Arberl explicitly teaches translating an address from the address space of the second bus (the “remote base address” / external PCIe address) to an address in the address space of the first bus (the “local base address” / internal AXI address) (Arberl, Paragraphs [0021]-[0022]). Therefore, the primary reference Arberl explicitly teaches the external-to-internal address conversion via an external interface scheme (PCIe).
Conclusion: When Arberl and Byrne are read together, the combination explicitly teaches receiving a bus command from an external interface scheme (PCIe), stripping/removing the security information as taught by Byrne, and converting the external remote address to an internal local address for the destination processor as taught by both Arberl and Byrne.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tim Vo whose telephone number is (571)272-3642. The examiner can normally be reached on Monday-Thursday 5:30 AM – 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on (571)272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/www.uspto.gov/interviewpractice.
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/TIM T VO/Supervisory Patent Examiner, Art Unit 2138
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