DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21 – 40 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 23, 25 – 30, 32- 40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ghose (US20070067595).
As to claim 21, Ghoose discloses a method comprising: selecting, from a range of latency values, a target latency for executing input/output (I/O) operations based on a queue depth of a queue that includes a plurality of I/O operations (Fig. 1, and steps 105, 110, and 115, where a latency in the form of a priority is chosen to enable the I/O operation, para. 0025); and performing one or more I/O operations of the plurality of I/O operations according to a throughput value that is determined based on the selected target latency (Fig. 1, and step 135 where operations occur, para. 0026).
As to claims 22, 29, and 36, Ghoose discloses the method, wherein selecting the target latency comprises evaluating a latency function that scales between a maximum target latency and a minimum target latency based on a queue depth (Fig. 2, and step 215 where all requests are tested, (paras. 0070 – 0075).
As to claims 23, 30, and 37, Ghoose discloses the method, wherein the latency function is a power function that intercepts the maximum target latency and the minimum target latency (Fig. 2, and step 245 where an appropriate level is found, (para. 0074) .
As to claims 25, 32, and 39, Ghoose discloses the method, further comprising determining the target latency based on the latency function and a current queue depth (Fig.1, and para. 0024, where the target latency is chosen based on queue depth).
As to claims 26, 33, and 40, Ghoose discloses the method, further comprising determining a throughput value corresponding to the target latency for writing to at least one storage device (Fig. 1, and step 135, para. 0068).
As to claims 27, and 34, Ghoose discloses the method, wherein the throughput value is selected to ensure that write operations in the queue complete within the target latency (Fig. 1, and step 130, para. 0068).
As to claim 28, Ghoose discloses an apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus (Fig. 1 operates on a system, comprising a computer, and related memory system, para. 0005) to: select, from a range of latency values, a target latency for executing input/output (I/O) operations based on a queue depth of a queue that includes a plurality of I/O operations (Fig. 1, and steps 105, 110, and 115, where a latency in the form of a priority is chosen to enable the I/O operation, para. 0025); and perform one or more I/O operations of the plurality of I/O operations according to a throughput value that is determined based on the selected target latency (Fig. 1, and step 135 where operations occur, para. 0026).
As to claim 35, Ghoose discloses a computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions (Fig. 1 operates on a system, comprising a computer, and related memory system, para. 0005) that, when executed, cause a computer to: select, from a range of latency values, a target latency for executing input/output (I/O) operations based on a queue depth of a queue that includes a plurality of I/O operations (Fig. 1, and steps 105, 110, and 115, where a latency in the form of a priority is chosen to enable the I/O operation, para. 0025); and perform one or more I/O operations of the plurality of I/O operations according to a throughput value that is determined based on the selected target latency (Fig. 1, and step 135 where operations occur, para. 0026).
Allowable Subject Matter
Claims 24, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20160196231, US20170351437, and US20160119443, among others teach the management of latency in a computing system.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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