DETAILED ACTION
Claims Objections
Claims 3 and 15 are objected to because there are two periods (.) in each claim (end of line #6 [Wingdings font/0xE0] “…between the second resistor and ground.”). Correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,203,965. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced in a table below for comparison.
Claim No.: __ of USP 12,203,965
Claim No.: __ of application 19/019,895
1. An impedance sensing circuit comprising: a first current source operably coupled and configured, based on a digital signal, to output a first current signal to a first node that is operably coupled to a first terminal of a Wheatstone bridge; a second current source operably coupled and configured, based on the digital signal, to output a second current signal to a second node that is operably coupled to second terminal of the Wheatstone bridge; a comparator operably coupled to the first current source and the second current source, wherein, when enabled, the comparator configured to: receive a first voltage based on the first terminal of the Wheatstone bridge via a first input of the comparator; receive a second voltage based on the second terminal of the Wheatstone bridge via a second input of the comparator; and compare the first voltage to the second voltage to generate a comparator output signal; and a digital circuit operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate the digital signal, wherein the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference associated with the Wheatstone bridge.
1. An impedance sensing circuit comprising: a first current source operably coupled and configured, based on a digital signal, to output a first current signal to a first node that is operably coupled to a first terminal of a Wheatstone bridge; a second current source operably coupled and configured, based on the digital signal, to output a second current signal to a second node that is operably coupled to second terminal of the Wheatstone bridge; a digital comparator operably coupled to the first current source and the second current source, wherein, when enabled, the digital comparator configured to: receive a first voltage based on the first terminal of the Wheatstone bridge via a first input of the digital comparator; receive a second voltage based on the second terminal of the Wheatstone bridge via a second input of the digital comparator; and compare the first voltage to the second voltage to generate the digital signal, wherein the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference associated with the Wheatstone bridge.
2. The impedance sensing circuit of claim 1 further comprising: memory that stores operational instructions; and one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the digital signal to determine the impedance difference associated with the Wheatstone bridge.
2. The impedance sensing circuit of claim 1 further comprising: memory that stores operational instructions; and one or more processing modules operably coupled to the digital comparator and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the digital signal to determine the impedance difference associated with the Wheatstone bridge.
3. The impedance sensing circuit of claim 2, wherein the Wheatstone bridge further comprising: a first resistor; a second resistor connected to the first resistor; a third resistor connected between the first resistor and ground; a fourth resistor connected between the second resistor and ground; the second terminal of the Wheatstone bridge based on connection between the first resistor and the third resistor; and the second terminal of the Wheatstone bridge based on connection between the second resistor and the fourth resistor.
3. The impedance sensing circuit of claim 2, wherein the Wheatstone bridge further comprising: a first resistor; a second resistor connected to the first resistor; a third resistor connected between the first resistor and ground; a fourth resistor connected between the second resistor and ground [.] the second terminal of the Wheatstone bridge based on connection between the first resistor and the third resistor; and the second terminal of the Wheatstone bridge based on connection between the second resistor and the fourth resistor.
4. The impedance sensing circuit of claim 3, wherein: the first resistor, the second resistor, and the third resistor have a first resistance value; the fourth resistor has a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
4. The impedance sensing circuit of claim 3, wherein: the first resistor, the second resistor, and the third resistor have a first resistance value; the fourth resistor has a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
5. The impedance sensing circuit of claim 3, wherein: the first resistor and the third resistor have a first resistance value; and the second resistor and the fourth resistor have a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
5. The impedance sensing circuit of claim 3, wherein: the first resistor and the third resistor have a first resistance value; and the second resistor and the fourth resistor have a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
6. The impedance sensing circuit of claim 3 further comprising: a bias current source that is operably coupled to connection between the first resistor and the second resistor and configured to output a bias current signal.
6. The impedance sensing circuit of claim 3 further comprising: a bias current source that is operably coupled to connection between the first resistor and the second resistor and configured to output a bias current signal.
7. The impedance sensing circuit of claim 6 further comprising: a reference current source that is operably coupled to another node that couples to inputs of the first current source and the second current source and configured to output a reference current signal, wherein sensitivity of the digital signal is based on a ratio of the bias current signal to the reference current signal.
7. The impedance sensing circuit of claim 6 further comprising: a reference current source that is operably coupled to another node that couples to inputs of the first current source and the second current source and configured to output a reference current signal, wherein sensitivity of the digital signal is based on a ratio of the bias current signal to the reference current signal.
8. The impedance sensing circuit of claim 1 further comprising: a capacitor that is operably coupled between the first input of the comparator and the second input of the comparator.
8. The impedance sensing circuit of claim 1 further comprising: a capacitor that is operably coupled between the first input of the digital comparator and the second input of the digital comparator.
9. The impedance sensing circuit of claim 1 further comprising: a first capacitor that is operably coupled to the first input of the comparator; and a second capacitor that is operably coupled to the second input of the comparator.
9. The impedance sensing circuit of claim 1 further comprising: a first capacitor that is operably coupled to the first input of the digital comparator; and a second capacitor that is operably coupled to the second input of the digital comparator.
10. The impedance sensing circuit of claim 1, wherein: the first current signal and the second current signal are regulated based on the digital signal to ensure that the first voltage is same as the second voltage.
10. The impedance sensing circuit of claim 1, wherein: the first current signal and the second current signal are regulated based on the digital signal to ensure that the first voltage is same as the second voltage.
11. The impedance sensing circuit of claim 1 further comprising: a first buffer operably coupled between the first node and the first terminal of the Wheatstone bridge; and a second buffer operably coupled between the second node and the second terminal of the Wheatstone bridge.
11. The impedance sensing circuit of claim 1 further comprising: a first buffer operably coupled between the first node and the first terminal of the Wheatstone bridge; and a second buffer operably coupled between the second node and the second terminal of the Wheatstone bridge.
12. An impedance sensing circuit comprising: a first current source operably coupled and configured, based on a comparator output signal, to output a first current signal to a first node that is operably coupled to a first terminal of a Wheatstone bridge; a second current source operably coupled and configured, based on the comparator output signal, to output a second current signal to a second node that is operably coupled to second terminal of the Wheatstone bridge; a comparator operably coupled to the first current source and the second current source, wherein, when enabled, the comparator configured to: receive a first voltage based on the first terminal of the Wheatstone bridge via a first input of the comparator; receive a second voltage based on the second terminal of the Wheatstone bridge via a second input of the comparator; and compare the first voltage to the second voltage to generate a comparator output signal; and a digital circuit operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a digital signal, wherein the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference associated with the Wheatstone bridge.
19. The impedance sensing circuit of claim 12 further comprising: a capacitor that is operably coupled between the first input of the comparator and the second input of the comparator.
20. The impedance sensing circuit of claim 12, wherein: the first current signal and the second current signal are regulated based on the comparator output signal to ensure that the first voltage is same as the second voltage.
12. An impedance sensing circuit comprising: a first current source operably coupled and configured, based on a comparator output signal, to output a first current signal to a first node that is operably coupled to a first terminal of a Wheatstone bridge; a second current source operably coupled and configured, based on the comparator output signal, to output a second current signal to a second node that is operably coupled to second terminal of the Wheatstone bridge, wherein the first current signal and the second current signal are regulated based on the comparator output signal to ensure that a first voltage is same as a second voltage; a comparator operably coupled to the first current source and the second current source, wherein, when enabled, the comparator configured to: receive the first voltage based on the first terminal of the Wheatstone bridge via a first input of the comparator; receive the second voltage based on the second terminal of the Wheatstone bridge via a second input of the comparator; and compare the first voltage to the second voltage to generate the comparator output signal; and a capacitor that is operably coupled between the first input of the comparator and the second input of the comparator.
12. …a digital circuit operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a digital signal, wherein the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference associated with the Wheatstone bridge.
13. The impedance sensing circuit of claim 12 further comprising: a digital circuit operably coupled to the comparator, wherein, when enabled, the digital circuit operably coupled and configured to process the comparator output signal to generate a digital signal, wherein the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference associated with the Wheatstone bridge.
13. The impedance sensing circuit of claim 12 further comprising: memory that stores operational instructions; and one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the digital signal to determine the impedance difference associated with the Wheatstone bridge.
14. The impedance sensing circuit of claim 13 further comprising: memory that stores operational instructions; and one or more processing modules operably coupled to the digital circuit and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the digital signal to determine the impedance difference associated with the Wheatstone bridge.
14. The impedance sensing circuit of claim 13, wherein the Wheatstone bridge further comprising: a first resistor; a second resistor connected to the first resistor; a third resistor connected between the first resistor and ground; a fourth resistor connected between the second resistor and ground; the second terminal of the Wheatstone bridge based on connection between the first resistor and the third resistor; and the second terminal of the Wheatstone bridge based on connection between the second resistor and the fourth resistor.
15. The impedance sensing circuit of claim 14, wherein the Wheatstone bridge further comprising: a first resistor; a second resistor connected to the first resistor; a third resistor connected between the first resistor and ground; a fourth resistor connected between the second resistor and ground [.] the second terminal of the Wheatstone bridge based on connection between the first resistor and the third resistor; and the second terminal of the Wheatstone bridge based on connection between the second resistor and the fourth resistor.
15. The impedance sensing circuit of claim 14, wherein: the first resistor, the second resistor, and the third resistor have a first resistance value; the fourth resistor has a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
16. The impedance sensing circuit of claim 15, wherein: the first resistor, the second resistor, and the third resistor have a first resistance value; the fourth resistor has a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
16. The impedance sensing circuit of claim 14, wherein: the first resistor and the third resistor have a first resistance value; and the second resistor and the fourth resistor have a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
17. The impedance sensing circuit of claim 15, wherein: the first resistor and the third resistor have a first resistance value; and the second resistor and the fourth resistor have a second resistance value that is different from the first resistance value; and the impedance difference associated with the Wheatstone bridge is based on a difference between the first resistance value and the second resistance value.
17. The impedance sensing circuit of claim 14 further comprising: a bias current source that is operably coupled to connection between the first resistor and the second resistor and configured to output a bias current signal.
18. The impedance sensing circuit of claim 15 further comprising: a bias current source that is operably coupled to connection between the first resistor and the second resistor and configured to output a bias current signal.
18. The impedance sensing circuit of claim 17 further comprising: a reference current source that is operably coupled to another node that couples to inputs of the first current source and the second current source and configured to output a reference current signal, wherein sensitivity of the digital signal is based on a ratio of the bias current signal to the reference current signal.
19. The impedance sensing circuit of claim 18 further comprising: a reference current source that is operably coupled to another node that couples to inputs of the first current source and the second current source and configured to output a reference current signal, wherein sensitivity of the digital signal is based on a ratio of the bias current signal to the reference current signal.
11. The impedance sensing circuit of claim 1 further comprising: a first buffer operably coupled between the first node and the first terminal of the Wheatstone bridge; and a second buffer operably coupled between the second node and the second terminal of the Wheatstone bridge.
20. The impedance sensing circuit of claim 12 further comprising: a first buffer operably coupled between the first node and the first terminal of the Wheatstone bridge; and a second buffer operably coupled between the second node and the second terminal of the Wheatstone bridge.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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