DETAILED ACTION
This Action is responsive to the Amendments filed on 05/19/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are amended. Claims 1-20 are pending and have been examined.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
No antecedent basis for the claimed term “a condition for merging” (see Claim 1, 11th line; Claim 11, 8th line; Claim 18, 8-9th lines) is provided in the Specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 1,
Examiner cannot identify support in the Specification for the limitation “wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging” recited in Claim 1, 10-11th lines. Applicant alleges support for the aforementioned limitation can be found at least in Specification ¶¶0035; 0039; and Fig. 4 (see 1st page of Remarks; numbered as page 7).
However, examiner first notes that the instant Specification does not provide explicit antecedent basis for the claimed term “a condition for merging”. In addition, the aforementioned limitation uses the term “without determining”, which examiner notes amounts to a negative limitation. As argued in Remarks (see final ¶ of 1st page; numbered as page 7) and as acknowledged by examiner, Fig. 4 and the corresponding description in Specification ¶¶0061-63 do not positively recite a “determining” step performed by the controller which checks whether a merging condition is satisfied prior to merging read commands. However, “Any negative limitation or exclusionary proviso must have basis in the original disclosure … The mere absence of a positive recitation is not basis for an exclusion … silence will not generally suffice to support a negative claim limitation” (MPEP 2173.05(i)). Therefore, despite the absence of a positive recitation of a determination step whereby a condition for merging is satisfied in the aforementioned portions of the Specification, the aforementioned portions of the Specification do not provide sufficient support for the negative limitation as currently recited in Claim 1, lines 10-11. In addition, examiner notes that the Specification ¶0037 discloses that “controller 110 may select read commands for unaligned pages … from among the received plurality of commands CMDs and merge the selected read commands” (Emphasis Added). Examiner notes that the process of a controller selecting unaligned read commands to merge out of a plurality of received read commands may read on the claimed concept of “determining whether the plurality of read commands satisfy a condition for merging”. Therefore, Specification ¶0037 appears to disclose an embodiment whereby a condition for merging is first determined by a controller before the controller merges a plurality of unaligned read commands.
Examiner has reviewed the Specification and cannot identify support for the aforementioned limitation. Therefore, Claim 1 is rejected as failing to comply with the written description requirement. Claim 11, 7-8th lines and Claim 18, 8-9th lines recite substantially similar language as compared to Claim 1 and are therefore similarly rejected according to the same rationale provided above with respect to Claim 1. Claims 2-10, 12-17, and 19-20 are similarly rejected according to their respective dependencies.
Finally, as discussed above, no antecedent basis for the claimed term “a condition for merging” is provided in the Specification. Therefore, if applicant wishes to claim an embodiment using a negative limitation, examiner recommends applicant amend Claim 1, 10-11th lines to instead describe the aforementioned “condition for merging” using terminology which is currently present in the Specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 9, 11, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 20150380097 A1)(cited by examiner in previous Action)(hereafter referred to as Sato) further in view of MacLaren et al. (US 10642684 B1)(hereafter referred to as MacLaren).
Regarding Claim 1,
Sato discloses the following limitations:
A storage device (Fig. 13) comprising:
a nonvolatile memory (BiCS Flash Memory 10, Fig. 13) comprising a plurality of planes (Planes 0 – n, Fig. 15), each comprising a plurality of pages (Pages 0 – 2, Fig. 15); and
a controller (Memory Controller 20, Fig. 13) configured to control the nonvolatile memory, wherein the controller is configured to perform operations (Fig. 14) comprising (¶¶0180-190):
receiving (Fig. 14, step S1001) a plurality of commands (“a plurality of access requests” [0183]) from a host (Host 2, Fig. 13) (“The memory controller 20 receives an access request (access command) from the host 2 … determining in step S1003 that a plurality of access requests to be processed exist” [0181-184]);
merging (Fig. 14, step S1005) a plurality of read commands (“read requests” [0184]) among the plurality of commands into a merge command signal (“the combined access request” [0190])(“the read/write control unit 1b determines whether the plurality of access requests can be combined … all the access requests indicate read requests … it is determined that the plurality of access requests can be combined … When determining in step S1004 that the plurality of access requests can be combined, the read/write control unit 1b combines the plurality of access requests.” [0184-185]) – As shown in Fig. 14 and taught in ¶0184, plural read requests can be combined into a combined access request.,
wherein the plurality of read commands are associated with at least two different planes among the plurality of planes and are associated with at least two different pages among the plurality of pages (“If the plurality of access requests to be processed aim at pages in different planes of the same BiCS flash memory 10 … the access requests can be combined” [0184] // Fig. 15 // “As shown in Fig. 15, it is possible to access user data A, B, and C stored on the pages … having different page numbers” [0192]) – As taught in ¶0184 and shown in Fig. 15, read requests which target different page numbers (e.g., pages 1, 0, and 2) in different memory planes (e.g., planes 0, 1, and n) are performed in parallel--,
transmitting (Fig. 14, step S1006) the merge command signal to the nonvolatile memory (“When combining the plurality of access requests, the write/read control unit 1b performs access (to be referred to as parallel access or multi-plane access) to the BiCS flash memory 10 based on the combined memory access” [0188]); and
applying the merge command signal to the nonvolatile memory (Fig. 15) – As shown in Figs. 14 and 15, after determining to merge read requests, controller 20 accesses the flash memory 10 using the combined memory access (see Fig. 14, step S1006) (i.e., at least “transmit[s]” the combined memory access to the nonvolatile memory) after which data stored within the nonvolatile memory is accessed based on the combined memory access (see Fig. 15) (i.e., “applying” the combined memory access to the nonvolatile memory).
Sato ¶0184 establishes that access requests may be merged when: 1) physical addresses of the plural access requests target pages on different planes; and 2) each request of the plural access request is a read type of request (as opposed to a write request); i.e., establishes two separate conditions for merging which are determined by a controller. However, Sato does not indicate either of conditions 1) or 2) as not being checked by a controller prior to merging commands, and thus does not explicitly disclose the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging
However, MacLaren discloses the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging (“the method 400 begins at operation 402, with the memory controller 106 evaluating placement of a RMW command sequence in a command queue … at operation 406, the memory controller may place, in the command queue, a first read command of the first RMW command sequence and a second read command of the second RMW command sequence as part of a read-modify-write group of consecutive read commands in the command queue. Additionally, at operation 408, the memory controller 106 may place, in the command queue, a first write command of the first RMW command sequence and a second write command of the second RMW sequence as part of a read-modify-write group of consecutive write commands” [Col. 13 – Col. 14, 1st ¶ ] // Figs. 3 + 4) – Examiner considers the storage environment depicted in MacLaren Fig. 1 as analogous to the storage environment depicted in Sato Fig. 13. As taught in MacLaren Fig. 4, read commands and write commands of read-modify-write command sequences are merged into respective sequences of read commands and respective sequences of write commands as part of the same method 400. One of ordinary skill would accordingly understand that the commands of MacLaren are merged while both read commands and write commands are scheduled for execution because a RMW command sequence includes both a read command and a write command. Therefore, the method depicted in MacLaren Fig. 4 is an example of merging read commands (step 406) without first determining that only read commands are present (i.e., the condition 2) checked by the controller of Sato as discussed above). Therefore, the method depicted in MacLaren is performed without checking a condition 2) as taught in Sato, and accordingly reads on a method whereby read commands are merged “without determining whether the plurality of read commands satisfy a condition for merging”.
Sato and MacLaren are considered analogous to the claimed invention because they all relate to the same field of reordering execution of plural memory access commands using a command queue. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato with the teachings of MacLaren and realize a storage device which merges read commands without a requirement that each queued memory access be a read type of access. Doing so enables interleaving of multiple read-modify-write command sequences, resulting in improved memory bus utilization over traditional memory systems as disclosed in MacLaren Col. 3, 35-50th lines: “Various embodiments described herein can reduce or avoid the turnaround delay (e.g., tWTR) between read operations to write operations for multiple RMWs, and can increase memory bus utilization over traditional memory systems. According to some embodiments, RMWs are grouped such that multiple RMWs can be executed (or rearranged in the command queue) in an interleaved manner (e.g., RRRWWW) rather than being executed in order” [Col. 3]
Regarding Claim 3,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 3. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1, wherein the controller is configured to determine (Sato, Fig. 14, step S1004) a number of the at least two different pages. (Sato, “the write/read control unit 1b determines whether the plurality of access requests can be combined. If the plurality of access requests to be processed aim at pages in different planes” [0184]) – As previously discussed, during step S1004, the memory controller determines whether or not the plural access requests are combinable by determining whether they target pages in different planes (i.e., at least 2 different pages). In the context of Sato, such a determination corresponds to a determination that the number of pages targeted by the plural access requests is at least 2 (i.e., a determination that “a number of the at least two different pages” is at least 2).
Regarding Claim 9,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 9. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1, wherein the controller is configured to store the plurality of commands in a queue (Sato, “a command queue” [0183]), select the plurality of read commands from the queue (Sato, “the memory controller 20 includes, for example, a command queue area (not shown) … The write/read control unit 1b can refer to the access request stored in the command queue area and determine whether a plurality of access requests exists” [0183]), and consecutively merge (Sato, Fig. 14) from the queue the plurality of read commands into the merge command signal. – As taught in ¶0183, memory controller 20 receives and stores host access requests in a command queue. As previously discussed (see Claim 1 limitation mappings above) and as shown in Fig. 14, after access requests are stored in the queue, the access requests are selected from the queue and are subsequently merged into the combined access request.
Regarding Claim 11,
Sato discloses the following limitations:
A method of operating a controller (Memory Controller 20, Fig. 13), the method comprising:
receiving (Fig. 14, step S1001) a plurality of commands (“a plurality of access requests” [0183]) from a host (Host 2, Fig. 13)(“The memory controller 20 receives an access request (access command) from the host 2 … determining in step S1003 that a plurality of access requests to be processed exist” [0181-184]);
merging (Fig. 14, step S1005) a plurality of read commands (“read requests” [0184]) among the plurality of commands into a merge command signal (“the combined access request” [0190])(“the read/write control unit 1b determines whether the plurality of access requests can be combined … all the access requests indicate read requests … it is determined that the plurality of access requests can be combined … When determining in step S1004 that the plurality of access requests can be combined, the read/write control unit 1b combines the plurality of access requests.” [0184-185]) – As shown in Fig. 14 and taught in ¶0184, plural read requests can be combined into a combined access request.,
wherein the plurality of read commands are associated with at least two different planes among a plurality of planes, wherein the plurality of planes each comprise a plurality of pages and are each associated with at least two different pages among the plurality of pages (“If the plurality of access requests to be processed aim at pages in different planes of the same BiCS flash memory 10 … the access requests can be combined” [0184] // Fig. 15 // “As shown in Fig. 15, it is possible to access user data A, B, and C stored on the pages … having different page numbers” [0192]) – As taught in ¶0184 and shown in Fig. 15, read requests which target different page numbers (e.g., pages 1, 0, and 2) in different memory planes (e.g., planes 0, 1, and n) are performed in parallel-; … and
transmitting (Fig. 14, step S1006) the merge command signal to a nonvolatile memory (BiCS Flash Memory 10, Fig. 13)(“When combining the plurality of access requests, the write/read control unit 1b performs access (to be referred to as parallel access or multi-plane access) to the BiCS flash memory 10 based on the combined memory access” [0188]);
Sato ¶0184 establishes that access requests may be merged when: 1) physical addresses of the plural access requests target pages on different planes; and 2) each request of the plural access request is a read type of request (as opposed to a write request); i.e., establishes two separate conditions for merging which are determined by a controller. However, Sato does not indicate either of conditions 1) or 2) as not being checked by a controller prior to merging commands, and thus does not explicitly disclose the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging
However, MacLaren discloses the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging (“the method 400 begins at operation 402, with the memory controller 106 evaluating placement of a RMW command sequence in a command queue … at operation 406, the memory controller may place, in the command queue, a first read command of the first RMW command sequence and a second read command of the second RMW command sequence as part of a read-modify-write group of consecutive read commands in the command queue. Additionally, at operation 408, the memory controller 106 may place, in the command queue, a first write command of the first RMW command sequence and a second write command of the second RMW sequence as part of a read-modify-write group of consecutive write commands” [Col. 13 – Col. 14, 1st ¶ ] // Figs. 3 + 4) – Examiner considers the storage environment depicted in MacLaren Fig. 1 as analogous to the storage environment depicted in Sato Fig. 13. As taught in MacLaren Fig. 4, read commands and write commands of read-modify-write command sequences are merged into respective sequences of read commands and respective sequences of write commands as part of the same method 400. One of ordinary skill would accordingly understand that the commands of MacLaren are merged while both read commands and write commands are scheduled for execution because a RMW command sequence includes both a read command and a write command. Therefore, the method depicted in MacLaren Fig. 4 is an example of merging read commands (step 406) without first determining that only read commands are present (i.e., the condition 2) checked by the controller of Sato as discussed above). Therefore, the method depicted in MacLaren is performed without checking a condition 2) as taught in Sato, and accordingly reads on a method whereby read commands are merged “without determining whether the plurality of read commands satisfy a condition for merging”.
Sato and MacLaren are considered analogous to the claimed invention because they all relate to the same field of reordering execution of plural memory access commands using a command queue. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato with the teachings of MacLaren and realize a storage device which merges read commands without a requirement that each queued memory access be a read type of access. Doing so enables interleaving of multiple read-modify-write command sequences, resulting in improved memory bus utilization over traditional memory systems as disclosed in MacLaren Col. 3, 35-50th lines: “Various embodiments described herein can reduce or avoid the turnaround delay (e.g., tWTR) between read operations to write operations for multiple RMWs, and can increase memory bus utilization over traditional memory systems. According to some embodiments, RMWs are grouped such that multiple RMWs can be executed (or rearranged in the command queue) in an interleaved manner (e.g., RRRWWW) rather than being executed in order” [Col. 3]
Regarding Claim 16,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 16. The combined teachings of Sato and MacLaren disclose the following limitations:
Sato anticipates the following limitations:
The method of claim 11, further comprising: storing the plurality of commands in a queue (Sato, “a command queue” [0183]), selecting the plurality of read commands from the queue (Sato, “the memory controller 20 includes, for example, a command queue area (not shown) … The write/read control unit 1b can refer to the access request stored in the command queue area and determine whether a plurality of access requests exists” [0183]), and consecutively merging (Sato, Fig. 14) from the queue the plurality of read commands into the merge command signal. – As taught in ¶0183, memory controller 20 receives and stores host access requests in a command queue. As previously discussed (see Claim 11 limitation mappings above) and as shown in Fig. 14, after access requests are stored in the queue, the access requests are selected from the queue and are subsequently merged into the combined access request.
Regarding Claim 18,
Sato discloses the following limitations:
A storage system comprising:
a host (Host 2, Fig. 13) configured to apply a plurality of commands (¶0181); and
a storage device (Memory Device 1, Fig. 13) configured to receive (Fig. 14, step S1001) the plurality of commands from the host(“The memory controller 20 receives an access request (access command) from the host 2 … determining in step S1003 that a plurality of access requests to be processed exist” [0181-184]),
merge (Fig. 14, step S1005) a plurality of read commands among the plurality of commands into a merge command signal (“the combined access request” [0190])(“the read/write control unit 1b determines whether the plurality of access requests can be combined … all the access requests indicate read requests … it is determined that the plurality of access requests can be combined … When determining in step S1004 that the plurality of access requests can be combined, the read/write control unit 1b combines the plurality of access requests.” [0184-185]) – As shown in Fig. 14 and taught in ¶0184, plural read requests can be combined into a combined access request.,
wherein the plurality of read commands are associated with at least two different planes among a plurality of planes, wherein the plurality of planes each comprise a plurality of pages and are each associated with at least two different pages among the plurality of pages (“If the plurality of access requests to be processed aim at pages in different planes of the same BiCS flash memory 10 … the access requests can be combined” [0184] // Fig. 15 // “As shown in Fig. 15, it is possible to access user data A, B, and C stored on the pages … having different page numbers” [0192]) – As taught in ¶0184 and shown in Fig. 15, read requests which target different page numbers (e.g., pages 1, 0, and 2) in different memory planes (e.g., planes 0, 1, and n) are performed in parallel--, …
wherein the storage device is further configured to perform a read operation based on the merge command signal (“When combining the plurality of access requests, the write/read control unit 1b performs access (to be referred to as parallel access or multi-plane access) to the BiCS flash memory 10 based on the combined memory access” [0188] // Fig. 15) – As shown in Fig. 15, a read operation is performed on the flash memory in response to the combined memory access.
Sato ¶0184 establishes that access requests may be merged when: 1) physical addresses of the plural access requests target pages on different planes; and 2) each request of the plural access request is a read type of request (as opposed to a write request); i.e., establishes two separate conditions for merging which are determined by a controller. However, Sato does not indicate either of conditions 1) or 2) as not being checked by a controller prior to merging commands, and thus does not explicitly disclose the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging
However, MacLaren discloses the following limitations:
wherein the plurality of read commands are merged without determining whether the plurality of read commands satisfy a condition for merging (“the method 400 begins at operation 402, with the memory controller 106 evaluating placement of a RMW command sequence in a command queue … at operation 406, the memory controller may place, in the command queue, a first read command of the first RMW command sequence and a second read command of the second RMW command sequence as part of a read-modify-write group of consecutive read commands in the command queue. Additionally, at operation 408, the memory controller 106 may place, in the command queue, a first write command of the first RMW command sequence and a second write command of the second RMW sequence as part of a read-modify-write group of consecutive write commands” [Col. 13 – Col. 14, 1st ¶ ] // Figs. 3 + 4) – Examiner considers the storage environment depicted in MacLaren Fig. 1 as analogous to the storage environment depicted in Sato Fig. 13. As taught in MacLaren Fig. 4, read commands and write commands of read-modify-write command sequences are merged into respective sequences of read commands and respective sequences of write commands as part of the same method 400. One of ordinary skill would accordingly understand that the commands of MacLaren are merged while both read commands and write commands are scheduled for execution because a RMW command sequence includes both a read command and a write command. Therefore, the method depicted in MacLaren Fig. 4 is an example of merging read commands (step 406) without first determining that only read commands are present (i.e., the condition 2) checked by the controller of Sato as discussed above). Therefore, the method depicted in MacLaren is performed without checking a condition 2) as taught in Sato, and accordingly reads on a method whereby read commands are merged “without determining whether the plurality of read commands satisfy a condition for merging”.
Sato and MacLaren are considered analogous to the claimed invention because they all relate to the same field of reordering execution of plural memory access commands using a command queue. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato with the teachings of MacLaren and realize a storage device which merges read commands without a requirement that each queued memory access be a read type of access. Doing so enables interleaving of multiple read-modify-write command sequences, resulting in improved memory bus utilization over traditional memory systems as disclosed in MacLaren Col. 3, 35-50th lines: “Various embodiments described herein can reduce or avoid the turnaround delay (e.g., tWTR) between read operations to write operations for multiple RMWs, and can increase memory bus utilization over traditional memory systems. According to some embodiments, RMWs are grouped such that multiple RMWs can be executed (or rearranged in the command queue) in an interleaved manner (e.g., RRRWWW) rather than being executed in order” [Col. 3]
Regarding Claim 19,
The same motivation to combine provided in Claim 18 is equally applicable to Claim 19. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage system of claim 18, wherein the storage device comprises: a nonvolatile memory (Sato, BiCS Flash Memory 10, Fig. 13) comprising the plurality of planes (Sato, Figs. 13 + 15); and
a storage controller (Sato, Memory Controller 20, Fig. 13) configured to merge (Sato, Fig. 14, step S1005) the plurality of read commands and transmit (Sato, Fig. 14, step S1006) the merge command signal to the nonvolatile memory (Sato, “When combining the plurality of access requests, the write/read control unit 1b performs access (to be referred to as parallel access or multi-plane access) to the BiCS flash memory 10 based on the combined memory access” [0188] // ¶¶0180-190) – As taught in Sato, memory controller 20 performs steps S1005 and S1006 of Fig. 14.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sato further in view of MacLaren and Weinberg et al. (US 20240028244 A1)(cited by examiner in previous action)(hereafter referred to as Weinberg).
Regarding Claim 2,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 2. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1 (see Claim 1 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
wherein the controller is configured to transmit a single status check command for the at least two different planes, comprising the at least two different pages, to the nonvolatile memory after transmitting the merge command signal.
However, Weinberg discloses the following limitations:
wherein the controller (Controller 106, Fig. 1) is configured to transmit a single status check command (“multi-channel status read command” [0032]) for the at least two different planes, comprising the at least two different pages, to the nonvolatile memory (Memory Package 102, Fig. 1) after transmitting the merge command signal (“a memory controller can issue commands (e.g., access commands) to various logical units … After issuing the commands, the memory controller can issue status read commands to the logical units to determine which of the operations have been completed and on which of the logical units” [0012] // “the multi-channel status read command can be a single (e.g., only one) command … the I/O expander 104 can interpret as instructions to transmit status read command to logical units 120 over two or more of the back-end channels” [0032] // Fig. 1 // ¶0015) -- Examiner considers Controller 106 of Weinberg Fig. 1 as analogous to Memory Controller 20 of Sato Fig. 13 because both are memory controllers which perform access commands received from an external host directed towards plural non-volatile memory planes (see Weinberg ¶¶0012;0015). As taught in Weinberg ¶0032, Controller 106 transmits a single “multi-channel status read command” to memory package 102 in order to check on the status of various accessed logical units (i.e., at least two different planes; see ¶¶0012; 0015).
Sato, MacLaren, and Weinberg are considered analogous to the claimed invention because they all relate to the same field of combining plural memory accesses targeting different memory planes into a single command transmit to a memory controller. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Weinberg and realize a storage device which transmits a single status command to a non-volatile memory in response to transmitting a merged access command to the non-volatile memory. Doing so improves technology by reducing I/O bus data overhead involved in obtaining status read data from logical units across multiple back-end channels, as disclosed in Weinberg ¶0013: “the present technology facilitates obtaining status read data from logical units across multiple back-end channels in response to a single multi-channel status read command. In this manner, the present technology is expected to reduce the I/O bus overhead involved in obtaining status read data from logical units across multiple back-end channels” [0013]
Regarding Claim 13,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 13. The combined teachings of Sato and MacLaren disclose the following limitations:
The method of claim 11 (see Claim 11 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
further comprising transmitting a single status check command for the at least two different planes comprising the at least two different pages, to the nonvolatile memory
However, Weinberg discloses the following limitations:
further comprising transmitting a single status check command (“multi-channel status read command” [0032]) for the at least two different planes comprising the at least two different pages, to the nonvolatile memory (Memory Package 102, Fig. 1)(“a memory controller can issue commands (e.g., access commands) to various logical units … After issuing the commands, the memory controller can issue status read commands to the logical units to determine which of the operations have been completed and on which of the logical units” [0012] // “the multi-channel status read command can be a single (e.g., only one) command … the I/O expander 104 can interpret as instructions to transmit status read command to logical units 120 over two or more of the back-end channels” [0032] // Fig. 1 // ¶0015) -- Examiner considers Controller 106 of Weinberg Fig. 1 as analogous to Memory Controller 20 of Sato Fig. 13 because both are memory controllers which perform access commands received from an external host directed towards plural non-volatile memory planes (see Weinberg ¶¶0012;0015). As taught in Weinberg ¶0032, Controller 106 transmits a single “multi-channel status read command” to memory package 102 in order to check on the status of various accessed logical units (i.e., at least two different planes; see ¶¶0012; 0015).
Sato, MacLaren, and Weinberg are considered analogous to the claimed invention because they all relate to the same field of combining plural memory accesses targeting different memory planes into a single command transmit to a memory controller. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Weinberg and realize a storage device which transmits a single status command to a non-volatile memory in response to transmitting a merged access command to the non-volatile memory. Doing so improves technology by reducing I/O bus data overhead involved in obtaining status read data from logical units across multiple back-end channels, as disclosed in Weinberg ¶0013: “the present technology facilitates obtaining status read data from logical units across multiple back-end channels in response to a single multi-channel status read command. In this manner, the present technology is expected to reduce the I/O bus overhead involved in obtaining status read data from logical units across multiple back-end channels” [0013]
Claims 4-5, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sato further in view of MacLaren and CP et al. (US 20220358995 A1)(cited by examiner in previous action)(hereafter referred to as CP).
Regarding Claim 4,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 4. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1, wherein each of the plurality of pages is classified as one of a plurality of logical pages corresponding to k-bits represented by a single memory cell, wherein k is a positive integer greater than or equal to 2 (Sato, “Each memory cell transistor MT … can store .. 3-bit data … The bits of each 3-bit data will be referred to as an upper page … middle page … and lower page” [0422-424]) – As taught in Sato, memory cells store 3-bit data whereby pages are logically organized into “upper”, “middle”, and “lower” type pages corresponding to respective bits of the data--, and
Sato does not provide specific detail regarding how the combined memory access command of step S1005 is organized relative logical pages. Therefore, Sato and MacLaren do not appear to disclose the following limitations:
wherein the controller is configured to merge the plurality of read commands into units of the plurality of logical pages
However, CP discloses the following limitations:
wherein the controller (Controller 102, Fig. 1A) is configured to merge the plurality of read commands into units of the plurality of logical pages (“A combined read operation … may be initiated by a command received by a non-volatile memory die. A host or memory controller … may send such a command to a memory die … It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command.” [0124-126] // Fig. 1A) – As taught in CP, a memory controller 102 transmits a “combined read operation” to non-volatile memory dies 104, similar to how a memory controller 20 of Sato Fig. 13 transmits a combined access request to a memory device 10. Examiner accordingly considers memory controller 102 of CP Fig. 1A as analogous to the claimed memory controller. As taught in CP, a combined read operation performs reads on particular combinations of logical pages (i.e., the combined read operation is organized into “units” of logical pages).
Sato, MacLaren, and CP are considered analogous to the claimed invention because they all relate to the same field of performing merged read commands on a non-volatile memory die organized logically into plural pages. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of CP and realize a storage device which organizes merged read commands into units of logical pages. Doing so improves the efficiency of read operation enabling multiple pages to be read at once without each logical page necessarily being read, as disclosed in CP ¶0126: “It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command. This may be more efficient than sending separate individual random read commands for multiple logical pages (e.g., less traffic on a bus between a controller and a memory die) while allowing fewer than all logical pages in a physical page to be read.” [0126]
Regarding Claim 5,
The same motivation to combine provided in Claim 4 is equally applicable to Claim 5. The combined teachings of Sato, MacLaren, and CP disclose the following limitations:
The storage device of claim 4, wherein the controller is configured to merge the plurality of read commands into a same logical page, among the plurality of logical pages. (CP, “any combination of logical pages may be specified” [0126]) – Examiner considers any combination of logical pages which are combined into the same combined read command as reading on the claimed concept of “a same logical page” under the BRI of the claimed language.
Regarding Claim 12,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 12. The combined teachings of Sato and MacLaren disclose the following limitations:
The method of claim 11, further comprising:
determining (Sato, Fig. 14, step S1004) a number of the at least two different pages. (Sato, “the write/read control unit 1b determines whether the plurality of access requests can be combined. If the plurality of access requests to be processed aim at pages in different planes” [0184]) – As previously discussed, during step S1004, the memory controller determines whether or not the plural access requests are combinable by determining whether they target pages in different planes (i.e., at least 2 different pages). In the context of Sato, such a determination corresponds to a determination that the number of pages targeted by the plural access requests is at least 2 (i.e., a determination that “a number of the at least two different pages” is at least 2).
Sato and MacLaren do not appear to explicitly disclose the following limitations
merging a subset of the plurality of read commands corresponding to the number into the merge command signal.
However, CP discloses the following limitations:
merging a subset of the plurality of read commands corresponding to the number into the merge command signal. (“A combined read operation … may be initiated by a command received by a non-volatile memory die. A host or memory controller … may send such a command to a memory die … It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command.” [0124-126] // Fig. 1A) – As taught in CP, a memory controller 102 transmits a “combined read operation” to non-volatile memory dies 104, similar to how a memory controller 20 of Sato Fig. 13 transmits a combined access request to a memory device 10. Examiner accordingly considers memory controller 102 of CP Fig. 1A as analogous to the claimed memory controller. As taught in CP, combined read operations correspond to reads targeting any combination of logical pages. In the context of CP, the particular combination of logical pages targeted by a combined read operation correspond to “a subset” of the total read commands which may be merged.
Sato, MacLaren, and CP are considered analogous to the claimed invention because they all relate to the same field of performing merged read commands on a non-volatile memory die organized logically into plural pages. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of CP and realize a storage device which merges a subset of read commands into a merged command signal. Doing so improves the efficiency of read operation enabling multiple pages to be read at once without each logical page necessarily being read, as disclosed in CP ¶0126: “It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command. This may be more efficient than sending separate individual random read commands for multiple logical pages (e.g., less traffic on a bus between a controller and a memory die) while allowing fewer than all logical pages in a physical page to be read.” [0126]
Regarding Claim 14,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 14. The combined teachings of Sato and MacLaren disclose the following limitations:
The method of claim 11, wherein each of the plurality of pages is classified as one of a plurality of logical pages corresponding to k-bits represented by a single memory cell, wherein k is a positive integer greater than or equal to 2 (Sato, “Each memory cell transistor MT … can store .. 3-bit data … The bits of each 3-bit data will be referred to as an upper page … middle page … and lower page” [0422-424]) – As taught in Sato, memory cells store 3-bit data whereby pages are logically organized into “upper”, “middle”, and “lower” type pages corresponding to respective bits of the data--, and
Sato does not provide specific detail regarding how the combined memory access command of step S1005 is organized relative logical pages. Therefore, Sato and MacLaren do not appear to disclose the following limitations:
wherein the merging the plurality of read commands comprises merging the plurality of read commands into units of the plurality of logical pages
However, CP discloses the following limitations:
wherein the merging the plurality of read commands comprises merging the plurality of read commands into units of the plurality of logical pages (“A combined read operation … may be initiated by a command received by a non-volatile memory die. A host or memory controller … may send such a command to a memory die … It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command.” [0124-126] // Fig. 1A) – As taught in CP, a memory controller 102 transmits a “combined read operation” to non-volatile memory dies 104, similar to how a memory controller 20 of Sato Fig. 13 transmits a combined access request to a memory device 10. Examiner accordingly considers memory controller 102 of CP Fig. 1A as analogous to the claimed memory controller. As taught in CP, a combined read operation performs reads on particular combinations of logical pages (i.e., the combined read operation is organized into “units” of logical pages).
Sato, MacLaren, and CP are considered analogous to the claimed invention because they all relate to the same field of performing merged read commands on a non-volatile memory die organized logically into plural pages. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of CP and realize a storage device which organizes merged read commands into units of logical pages. Doing so improves the efficiency of read operation enabling multiple pages to be read at once without each logical page necessarily being read, as disclosed in CP ¶0126: “It can be seen that any combination of logical pages may be specified for a combined read using such a combined read command. This may be more efficient than sending separate individual random read commands for multiple logical pages (e.g., less traffic on a bus between a controller and a memory die) while allowing fewer than all logical pages in a physical page to be read.” [0126]
Claims 6-8, 10, 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sato further in view of MacLaren and Madraswala et al. (US 20190102097 A1)(cited by examiner in previous action)(hereafter referred to as Madraswala).
Regarding Claim 6,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 6. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1 (see Claim 1 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
wherein the merge command signal comprises level adjustment information for adjusting a read voltage for a read operation for each of the plurality of planes
However, Madraswala discloses the following limitations:
wherein the merge command signal (“multiplane read command” [0113]) comprises level adjustment information (“a profile identifier” [0065]) for adjusting a read voltage for a read operation for each of the plurality of planes (“Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // “In an embodiment, the read command is a multiplane read command and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multiplane read command.” [0113] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0113). As taught in Madraswala, a “multiplane read operation” specifying plural memory planes (¶0113) includes a “profile identifier” (¶0065) which enables memory controller 126 to adjust each read voltage applied to each plane associated with the multiplane read operation. Examiner accordingly considers a profile identifier associated with a read command as reading on the claimed concept of “level adjustment information”.
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which adjusts a read voltage for each plane of a plurality of planes targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Regarding Claim 7,
The same motivation to combine provided in Claim 6 is equally applicable to Claim 7. The combined teachings of Sato, MacLaren, and Madraswala disclose the following limitations:
The storage device of claim 6 (see Claim 6 limitation mappings above), wherein the level adjustment information comprises plane information for which the read voltage is to be adjusted (Madraswala, ¶¶0065; 0113) – As previously discussed (see Claim 6 limitation mappings above), a “profile identifier” included within a read command enables voltage adjustment while performing the command. Examiner accordingly considers the profile identifier included within a “multiplane read” type of read command (see Madraswala ¶0113) as reading on the claimed concept of “plane information” because the profile identifier of a multiplane read command causes particular voltages to be applied to each plane identified by the multiplane command.
Regarding Claim 8,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 8. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1 (see Claim 1 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
wherein the nonvolatile memory is configured to perform a set-up on the at least two different pages based on receiving the merge command signal
However, Madraswala discloses the following limitations:
wherein the nonvolatile memory (Memory Device 122, Fig. 4) is configured to perform a set-up on the at least two different pages based on receiving the merge command signal (“a multiplane read command may specify a single read voltage offset profile identifier that is used for each page read from the various planes” [0093] // “Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0093). As taught in Madraswala, after a memory controller receives a multiplane read command specifying a profile identifier, particular read voltage offsets are retrieved from a memory which specify particular voltages to apply to each page specified in the multiplane read command. Examiner considers the process of retrieving read voltage offsets based on a profile identifier received with a multiplane read command as “a set-up” performed on each page associated with the multiplane read command (i.e., setting up particular read voltages which will be applied to the at least two different pages).
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which sets up a read voltage for pages targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Regarding Claim 10,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 10. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage device of claim 1 (see Claim 1 limitation mappings above),
Sato does not explicitly disclose read voltage adjustment with respect to each memory plane. Specifically, Sato and MacLaren do not explicitly disclose the following limitations:
wherein the controller is configured to adjust a read voltage for a read operation for each of the plurality of planes.
However, Madraswala discloses the following limitations:
wherein the controller (Controller 126, Fig. 4) is configured to adjust a read voltage for a read operation for each of the plurality of planes (“Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // “In an embodiment, the read command is a multiplane read command and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multiplane read command.” [0113] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0113). As taught in Madraswala, controller 126 adjusts a read voltage for each plane of plural planes specified in a multiplane read command.
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which adjusts a read voltage for each plane of a plurality of planes targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Regarding Claim 15,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 15. The combined teachings of Sato and MacLaren disclose the following limitations:
The method of claim 11 (see Claim 11 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
wherein the merge command signal comprises level adjustment information for adjusting a read voltage for a read operation for each of the plurality of planes, and wherein the level adjustment information comprises plane information for which the read voltage is to be adjusted.
However, Madraswala discloses the following limitations:
wherein the merge command signal (“multiplane read command” [0113]) comprises level adjustment information (“a profile identifier” [0065]) for adjusting a read voltage for a read operation for each of the plurality of planes (“Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // “In an embodiment, the read command is a multiplane read command and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multiplane read command.” [0113] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0113). As taught in Madraswala, a “multiplane read operation” specifying plural memory planes (¶0113) includes a “profile identifier” (¶0065) which enables memory controller 126 to adjust each read voltage applied to each plane associated with the multiplane read operation. Examiner accordingly considers a profile identifier associated with a read command as reading on the claimed concept of “level adjustment information”., and
wherein the level adjustment information comprises plane information for which the read voltage is to be adjusted. (Madraswala, ¶¶0065; 0113) – As discussed above, a “profile identifier” included within a read command enables voltage adjustment while performing the command. Examiner accordingly considers the profile identifier included within a “multiplane read” type of read command (see Madraswala ¶0113) as reading on the claimed concept of “plane information” because the profile identifier of a multiplane read command causes particular voltages to be applied to each plane identified by the multiplane command.
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which adjusts a read voltage for each plane of a plurality of planes targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Regarding Claim 17,
The same motivation to combine provided in Claim 11 is equally applicable to Claim 17. The combined teachings of Sato and MacLaren disclose the following limitations:
The method of claim 11 (see Claim 11 limitation mappings above),
Sato does not explicitly disclose read voltage adjustment with respect to each memory plane. Specifically, Sato and MacLaren do not explicitly disclose the following limitations:
adjusting a read voltage for a read operation for each of the plurality of planes.
However, Madraswala discloses the following limitations:
adjusting a read voltage for a read operation for each of the plurality of planes (“Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // “In an embodiment, the read command is a multiplane read command and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multiplane read command.” [0113] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0113). As taught in Madraswala, controller 126 adjusts a read voltage for each plane of plural planes specified in a multiplane read command.
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which adjusts a read voltage for each plane of a plurality of planes targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Regarding Claim 20,
The same motivation to combine provided in Claim 18 is equally applicable to Claim 20. The combined teachings of Sato and MacLaren disclose the following limitations:
The storage system of claim 18 (see Claim 18 limitation mappings above),
Sato and MacLaren do not appear to explicitly disclose the following limitations:
wherein the plurality of commands comprise level adjustment information for adjusting a read voltage for a read operation for each of the plurality of planes.
However, Madraswala discloses the following limitations:
wherein the plurality of commands comprise level adjustment information (“a profile identifier” [0065]) for adjusting a read voltage for a read operation for each of the plurality of planes (“Controller 126 may also be operable to receive a read command that specifies a profile identifier, retrieve the read voltage offsets from memory 402, and adjust the read voltages based on the offsets for the read operation.” [0065] // “In an embodiment, the read command is a multiplane read command and the at least one adjusted read voltage is applied to read data from each plane of a plurality of planes specified in the multiplane read command.” [0113] // Fig. 4) – Examiner considers Controller 126 of Madraswala Fig. 4 as analogous to the Controller 20 of Sato Fig. 13 because both are memory controllers which perform simultaneous read operations on plural memory planes (see Madraswala ¶0113). As taught in Madraswala, a “multiplane read operation” specifying plural memory planes (¶0113) includes a “profile identifier” (¶0065) which enables memory controller 126 to adjust each read voltage applied to each plane associated with the multiplane read operation. Examiner accordingly considers a profile identifier associated with a read command as reading on the claimed concept of “level adjustment information”.
Sato, MacLaren, and Madraswala are considered analogous to the claimed invention because they all relate to the same field of performing simultaneous read operations on plural memory planes. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sato and MacLaren with the teachings of Madraswala and realize a storage device which adjusts a read voltage for each plane of a plurality of planes targeted by a merged read command. Doing so provides a low-overhead mechanism for extending the age of data without requiring a refresh operation, as disclosed in Madraswala ¶0017: “Various embodiments of the present disclosure may significantly reduce overhead associated with the adjustment of read voltages. Particular embodiments may relax the period of background data refresh as well. In some systems, data that has aged significantly may need to be refreshed (e.g., read out and programmed again) in order to maintain the ability to accurately read the data. The ability to adjust the read voltages without undue overhead may allow the data to age further without a refresh operation while still preserving the ability to accurately read the data.”
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in view of the newly-identified MacLaren reference because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.S.M./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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