CTNF 19/020,078 CTNF 81127 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-5 AND 12-13 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yakubo et al. (US 20230188094) . PNG media_image1.png 754 566 media_image1.png Greyscale With respect to claim 1, Yakubo et al. discloses an electronic frequency mixer, comprising: at least one transistor (Tr1 to Tr6, M1 and M2 see [00134]) having a front gate (at TLO+ for Tr4 and Tr5 and TLO- for Tr3 and Tr6), a back gate ([0053] “Depending on the transistor structure, a transistor may include a back gate in addition to the above three terminals. In that case, in this specification and the like, one of the gate and the back gate of the transistor may be referred to as a first gate and the other of the gate and the back gate of the transistor may be referred to as a second gate. In some cases, the terms “gate” and “back gate” can be replaced with each other in one transistor. In the case where a transistor includes three or more gates, the gates may be referred to as a first gate, a second gate, and a third gate, for example, in this specification and the like.”, Here, the backgates would be as shown in Fig. 5C (directly connected to the front gate) or Fig. 5D. (different signal BG) ), a source, and a drain; wherein: the source (at 111 going to 112) is coupled to a node of application of a radio frequency input signal (TRF+ and TRF-) ; the front gate is coupled to a node of application of a first periodic signal at a first frequency (TLO+); and the back gate is coupled to one of: a node of application of the first periodic signal or a node of application of a second periodic signal at the first frequency (TLO+). (Here see [0134] stating “The transistors Tr1 to Tr6, the transistor M1, and the transistor M2 may each be a transistor including a back gate. “ The demonstrated configurations includes Fig. 5C wherein the gate is connected to the back gate and thus the gate and back gate would be periodic signals in phase of each other. “ Fig. 5D would include application of a second periodic signal. ) With respect to claim 2, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the at least one transistor is of silicon-on-insulator type (See [185], transistors of the silcon germaium or silicon carbide can be used). With respect to claim 3, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the front and back gates receive the first periodic signal (TLO is periodic in that it is a frequency). With respect to claim 4, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the front gate (at TLO) receives the first periodic signal (TLO is periodic in that it is a frequency) and the back gate receives the second periodic signal, the first and second periodic signals being in phase (Here see [0134] stating “The transistors Tr1 to Tr6, the transistor M1, and the transistor M2 may each be a transistor including a back gate. “ The demonstrated configurations includes Fig. 5C wherein the gate is connected to the back gate and thus the gate and back gate would be periodic signals in phase of each other. ) With respect to claim 5, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the front gate receives the first periodic signal (TLO) and the back gate receives the second periodic signal (TLO), the first and second periodic signals being in phase opposition. (Here 5D shows a structure in which the back gate receives a different signal as opposed to the front gate). With respect to claim 12, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the drain of the at least one transistor is coupled to the output of the mixer .(TR3-TR5 have drains connected to the output TIF+ and TIF- as disclosed). PNG media_image2.png 586 855 media_image2.png Greyscale With respect to claim 13, Yakubo et al. discloses an electronic circuit (see fig. 10), comprising: an antenna (ANT); and at least one electronic frequency mixer (202 and 210) according to claim 1 (See [0173], “ The low noise amplifier 201 amplifies a signal received by the antenna ANT with low noise. As the mixer 202, the semiconductor device 100A or the like described in the above embodiment can be used.”) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 6, 8-11 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yakubo et al. (US 20230188094) in view of Ipek (US 20250373203) . With respect to claim 6, Yakubo et al. discloses the electronic frequency mixer according to claim 1, wherein the at least one transistor comprises a first pair of transistors (Tr3 and Tr4) and a second pair of transistors (Tr5 and Tr6), and wherein: sources of transistors in the first pair of transistors are coupled to a node of application of a first radio frequency input signal (at drain of Tr1 the frequency TRF+); sources of transistors in the second pair of transistors are coupled to a node of application of a second radio frequency input signal (at drain of Tr2 the frequency TRF-) , the first and second radio frequency input signals being differential signals (TRF+ and TRF-) front and back gates of a first transistor of each of the first and second pairs of transistors are coupled to a node of application of a first periodic signal (i.e. TRO); and front and back gates of a second transistor of each of the first and second pairs of transistors are coupled to a node of application of a second periodic signal (i.e. BG of fig. 5D) , (Here see [0134] stating “The transistors Tr1 to Tr6, the transistor M1, and the transistor M2 may each be a transistor including a back gate. “The demonstrated configurations include Fig. 5D wherein the gate is not connected to the backgate), but fails to disclose the first and second periodic signals being differential signals. PNG media_image3.png 647 566 media_image3.png Greyscale Ipek teaches making differential the front gate and the backgate of inputs in a mixer (See [0017]-0018] “These dual-gated NFETs can each have two independently biasable gates including a front gate (also referred to herein as a primary gate) and a back gate (also referred to herein as a secondary gate) opposite the front gate.”) It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to bias the front gate and backgate (i.e. in figure 5D of Yakubo et al. make the front and back gate differential) in a differential format for the purpose of achieving a specific offset. With respect to claim 8, the circuit above discloses the electronic frequency mixer according to claim 6, wherein the mixer is an active mixer. (Here, the mixer is interpreted as active in that 115 is supplied with a voltage VDD powering the system.) With respect to claim 9, the circuit above discloses the electronic frequency mixer according to claim 8, wherein the radio frequency input signal is generated by an amplifier stage (Here, because the 120 section including amplifiers in for example 3a-3C, the claim language is believed to be met via the biasing at 121). With respect to claim 10, the circuit above discloses the electronic frequency mixer according to claim 6, wherein a duty cycle of the first periodic signal is identical to a duty cycle of the second periodic signal to within 5%. (Here, the duty cycle would be identical as the first periodic signal and second periodic signal are the same signal according to interpretation of the transistors being the transistors of Fig. 5C) With respect to claim 11, the circuit above disclose the electronic frequency mixer according to claim 6, wherein the front and back gates of the first transistor of each of the first and second pairs of transistors receive the first periodic signal in phase opposition , and wherein the front and back gates of the second transistor of each of the first and second pairs of transistors receive the second periodic signal in phase opposition (Here, the first and second pairs of transistors would receive the periodic signals in phase opposition according the interpretation of the transistors being the transistors of Fig. 5D). With respect to claim 14, Yakubo et al. discloses the electronic circuit according to claim 13, further comprising a circuit for receiving a radio frequency signal comprising: a) a low-noise amplifier (201) having an input coupled (via DUP) to the antenna (ANT); and b) the at least one mixer comprising a first mixer (202) and a second mixer (210), the radio frequency input signal of each of the first and second mixers being a signal originating from the low-noise amplifier (from 201), and but fails to disclose the first and/or the second periodic signal of the first mixer being phase-shifted by 90( π /2) with respect to the first and/or to the second periodic signal of the second mixer. Ipek teaches making differential the front gate and the backgate of inputs in a mixer (See [0017]-0018] “These dual-gated NFETs can each have two independently biasable gates including a front gate (also referred to herein as a primary gate) and a back gate (also referred to herein as a secondary gate) opposite the front gate.”) It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to bias the front gate and backgate (i.e. in figure 5D of Yakubo et al. make the front and back gate differential or offset by a specific value) in a differential format for the purpose of achieving a specific offset. With respect to claim 15, Yakubo et al. discloses the electronic circuit according to claim 13, further comprising a circuit for transmitting a radio frequency signal comprising: a) a power amplifier (211) having an output coupled to the antenna (ANT); and b) the at least one mixer (210 and 202) comprising a third mixer (202) and a fourth mixer (210), an output of each of the third and fourth mixers being coupled to the power amplifier (211), but fails to disclose the first and/or the second periodic signal of the third mixer being phase-shifted by 90( π /2) with respect to the first and/or to the second periodic signal of the fourth mixer. Ipek teaches making differential the front gate and the backgate of inputs in a mixer (See [0017]-0018] “These dual-gated NFETs can each have two independently biasable gates including a front gate (also referred to herein as a primary gate) and a back gate (also referred to herein as a secondary gate) opposite the front gate.”) It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to bias the front gate and backgate (i.e. in figure 5D of Yakubo et al. make the front and back gate differential or offset by a specific value ) in a differential format for the purpose of achieving a specific offset . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 7, the prior art of record fails to suggest or disclose wherein the circuit the electronic frequency mixer according to claim 6, wherein the mixer is a passive mixer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm) . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAREEM E ALMO/Examiner, Art Unit 2836 Application/Control Number: 19/020,078 Page 2 Art Unit: 2836 Application/Control Number: 19/020,078 Page 3 Art Unit: 2836 Application/Control Number: 19/020,078 Page 4 Art Unit: 2836 Application/Control Number: 19/020,078 Page 5 Art Unit: 2836 Application/Control Number: 19/020,078 Page 6 Art Unit: 2836 Application/Control Number: 19/020,078 Page 7 Art Unit: 2836 Application/Control Number: 19/020,078 Page 8 Art Unit: 2836 Application/Control Number: 19/020,078 Page 9 Art Unit: 2836 Application/Control Number: 19/020,078 Page 10 Art Unit: 2836
Prosecution Insights