Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6-8, 10 and 15-17 of U.S. Patent No. 12,210,399 in view of Vaidyu et al., US Patent No. 7,962,775.
Claim 1 of U.S. Patent No. 12,210,399 discloses the claim elements of claim 1 in the current Application except the main processor to transfer management of a timed function that is being managed by the main processor at a time when the main processor is instructed to enter itself into a quiescent state of operation to the co-processor prior to the main processor causing itself to enter into the quiescent state of operation.
Claim 10 of U.S. Patent No. 12,210,399 discloses the claim elements of claim 5 in the current Application except transferring management of a timed function that is being managed by the main processor at a time when the main processor is instructed to enter itself into a quiescent state of operation to the co-processor prior to the main processor causing itself to enter into the quiescent state of operation.
Vaidyu teaches a mobile device, wherein during operating/active state, while the high-level processor (main processor) is executing the regular low-level periodic system tasks (timed function), and upon the high-level processor detecting a dormant low-power sate condition or user request for entry into the dormant low-power state (FIG. 4, 404 – column 5, lines 56-59), the high-level processor (main processor) updates the shared information necessary to run the regular low-level system tasks and initiates the proxy software module on the base-band processor (FIG. 4, 406-408, column 5, lines 56-67), which transfers control of the execution for the low-level periodic system tasks to the base-band processor (co-processor), and after such transfer, the high-level processor (main processor) is deactivated to dormant low-power sate (FIG. 4, 410-412 – column 5, line 67 – column 6, line 3). Accordingly, the duration the high-level processor remains in the active state is reduced substantially as there is no requirement for the high-level processor to exit a dormant low power state to perform regular low-level system tasks. Thus, overall power consumption by a mobile electronic communications device implementing this scheme may be reduced (column 4, lines 10-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above described device and functionality as suggested by Vaidyu with claim 1 of U.S. Patent No. 12,210,399 to implement the main processor to transfer management of a timed function that is being managed by the main processor at a time when the main processor is instructed to enter itself into a quiescent state of operation to the co-processor prior to the main processor causing itself to enter into the quiescent state of operation; and with claim 10 of U.S. Patent No. 12,210,399 to implement transferring management of a timed function that is being managed by the main processor at a time when the main processor is instructed to enter itself into a quiescent state of operation to the co-processor prior to the main processor causing itself to enter into the quiescent state of operation. One of ordinary skill in the art would be motivated to do so in order to reduce the overall power consumption of the device.
In addition, the claim limitation of claims 2-4 are disclosed in respective claims 6-8 of U.S. Patent No. 12,210,399 and claims 6-8 are disclosed in respective claims 15-17 of U.S. Patent No. 12,210,399.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vaidyu et al., US Patent No. 7,962,775.
Regarding claim 1, Vaidyu discloses a battery-powered (FIG(s) 1-4), electronic device, comprising:
a memory for storing processor-executable instructions (the shared hardware resources include memory [not shown] storing OS and software instructions – FIG(s) 1-2, 110, 210, column 4, lines 34-44, column 5, lines 7-10);
a co-processor (base-band processor subsystem [FIG(s) 1-2, 106, 206], supplementing the execution of regular low-level system tasks [FIG. 2, 222] when the high-level processor subsystem [FIG. 2, 208] is in dormant low power state – column 4, lines 57-65, column 5, lines 18-27); and
a main processor (high-level processor subsystem – FIG(s) 1-2, 108, 208) coupled to the co-processor and the memory (FIG(s) 1-2) for executing the processor-executable instructions that causes the main processor to transfer management of a timed function (regular low-level periodic device tasks [FIG. 1-2, 122, 222], including network connection state information, signal strength updating, and system time updating are time functions – column 5, lines 28-30, lines 60-63) that is being managed by the main processor at a time when the main processor is instructed to enter itself into a quiescent state of operation to the co-processor prior to the main processor causing itself to enter into the quiescent state of operation (during operating/active state, while the high-level processor is executing the regular low-level periodic system tasks [column 4, lines 45-49], and upon the high-level processor detecting a dormant low-power sate condition or user request for entry into the dormant low-power state [FIG. 4, 404 – column 5, lines 56-59], the high-level processor updates the shared information necessary to run the regular low-level system tasks and initiates the proxy software module on the base-band processor [FIG. 4, 406-408, column 5, lines 56-67], which transfers control of the execution for the low-level periodic system tasks to the base-band processor, and after such transfer, the high-level processor is deactivated to dormant low-power sate [FIG. 4, 410-412 – column 5, line 67 – column 6, line 3]).
Regarding claim 5, Vaidyu discloses a method comprising all claim limitations addressed above for claim 1.
Regarding claims 4 and 8, Vaidyu further discloses the device and method, wherein the timed function comprises retransmission of a status (periodically obtaining network connection state information inherently discloses retransmission of a status – column 5, lines 60-63).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidyu et al., US Patent No. 7,962,775 in view of WO 0011839.
Regarding claims 2 and 6, Vaidyu disclose the device and method, as per claims 1 and 5, respectively.
Vaidyu does not specifically state the timed function comprises periodic transmission of a heartbeat signal.
WO 0011839 teaches a coprocessor generating a “heart beat” packet while the host processor or host system has been put to sleep (page 7, lines 28-30). Thus, signaling proper computer functionality to remote application while maintaining the computer system in a low power state (page 7, lines 30-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above-described functionality, as suggested by WO 0011839 with the device and method disclosed by Vaidyu in order to implement the timed function comprises periodic transmission of a heartbeat signal. One of ordinary skill in the art would be motivated to do so in order to ensure proper signaling for the device functionality to remote application while maintaining the high-level processing system in the dormant low-power state.
Claim(s) 3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidyu et al., US Patent No. 7,962,775 in view of Vaisnys et al., US Patent Appl. Pub. No. 2008/0136652.
Regarding claims 3 and 7, Vaidyu disclose the device and method, as per claims 1 and 5, respectively.
Vaidyu does not specifically state the timed function comprises periodic blinking of an indicator.
Vaisnys teaches and active status indicator (ASI) system (FIG. 2) periodically illuminating LED 235 in a green state to indicate that the host system is operating properly and further comprise changing the illumination state of LED 235 to red if the host system requires operator attention (paragraph 0072). Thus, providing a status indicator that is easy to notice and to interpret, yet also conserves remaining battery power (paragraphs 0002 and 0014).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above described functionality, as suggested by Vaisnys with the device and method disclosed by Vaidyu in order to implement the timed function comprises periodic blinking of an indicator. One of ordinary skill in the art would be motivated to do so in order to provide a status indicator that is easy to notice and to interpret, yet also conserves remaining battery power.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEFAN STOYNOV whose telephone number is (571)272-4236. The examiner can normally be reached 8AM - 4:30PM.
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/STEFAN STOYNOV/ Primary Examiner, Art Unit 2175
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