DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 6/2/2026 is acknowledged. The traversal is on the ground(s) that claims 1 and 13 appear to be generic to their respective Species. This is found persuasive and therefore claims 1-12, 34, 36, 38 and 40 are found to be timely elected as corresponding to the Species related to generic claim 1. However, claims 13-33, 35, 37, 39 and 41 remain withdrawn as being non-elected Species related to generic claim 13.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the transmission gate comprising a plurality of PMOS and a plurality of NMOS transistors must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-12, 34, 36, 38 and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2021/0167761).
In regards to claim 1, Liu discloses of a dynamic latch, comprising: an input terminal (504, 604) for inputting a first data; an output terminal (505, 605) for outputting a second data; a clock signal terminal for supplying a clock signal (not shown, but supplying CLKP and CLKN, see Paragraphs 0055, 0057-0059, 0061, 0063-0065, 0069-0070, 0073); a data transmission unit (501, 601) for transmitting the first data under control of the clock signal; and a data output unit (503, 603) for converting the first data into the second data, wherein the data transmission unit (501, 601) and the data output unit (503, 603) are sequentially connected in series between the input terminal (504, 604) and the output terminal (505, 605, see Figs 4A-D), and a node is provided between the data transmission unit (501, 601) and the data output unit (503, 603), and wherein the dynamic latch further comprises: a data retention unit (502, 602, 518, 618) electrically connected to the node (see Figs 4A-D).
In regards to claim 2, Liu discloses of the dynamic latch according to claim 1, wherein the data retention unit (502, 602, 518, 618) comprises a PMOS transistor (for example see 510-511, 610-611, 616) and/or a NMOS transistor (see 512-13, 612-613, 617 in Figs 4A-D).
In regards to claim 9, Liu discloses of the dynamic latch according to claim 1, wherein the clock signal comprises a first clock signal and a second clock signal in a opposite phase (for example CLKP, CLKN, see Paragraphs 0054-0071).
In regards to claim 10, Liu discloses of the dynamic latch according to claim 1, wherein the data transmission unit (501, 601) is a transmission gate (see Figs 4A-D).
In regards to claim 11, Liu discloses of the dynamic latch according to claim 10, wherein the transmission gate (for example see 200, 204 in Fig 1) comprises a plurality of PMOS transistors and a plurality of NMOS transistors connected in parallel, respectively (see Fig 1, data transmission units 300, 304 are located between the input terminal D, output terminal Q, data retention unit (comprised of 302, 308, 310) and a data output unit 305, with clock signals CLKP, CLKN).
In regards to claim 12, Liu discloses of the dynamic latch according to claim 1, wherein the data output unit (503, 603) is an inverter (see Figs 4A-D).
In regards to claim 34, Liu discloses of a data operation unit, comprising a control circuit, an operational circuit, and a plurality of dynamic latches interconnected with each other, wherein the plurality of dynamic latches are connected in series and/or in parallel, and the plurality of dynamic latches are the dynamic latch according to claim 1 (for example see Figs 4A-D, 7 and Paragraph 0082).
In regards to claim 36, Liu discloses of a chip, comprising at least one data operation unit, wherein at least one data operation unit comprises a control circuit, an operational circuit, and a plurality of dynamic latches interconnected with each other, wherein the plurality of dynamic latches are connected in series and/or in parallel, and the plurality of dynamic latches are the dynamic latch according to claim 1 (for example see Figs 4A-D, 7-8 and Paragraph 0082-0083).
In regards to claim 38, Liu discloses of a hash board for a computing device, comprising a chip, wherein the chip comprises at least one data operation unit, wherein at least one data operation unit comprises a control circuit, an operational circuit, and a plurality of dynamic latches interconnected with each other, wherein the plurality of dynamic latches are connected in series and/or in parallel, and the plurality of dynamic latches are the dynamic latch according to claim 1 (for example see Figs 4A-D, 7-9 and Paragraphs 0082-0084).
In regards to claim 40, Liu discloses of a computing device, comprising a power supply board, a control board, a connection board, a radiator and a plurality of hash boards, the control board is connected to the hash boards through the connection board, the radiator is disposed around the hash boards, the power supply board is configured to supply a power supply to the connection board, the control board, the radiator and the hash boards, wherein the hash boards each comprises a chip, wherein the chip comprises at least one data operation unit, wherein at least one data operation unit comprises a control circuit, an operational circuit, and a plurality of dynamic latches interconnected with each other, wherein the plurality of dynamic latches are connected in series and/or in parallel, and the plurality of dynamic latches are the dynamic latch according to claim 1 (for example see Figs 4A-D, 7-10 and Paragraphs 0082-0085).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 3, the prior art does not disclose of the dynamic latch according to claim 2, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to the node, and the gate terminal of the PMOS transistor is electrically connected to a power supply, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 4, the prior art does not disclose of the dynamic latch according to claim 2, wherein the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to the node, and the gate terminal of the NMOS transistor is electrically connected to a ground, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 5, the prior art does not disclose of the dynamic latch according to claim 2, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to a power supply, and the gate terminal of the PMOS transistor is electrically connected to the node, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 6, the prior art does not disclose of the dynamic latch according to claim 2, wherein the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to a ground, and the gate terminal of the NMOS transistor is electrically connected to the node, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 7, the prior art does not disclose of the dynamic latch according to claim 2, wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the PMOS transistor are electrically connected to a power supply, and the drain terminal of the PMOS transistor is electrically connected to the node, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 8, the prior art does not disclose of the dynamic latch according to claim 2, wherein the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the NMOS transistor are electrically connected to a ground, and the drain terminal of the NMOS transistor is electrically connected to the node, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Thurs 6:30am-3:00pm, Fri 6:30am-12:30pm.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2845
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