DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 19/020,409 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statements 01/14/2025, 02/19/2025 and 08/14/2025 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting over the claims of 1-19 of U.S. Pat. No. 12,511,041, 1-20 of U.S. Pat. No. 11,947,798, claims of 1-20 of U.S. Pat. No. 11,132,127 and claims of 1-20 of U.S. Pat. No. 10,126,947 and, since the claims, if allowed, would improperly extend the “right to exclude” already granted in patent. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lie et al. (US pub. # 2014/0185611), hereinafter, “Lie”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 14 and 18, Lie discloses an interconnect system (cluster compute server 100 of fig. 1) comprising: host devices (compute nodes 101-106 of fig. 1, as disclose in paragraphs 0021 and 0042. See also details of a compute node such as compute node 400 of fig. 4), respective ones (compute node 400) of the host devices including at least one interface [port 731, inside fabric switch 420. See fig. 7 and paragraph 0063, which discloses “node 710 of FIG. 7 illustrates an example implementation of this local translation caching technique. The node 710 can comprise a compute node, a peripheral resource node, a management node, and the like. In the depicted example, the node 710 includes a fabric switch 720 (corresponding to fabric switches 420, 520, and 620), a switch control 724, a crossbar switch 727, and ports 731, 732, 733, 734, 735, 736, and 737. The port 731 is connected to a packet formatter 728, which in turn is connected to the internal components of the node 710, and the ports 732-737 are connected to corresponding links of the fabric interconnect 112. The crossbar switch 727 forwards packets (or, more specifically, forwards flits that together represent a packet) between the ports 731-737 based on control signaling received from switch control 724. The switch control 724 determines which of the ports 731-737 is to serve as the egress port for a received packet based on the network location of the node associated with the destination MAC address of the packet and based on deterministic routing logic”] to communicate packet requests over respective packetized links (corresponding links of the fabric interconnect 112, as discloses in paragraph 0063; see figures 4 and 7) (see paragraphs 0042 and 0063), the respective ones of the host devices including local memory comprising a cache (memory 404 of fig. 4) (see paragraphs 0037 and 0050); one or more memory devices (one of storage nodes 107-109 of figures 1 and 6), respective ones of the one or more memory devices including at least one interface to receive and respond to the packet requests over the respective packetized links [see paragraph 0055, which discloses “FIG. 6 illustrates a storage node 600 implemented in the server 100 of FIG. 1 in accordance with some embodiments. The storage node 600 corresponds to, for example, storage nodes 107-109 of FIG. 1. As illustrated, the storage node 600 is configured similar to the network node 500 of FIG. 5 and includes a NIC 619 having a fabric switch 620, a packet formatter 618, and a local translation cache 642, which operate in the manner described above with reference to the fabric switch 520, the packet formatter 518, and the local translation cache 642 of the network node 500 of FIG. 5. However, rather than implementing a NIC, the storage node 600 implements a storage device controller 604, such as a SATA controller. A depacketized incoming request is provided to the storage device controller 604, which then performs the operations represented by the request with respect to a mass storage device 606 or other peripheral device (e.g., a USB-based device). Data and other responses from the peripheral device are processed by the storage device controller 604, which then provides a processed response to the packet formatter 618 for packetization and transmission by the fabric switch 620 to the destination node via the fabric interconnect 112”]; and a routing system (fabric switch 420 of figures 4 and 7; see paragraphs 0026 and 0063) to connect the host devices and the one or more memory devices (see figures 4 and 7 and paragraph 0053), the routing system comprising devices interconnected in a routing topology (see abstract, which discloses “a cluster compute server includes nodes coupled in a network topology via a fabric that source routes packets based on location identifiers assigned to the nodes, the location identifiers representing the locations in the network topology. Host interfaces at the nodes may be associated with link layer addresses that do not reflect the location identifier associated with the nodes. The nodes therefore implement locally cached link layer address translations that map link layer addresses to corresponding location identifiers in the network topology. In response to originating a packet directed to one of these host interfaces, the node accesses the local translation cache to obtain a link layer address translation for a destination link layer address of the packet. When a node experiences a cache miss, the node queries a management node to obtain the specified link layer address translation from a master translation table maintained by the management node”), respective ones of the devices comprising a switch and interfaces, the routing system to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links [see paragraph 0030, which discloses “in the server 100, messages communicated between nodes are segmented into one or more packets, which are routed over a routing path between the source node and the destination node. The routing path may include zero, one, or more than one intermediate node. As noted above, each node includes an interface to the fabric interconnect 112 that implements a link layer switch to route packets among the ports of the node connected to corresponding links of the fabric interconnect 112. In some embodiments, these distributed switches operate to route packets over the fabric 122 using source routing or a source routed scheme, such as a strict deterministic dimensional-order routing scheme (that is, completely traversing the torus network 200 in one dimension before moving to another dimension) that aids in avoiding fabric deadlocks. To illustrate an example of strict deterministic dimensional-order routing, a packet transmitted from the node at location (0,0,0) to location (2,2,2) would, if initially transmitted in the X dimension from node (0,0,0) to node (1,0,0) would continue in the X dimension to node (2,0,0), whereupon it would move in the Y plane from node (2,0,0) to node (2,1,0) and then to node (2,2,0), and then move in the Z plane from node (2,2,0) to node (2,2,1), and then to node (2,2,2). The order in which the planes are completely traversed between source and destination may be preconfigured and may differ for each node”], wherein the respective ones of the host devices are to communicate the packet requests over the respective packetized links to read data from memory of the one or more memory devices and to cache the data in respective caches of the host devices (see paragraph 0043), the host devices having shared access to memory of the one or more memory devices, and wherein the host devices are to communicate cache coherency traffic to each other over at least one of the respective packetized links [see paragraph 0042, which discloses “As illustrated, the fabric switch 420 implements a plurality of ports, each port interfacing with a different link of the fabric interconnect 112. To illustrate using the 3.times.3 torus network 200 of FIG. 2, assume the compute node 400 represents the node at (1,1,1). In this example, the fabric switch 420 would have at least seven ports to couple it to seven bi-directional links: an internal link to the packet formatter 418; an external link to the node at (0,1,1); an external link to the node at (1,0,1), an external link to the node at (1,1,0), an external link to the node at (1,2,1), an external link to the node at (2,1,1), and an external link to the node at (1,1,2). Control of the switching of data among the ports of the fabric switch 420 is determined based on integrated deterministic switching logic, which specifies the egress port based on the destination address (that is, destination fabric ID) indicated by the packet and based on the deterministic routing implemented in the server 100”].
3. As per claim 2, Lie discloses “The interconnect system of claim 1” [See rejection to claim 1 above], wherein the routing topology comprises one of a chain topology, a ring topology, a modified ring topology, a mesh topology (see paragraph 0016), or a crossbar topology.
4. As per claims 3 and 15, Lie discloses wherein the routing topology comprises a mesh topology (see paragraph 0016).
5. As per claim 4, Lie discloses wherein the routing system comprising the devices includes a hub (see paragraph 0004).
6. As per claims 5 and 16, Lie discloses wherein the devices of the routing system interconnected in the routing topology are to create multiple routing paths to route the packet requests and responses over the respective packetized links (see paragraph 0026 and fig. 1).
7. As per claim 6, Lie discloses wherein the devices of the routing system are to receive routing configuration information to route the packet requests and responses over the respective packetized links (see paragraph 0026 and fig. 1).
8. As per claim 7, Lie discloses wherein the interconnect system is to provide the host devices with access to memory of the one or more memory devices, and the packet requests comprise read requests and write requests to the memory of the one or more memory devices (see paragraphs 0043 and 0055).
9. As per claim 8, Lie discloses wherein the at least one of the respective packetized links is to provide direct messaging of the cache coherency traffic between the host devices (see paragraph 0043).
10. As per claim 9, Lie discloses wherein the respective ones of the devices of the routing system comprise semiconductor memory devices (see paragraph 0024 and fig. 4).
11. As per claims 10 and 18, Lie discloses wherein the one or more memory devices include a memory device comprising a crossbar switch and multiple memory dies (see fig. 7 and paragraph 0078).
12. As per claim 11, Lie discloses wherein the respective ones of the host devices comprise System on a Chip (SoC) devices (see paragraph 0077).
13. As per claim 12, Lie discloses wherein the respective ones of the one or more memory devices further include a controller, and the respective ones of one or more memory devices are to: receive a packet request through an interface of the memory device; pass the received packet request to the controller responsive to a determination that the received packet request indicates the memory device as a destination of the received packet request; and pass the received packet through another interface of the memory device toward another memory device responsive to a determination that the received packet request indicates the other memory device as the destination of the received packet request (see paragraphs 0050 and 0069).
14. As per claim 13, Lie discloses wherein the respective ones of the devices of the routing system further include a controller (see figures 4 and 7), and the respective ones of the devices of the routing system are to: receive a packet request through an interface of the device; pass the received packet request through a first other interface of the device toward a first other device responsive to a determination that the received packet request indicates the first other device as a destination of the received packet request; and pass the received packet request through a second other interface of the device toward a second other device responsive to a determination that the received packet request indicates the second other device as the destination of the received packet request (see paragraphs 0050 and 0069).
15. As per claims 17 and 20, Lie discloses wherein the coherency traffic includes coherency lookups and coherency invalidations (see paragraph 0062 and abstract of Lie).
16. As per claim 19, Lie discloses wherein the first host device comprises a first System on a Chip (SoC) device, the second host device comprises a second SoC device, and the routing system includes the device and additional devices interconnected in a mesh topology (see paragraphs 0016 and 0077).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights