Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. FR2400758, filed on January 26, 2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
In pages 1-2 of the remarks, Applicant states that claims 1-20 were rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter. In particular, Application states that the previous Office Action (“OA”) identifies two independent bases for this rejection: (i) that the term "piece of information" in claim 1 is a relative term rendering the claim indefinite, and (ii) that the claim limitation "a device for protecting a writing of data into at least one register of at least one first electronic circuit" invokes 35 U.S.C. § 112(f), but that the written description fails to disclose corresponding structure for the recited function. Claim 1 has been amended to no longer recite the term "piece of information" and "a device for protecting a writing of data into at least one register of at least one first electronic circuit." Claim 1 now recites structural elements, and requests withdrawal of the rejection under 35 U.S.C. § 112(b).
Examiner states that as the amendments of the claims overcome the rejections under 112(b), claims 1-11, and 13-20 have their rejections under 112(b) withdrawn.
In pages 2-3 of the remarks, Applicant states that claims 1-20 were rejected under 35 U.S.C. § 112(a) as failing to comply with the written description requirement. In particular, the written description rejections are based on: (i) that the specification fails to disclose corresponding structure for the function of "protecting a writing of data, "which the Office Action determined invokes 35 U.S.C. § 112(f), and (ii) that the specification does not adequately describe how the recited pieces of information function to enforce the requirements of the claimed verification table. In particular, the Specification recites, in paragraphs [0044]-[0045], a protection device 103 comprising a memory adapted to storing one or a plurality of verification tables 104, and paragraphs [0075]-[0083], detailed examples of verification tables 301, 302, and 303, each comprising, for each register, multiple columns of entries. Claim 1 has been amended to remove the language leading to the rejections, and Applicant requests withdrawal of the 112(a) rejections, as well as the claim interpretation invoking 112(f).
Examiner states that the independent claims have been amended to overcome the claim interpretation invocation under 112(f) based on insufficient structure, where the independent claims now recite three circuits comprising different portions of the invention. With regards to the 112(a) rejections that were made in the previous OA, an electronic system 100 with a main control circuit with a processor and at least one secondary circuit comprising at least one register is described in paragraphs [0040]-[0041], a protection device 103 that comprises a memory adapted to storing one or more of a plurality of verification tables in paragraph [0044]-[0045], verification tables described in Fig. 3, paragraphs [0075]-[0083]. However, the limitations as described in claim 6, that being “temporary or permanent” aspect of the data written to the verification tables is written, as there is no timer functionality in the event that the bits are temporarily written to the fourth bits. Furthermore, in amended claim 1, the limitations of limitation of “a third circuit comprising a memory storing a first verification table, wherein the first verification table comprises for each of the at least one register”, “at least one or more first bits, wherein the one or more first bits indicate the writing of data into the at least one register”, “and at least one or more second bits, wherein the one or more second bits indicate whether a data item has been written or not into the at least one register”, as although the Specification describes these limitations in paragraphs [0014]-[0016], [0044]-[0045], and [0076]-[0083], paragraph [0076] further describes the ‘one or more first bits’ as “verification table 302 comprises two columns Test1(Req) and Test2 (Forbid) […] two pieces of information concerning the writing of data into the register”, where the Specification merely repeats the claimed limitation. The Specification does not sufficiently describe how a single bit is utilized in a first verification table differs from multiple bits, as stated in “one or more bits” as while paragraphs [0077]-[0079] describe the multiple bits that are performed in each of tables (A)-(C) are shown in Fig. 3, how one bit is utilized as well as how operation would differ if only one bit compared to “more bits” being used is unclear. Furthermore, what the columns of “Word”, “Test1(Req)”, “Test2(forbid)”, “Test3”, and the “status” mean when the bits are set to either a value of 0 or 1, as indicated in Fig. 3, with paragraphs [0076]-[0083], remains unclear. Finally, there is no indication of memories as part of the protection device 103, where the protection device 103 appears to be a third circuit that is in the independent claims as claimed by the Applicant, and as a result, the third circuit containing a memory constitutes new matter as it was not previously described by the Specification. As a result of the amendments reiterating the language used in the Specification in sufficient detail with regards to the invention, Examiner withdraws the previous 112(a) rejections for claims 1-11, and 13-20, but new rejections under 112(a) are added in this Office Action as the amendments present issues not previously recited in the claims.
In pages 3-4 of the remarks, Applicant states that claims 1-20 were rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Barman (U.S. Publication No. 2020/0342924 Al). Independent claim 1 now recites three circuits, including “a first circuit comprising a processor, a second electronic circuitry comprising at least one register, and a third circuit comprising a memory storing a first verification table”. In page 4 of the remarks, Applicant states that Barman fails to disclose the amended limitations of “one or more first bits, wherein the one or more first bits indicate the writing of data into the at least one register” and “one or more second bits, wherein the one or more second bits indicate whether a data item has been written or not into the at least one register” because Barman's GCR 336 does not belong to any page and is not organized on a per-register basis. Applicant also states that Berman does not disclose or suggest a first verification table comprising the first bits and the second bits as required by claim 1.
Applicant's arguments filed July 10, 2026 have been fully considered but they are not persuasive. Examiner restates that Barman’s general configuration register (GCR) 336, as described in paragraph [0045[ of Berman, is included in the memory map as well as an ASE parameter, with the enabled state of the GCR (set to 1) allowing the device of Berman to write values to a previously locked functional register 322 after writing to a different register 322. Furthermore, the memory map described in Berman corresponds to the verification table, with different types of registers included, as well as the SLB register being the “one or more first bits”, and the GCR corresponding to “one or more second bits”. The “page” that the Applicant is referring to soft lock bits address page 334 (SLB address page), which is a table that corresponds to a byte present in the functional registers table 320, which itself is present in the memory map in Berman’s paragraph [0045], as well as Fig. 4. The GCRs of MS (mode select) and PS (page select) are described with the SLBs in Fig. 11, where the GCR bits are shown to be closely related to the SLBs, despite the GCRs not being part of any SLB page. Finally, the MS control parameter indicates whether access by a master module to functional registers in the SLB page is in normal access mode or auto-lock mode where the register is locked after setting the corresponding SLB, as described in paragraph [0028]. Both of the registers are included in the memory map of Berman, Fig. 11. As a result of the rejections being maintained, claims 1-5, 7-9, 11-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barman.
In page 5 of the remarks, Applicant states that claims 1-20 were rejected under 35 U.S.C. § 103 as being unpatentable over Barman in view of Fetik (U.S. Publication No. 2014/0020083 Al). Applicant respectfully traverses this rejection for at least the following reasons. Claim 6 depends from claim 5, which depends from claim 1, and claim 18 depends from claim 17, which depends from claim 13. The Office Action relies on Barman, not Fetik, for the base limitations of claims 1, 5, 13, and 17. As respectfully submitted above, the amended independent claims are not disclosed by the prior art and, thus, are allowable.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. As a result of the arguments not arguing the rejections made to the aforementioned claims under 103, claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Barman in view of Fetik.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claim 1, the limitation of “a third circuit comprising a memory storing a first verification table, wherein the first verification table comprises for each of the at least one register”, and “at least one or more first bits, wherein the one or more first bits indicate the writing of data into the at least one register” is recited in paragraphs [0014]-[0016], and paragraph [0076] further describes the ‘one or more first bits’ as “verification table 302 comprises two columns Test1(Req) and Test2 (Forbid) […] two pieces of information concerning the writing of data into the register”, where the Specification merely repeats the claimed limitation. Paragraph [0076] further describes that “the first column Test1(Req) stores information indicating whether or not the writing of a data item is required in the associated register”, which is not further described as to how the Test1(req) column of the verification table enforces the requirement of the writing of data onto the associated register, and the Specification does not appear to clarify how the claimed limitation of a one or more first bits of the verification table to require writing of data is performed in the context of the invention.
The independent claims are also rejected for stating new matter, that being “a third circuit comprising a memory storing a first verification table, wherein the first verification table comprises for each of the at least one register“, as nowhere in the Specification is it described that a third circuit contains a memory that stores a first verification table that stores at least one register. Despite Applicant stating that paragraphs [0044]-[0045] stating in the remarks that “a protection device 103 comprising a memory adapted to storing one or a plurality of verification tables 104” as well as Fig. 1, as well as the protection device 103 storing one or a plurality of verification tables 104 (MAP) that can contain one or more registers in each of the tables, there is no indication of memories as part of the protection device 103, where the protection device 103 appears to be a third circuit that is in the independent claims as claimed by the Applicant, where this limitation constitutes new matter as it was previously not described in the Specification.
Furthermore, the claim limitation of “and at least one or more second bits, wherein the one or more second bits indicate whether a data item has been written or not into the at least one register” is described in paragraphs [0014]-[0015], and paragraph [0045] further describes the “information 1043 (STATUS) indicating whether a data item has been written into the register”, with paragraph [0061] describing step 207 of Fig. 2 as determining whether a data item has been written into a register Reg(i) is modified to show that a data item is written, and verifies if no data has been written into the register. However, it is not stated in further detail as to how the verification in step 207 is performed to indicate that no data was previously written into the register.
Furthermore, the claim limitations that state “one or more bits”, for either the first bits or the second bits as indicated in the independent claims as recited above are insufficiently recited in the Specification as to how a single bit, in the event that one bit is utilized in a first verification table differs from multiple bits, as stated in “one or more bits”. Furthermore, the Specification does not describe how ”more bits” are indicated in the first verification table, as while paragraphs [0077]-[0079] describe the multiple bits that are performed in each of tables (A)-(C) are shown in Fig. 3, how one bit is utilized as well as how operation would differ if only one bit compared to “more bits” being used is unclear, as described in the independent claims as well as the dependent claims. Furthermore, what the bits as shown in the verification tables (A)-(C) in Fig. 3 are insufficiently described, particularly as to what the columns of “Word”, “Test1(Req)”, “Test2(forbid)”, “Test3”, and the “status” mean when the bits are set to either a value of 0 or 1, as indicated in Fig. 3, with paragraphs [0076]-[0083].
Dependent claims 2-12 inherit the rejections of their respective independent claims that have been rejected, and as a result, are also rejected for similar reasons as claim 1 above.
Claim 6 recites “the device of claim 5, wherein the one or more fourth bits indicate: whether a value of the data item to be written is authorized or not; whether the data item to be written has priority or not; or whether the data item to be written is temporary or permanent”, and as the issues described in claim 6 regarding the “one or more fourth bits indicate […] authorized or not […] temporary or permanent”, as claim 6 does not further clear up how the authorization to be written into the register is performed in the invention, nor how the “temporary or permanent” aspect of the data written to the verification tables is written, as there is no timer functionality in the event that the bits are temporarily written to the fourth bits.
Independent claim 13 recites similar limitations as described in claim 1 above, and is also rejected for similar reasons as claim 1 above.
Dependent claims 14-20 inherit the rejections of their respective independent claims that have been rejected, and as a result, are also rejected for similar reasons as claim 13 above. Furthermore, dependent claims 14-20 also inherit the rejections of dependent claims 2-8, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 11-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barman et al. (US 20200342924 A1), hereinafter Barman.
Regarding claim 1, Barman discloses “a system comprising: a first circuit comprising a processor” ([0029] Fig. 3, Electronic circuit 300. Circuit 300 comprises a system on a chip (SOC) having multiple cores, memories, and other components, where multiple cores corresponds to cores on a processor.);
“a second electronic circuitry comprising at least one register” ([0045] Fig. 4, each row of the memory map corresponds to at least one register, up to 2^n-2 registers.);
“and a third circuit comprising a memory storing a first verification table, wherein the first verification table comprises for each of the at least one register” ([0045] Fig. 4, memory map includes soft lock bits address page 334 (SLB address page) is a table that corresponds to a byte present in the functional registers table 320, and each row corresponds to at least one register, up to 2^n-2 registers. Memory map is also displayed in Fig. 11, paragraph [0087], including SLBs/SLB address page 334 and general configuration register 336 present in the memory map 1100 in Fig. 11.);
“at least one or more first bits, wherein the one or more first bits indicate the writing of data into the at least one register” ([0054] When an SLB is set (1), the corresponding functional register is locked, in other words, not allowed to be written to. When reset (0), writing is allowed.);
“and at least one or more second bits, wherein the one or more second bits indicate whether a data item has been written or not into the at least one register” ([0045] Fig. 4, memory map includes general configuration register (GCR) 336 includes an ASE parameter, and when it is enabled (set to 1), the device writes to a previously locked functional register 322, after data was just written to a different functional register. ASE corresponds to the second piece of information. Paragraph [0085] describes the "just-written-to" functional register, which leaves the same functional register unlocked.);
Regarding claim 2, Barman discloses the device of claim 1 as described above. Barman also discloses “wherein the one or more first bits indicate whether a data writing is required in the at least one register” ([0054] When an SLB is set (1), the corresponding functional register is locked, in other words, not allowed to be written to. When reset (0), writing is allowed.).
Regarding claim 3, Barman discloses the device of claim 1 as described above. Barman also discloses “wherein the first verification table comprises, for each of the at least one register, one or more third bits, wherein the one or more third bits indicate the writing of data into the at least one register” ([0054] Hard lock bit (HLB) present in GCR 336, and when HLB is enabled (set to 1), all SLBs are write protected and cannot be modified, when cleared by hardware reset, allows writing to occur.).
Regarding claim 4, Barman discloses the device of claims 1 and 3 as described above. Barman also discloses “wherein the one or more third bits indicate whether a data writing is authorized in the at least one register” ([0054] When HLB is enabled (set to 1), all SLBs are write protected and cannot be modified, when cleared by hardware reset, allows writing to occur.).
Regarding claim 5, Barman discloses the device of claim 1 as described above. Barman also discloses “wherein the first verification table comprises, for each of the at least one register, one or more fourth bits, wherein the one or more fourth bits indicate the writing of data into the at least one register” ([0056] Page selection (HLB) parameter is present in GCR 336, and when HLB is enabled (set to 1), selects either the functional page registers or the SLB page of their respective registers.).
Regarding claim 7, Barman discloses the device of claim 1 as described above. Barman also discloses “wherein the first verification table is used during a data writing comprised in an implementation of a first instruction by the processor” ([0045] Fig. 4, memory map includes soft lock bits (SLBs) and the GPR is referenced whenever a write operation occurs.).
Regarding claim 8, Barman discloses the device of claims 1 and 7 as described above. Barman also discloses “wherein the third circuit further stores a second verification table” ([0028] Fig. 3, mode select (MS) parameter indicates whether access by the master module to functional registers is in a normal access mode or an auto-lock access mode where each written-to functional register is locked by settings the corresponding SLB. [0088] The MS control allows for virtually the same functionality as two verification tables to exist without needing to mirror the address space 220 of Fig. 2.).
Regarding claim 9, Barman discloses the device of claims 1, and 7-8 as described above. Barman also discloses “wherein the second verification table is used during a data writing in an implementation of a second instruction by the processor, different from the first instruction” ([0088] Addition of the MS control parameter to indicate selection of either the normal access mode or the auto-lock access mode eliminates the need for the mirrored address space, but the MS parameter provides virtually the same resources as a second verification table to be adapted for data writing for a second instruction.).
Regarding claim 10, Barman discloses the device of claim 1 as described above. Barman also discloses “further comprising a fourth electronic circuitry comprising at least one register, different from the second electronic circuitry, wherein the first verification table further comprises one or more fifth bits, wherein the one or more fifth bits indicate a writing of data into the at least one register of the fourth electronic circuitry” ([0030] Fig. 3, although only one of each module (master module 310, protected module 320, and protection module 330) is present, there can be multiple of each module in the circuit 300, where "each master module 310 may access more than one protected module 320, each protected module 320 may be accessed by different master modules 310, but by only one master module 310 at a time, and each protection module 330 may protect more than one protected module 320 [...] each protected module 320 is protected by only one protection module 330", and as a result of different modules present, a different master module can correspond to a second electronic circuit different from the first electronic circuit.).
Regarding claim 11, Barman discloses the device of claim 1 as described above. Barman also discloses “wherein the second electronic circuitry modifies the first verification table” ([0087] Fig. 11, memory map 1100 is part of the protected module 320 and protection 330, associated with circuit 300. [0001] Circuit is utilized to preventing unintended write operations from being written to functional registers of hardware IP modules, which is also performed in circuit 300.).
Regarding claim 13, Barman discloses the method with limitations that are also present in the device of claim 1 as described above.
Regarding claim 14, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 2 above.
Regarding claim 15, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 3 above.
Regarding claim 16, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 4 above.
Regarding claim 17, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 5 above.
Regarding claim 19, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 7 above.
Regarding claim 20, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 8 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Barman in view of Fetik (US 20140020083 A1), hereinafter Fetik.
Regarding claim 6, Barman discloses the device of claims 1 and 5 as described above. Barman also discloses “wherein the one or more fourth bits indicate: whether a value of the data item to be written is authorized or not” ([0064] When automatic page switching is enabled, and when PS is set to 0, selecting the functional page registers, the writing occurs after the SLB is reset to unlock the functional register, allowing writing to the register to occur.).
Barman does not appear to disclose or suggest, but Fetik teaches “whether the data item to be written has priority or not” ([0377] Prioritization of read-write accesses is taken into consideration via a scheduling component.);
or “whether the data item to be written is temporary or permanent” ([0039] Invention can filter or control access to any computer or digital storage, with both long term (CDs, tapes, disks) storage or temporary (RAM) storages.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "whether the data item to be written has priority or not" and “or whether the data item to be written is temporary or permanent” in an device for protecting a writing of data into at least one register of at least one first electronic circuit, and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to determine the importance of processes occurring, as the read-write access is determined by a scheduling component, and using a value from 0 to 100, with 100 representing the highest priority access to assist with the storage firewall to run analysis on disk access attempts (Fetik, [0023], [0377]-[0378]).
Regarding claim 18, Barman discloses the method of claim 13 as described above. Barman also discloses the limitations of claim 6 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.M./Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/Supervisory Patent Examiner, Art Unit 2496
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