DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 10 and 15 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 10
What claim 10 requires
What is already required in claim 1
“the status register stores the status information as a set of bits”
“the status register storing the status information as a set of bits”
“a subset of bits of the set of bits are designated for the indicator of the predicted completion time for the array operation”
“a subset of bits in the set of bits of the status register that are designated for storing the predicted completion time for the array operation” where the status bits comprise “an indicator of a predicted completion time for the array operation”
Accordingly, the Examiner cannot find a requirement in the limitations of claim 10 that is not already required by the limitations in claim 1.
Regarding claim 15:
What claim 15 requires
What is already required in claim 14
“the obtaining the status information comprises accessing the subset of bits from the status register”
“obtaining… the status information…” which is stored “as a set of bits”, where the status information includes “an indicator of a predicted completion time” which is stored “as a subset of bits in the set of bits of the status register”.
Accordingly, the Examiner cannot find a requirement in the limitations of claim 15 that is not already required by the limitations in claim 14 as claim 14 requires obtaining the status information stored as a plurality of bits including a subset of bits that represent the predicted completion time, which would appear to necessarily require accessing the subset of bits from the status register as part of “obtaining the status information” which includes the predicted completion time stored as a subset of its own set of bits. By analogy, if I pick up a bucket of apples, I have also necessarily picked up every subset of apples in that bucket as well – therefore, accessing a set of bits representing status information also necessarily includes accessing a subset of the set of bits as well.
Regarding claims 10 and 15:
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 8-11, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2022/0328109 A1 (Weinberg) in view of the Open NAND Flash Interface (ONFI) Specification, Revision 5.2, dated 27 February 2024 (ONFI_5.2) in further view of US Patent Application Publication No. US 2017/0206033 A1 (Ma).
Regarding claim 1 and analogous claims 14-15 and 19:
Weinberg discloses, a memory sub-system (110) comprising: a memory device ((130), which includes an array of non-volatile memory cells, which may be grouped into one or more LUNs [0010] [0029-0031]) with an associated status register (by disclosing that a memory device may have its status read with a read status command sent to the memory device, where the memory device may provide a response including status information stored in a status register associated with the memory device [0015]. The status register (221) may be stored in a local memory (119) or other locations [0056]) a processing device ((117) which may perform the operations of the almost ready management component (113) by executing instructions stored in a local memory (119) [0033]), operatively coupled with the memory device ((130) [0032-0035] [0039]), to perform operations comprising: polling the memory device for status information about an array operation being performed at the memory device (by disclosing that the almost ready management component (113) performs status polling to determine if the set of memory cells of the memory device is almost ready to complete execution of an operation [0038]. Status polling includes sending a read status command to the memory device [0015]. The almost ready status indicates that an operation involving memory cells of the memory device (including an array [0029-0031]) is in progress, but is not yet completed, but a current level of completion of the operation satisfies an almost ready threshold [0020]); obtaining the status information from the status register of the memory device based on the polling; (by disclosing determining that the memory cells of the memory device may have an almost ready status [0038], which may be determined by status polling reading the status register [0015]. The status register includes a plurality of status information [0057-0060]) the status register storing the status information as a set of bits (the status information may include 8 bits, or 64 or 128 or some other number of bits [0058], the status information comprising an indicator of an almost ready status for the array operation, the almost ready status for the array operation being represented by a subset of bits in the set of the status register that are designated for storing the almost ready status for the array operation (by disclosing that the status register stores status information in a plurality of bits, such as 8, 64, 128 etc. [0057]. The status register contains other information that just the almost ready status indication, and accordingly, only stores the almost ready status indication in a subset of the bits, such as bit 4, or another collection of bits in the status register [0057-0060]. The almost ready status indicates whether the operation being performed on the memory array (130) is nearly complete [0011] [0029-0030] [0038]) and adjusting one or more polling parameters based on the status information (by disclosing that based on determining that the memory cells have the almost ready status, performing status polling at a second interval [0038]).
Weinberg does not explicitly disclose, but ONFI teaches the memory device comprising the status register (by teaching that the command “read status” returns the composite status value for the status register bits of a LUN of the memory device (of which there are one or more), and indicates the busy/not busy status of the planes, as well as the fail status of the operation [pg. 3, §1.3.1.2 LUN] [pg. 4, §1.3.1.16 SR[]] [pg. 312: §6.10 Read Status Definition]. The read status is returned over the DQ[7:0] pins of the ONFI interface in response to the “read status” command [Fig. 6-16] [Table 6-10]. The status register includes a plurality of bits that are read with the “read status” command [pg. 318, ¶6.13 Status Field Definition]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the interface between the memory subsystem controller (115) and the memory device (130), including a LUN, which is sent the status polling commands as taught by Weinberg to be an ONFI interface compatible with the ONFI Revision 5.2 that performs the status read commands to the status register including a plurality of bits as taught by ONFI_5.2, such that the status register is stored in the LUN of the memory device as taught by ONFI_5.2
One of ordinary skill in the art would have been motivated to make this modification because Weinberg teaches the status register may be stored in other possible locations, and ONFI provides a standardized NAND Flash Device Interface that provides means for a system to be designed that supports a range of NAND flash devices without direct design pre-association to allow a system to seamlessly make use of new NAND devices that may not have existed at the time the system was designed as taught by ONFI_5.2 in [pg. 1, §1.1 Goals and Objectives].
Weinberg in view of ONFI_5.2 do not explicitly disclose, but Ma teaches that a status register can provide a predicted completion time (by teaching that a status register can provide an estimated completion time of an operation on the memory device, which can be used to modify a polling time (i.e., such as delaying the polling at the first interval taught by Weinberg) if it can provide a good estimate of how long the block access to a memory device will take [0104]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the status register including a variety of status information stored in subsets of bits among multiple bits of the status register as taught by Weinberg to additionally include the estimated completion time as taught by Ma; and to have modified polling at the first interval as taught by Weinberg to be delayed for an amount of time based on the estimated completion time as taught by Ma.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the CPU to go off and do other useful works before the next polling and reduce unnecessary CPU polling as taught by Ma in [0104].
Regarding claim 3:
The memory sub-system of claim 1 is made obvious by Weinberg in view of ONFI_5.2 in further view of Ma (Weinberg-ONFI_5.2-Ma).
Weinberg further discloses, wherein polling the memory device comprises sending one or more operation status commands to the memory device (by disclosing that the status polling is performed by sending “read status” commands to the memory device [0015] [0051]).
Regarding claim 4:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg further discloses, wherein polling the memory device comprises sending an initial operation status command to the memory device (by disclosing that the memory device performs status polling at a first interval when the memory device does not have the almost ready status, which would include at least an initial polling command (operation status command) [0015] [0020-0021]) wherein the operations comprise sending one or more follow-up operation status commands to the memory device (by disclosing that the memory device performs status polling at a first interval when the memory device does not have the almost ready status, and then at a second interval when the memory device does have the almost ready status, which would include sending multiple status polling commands (operation status commands) to the memory device [0015] [0020-0021]).
Regarding claim 6 and analogous claim 16:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg further discloses, wherein the adjusting of the one or more polling parameters comprises adjusting a polling interval parameter, the polling interval parameter defining a time period between operation status commands (by disclosing that the ready memory management component (113) will continue polling (sending “read status” commands) to the memory device at the first interval (for example, once every 50 μs) (one or more follow-up operation status commands) until the memory device returns an “almost ready” status, at which point the almost ready management component may switch to polling at a second interval (for example, once every 1 μs) (adjust a polling interval parameter) [0020-0021]).
Regarding claim 8 and analogous claim 17:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg further discloses, wherein the status information comprises one of: a loop count, an estimated remaining loops to completion, and a forward progress indicator (by teaching that the status information may include information related to an almost ready/not almost ready status of the memory cells of the memory device stored in a register, which may indicate that the current level of completion has reached an almost ready threshold (i.e., forward progress indicator) [0038] [0041] [0043-0047]).
Regarding claim 9 and analogous claims 18 and 20:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg further discloses, wherein the operations comprise adjusting a timing parameter associated with the array operation based on the status information (by disclosing that the ready memory management component (113) will continue polling (sending “read status” commands) to the memory device at the first interval (for example, once every 50 μs) until the memory device returns an “almost ready” status, at which point the almost ready management component may switch to polling at a second interval (for example, once every 1 μs) (adjusting a timing parameter associated with the array based on the status information) [0020-0021]).
Regarding claim 10:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg-ONFI_5.2-Ma make obvious, wherein the status register stores the status information as a set of bits, wherein a subset of bits of the set of bits are designated for the indicator of the predicted completion time for the array operation (through the analysis performed for claim 1).
Regarding claim 11:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg-ONFI_5.2-Ma makes obvious, wherein the obtaining of the status information comprises accessing the subset of bits from the status register (through the analysis performed for claim 1).
Regarding claim 13:
The memory sub-system of claim 11 is made obvious by Weinberg-ONFI_5.2-Ma in view of ONFI_5.2.
Weinberg does not explicitly disclose, but ONFI_5.2 teaches, comprising a communication interface to communicatively couple the processing device with the memory device, wherein the communication interface comprises at least one of an open NAND flash interface (ONFI) bus and a separate command address (SCA) bus, wherein the processing device accesses the status information from the status register via the communication interface (by teaching that the command “read status” returns the composite status value for the status register bits, and indicates the busy/not busy status of the planes, as well as the fail status of the operation [pg. 312: §6.10 Read Status Definition]. The read status is returned over the DQ[7:0] pins of the ONFI interface in response to the “read status” command [Fig. 6-16] [Table 6-10]. The status register includes a plurality of bits that are read with the “read status” command [pg. 6.18, ¶6.13 Status Field Definition]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the interface between the memory sub-system controller and the memory device for performing the status polling commands to read the status register as taught by Weinberg to be an ONFI interface compatible with the ONFI Revision 5.2 that performs the status read commands to the status register including a plurality of bits as taught by ONFI_5.2.
One of ordinary skill in the art would have been motivated to make this modification because ONFI provides a standardized NAND Flash Device Interface that provides means for a system to be designed that supports a range of NAND flash devices without direct design pre-association to allow a system to seamlessly make use of new NAND devices that may not have existed at the time the system was designed as taught by ONFI_5.2 in [pg. 1, §1.1 Goals and Objectives].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Weinberg-ONFI_5.2-Ma in further view of the paper by Lucas Jellema titled, “Downsizing the Data Set – Resampling and Binning of Time Series of other Data Sets”, 16 September 2019, AMIS Technology Blog – Oracle & Microsoft Azure, as preserved by the Internet Archive on 22 January 2021, pgs. 1-18 (Jellema).
Regarding claim 2:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg does not explicitly disclose, but Ma teaches, wherein the subset of bits comprise a value corresponding to time remaining until completion of the array operation (by teaching that a status register can provide an estimated completion time of an operation on the memory device, which can be used to modify a polling time (i.e., such as the initial polling time taught by Weinberg) if it can provide a good estimate of how long the block access to a memory device will take [0104]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the polling at the initial interval and to have modified the status register including a variety of status information stored in subsets of bits among multiple bits of the status register as taught by Weinberg to include modifying the status register to additionally include the estimated completion time, and modifying the initial interval based on an estimated completion time of the operation being performed on the memory device as indicated by the estimated completion time indicated by the status register as taught by Ma.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the CPU to go off and do other useful works before the next polling and reduce unnecessary CPU polling as taught by Ma in [0104].
Weinberg does not explicitly disclose, but Jellema teaches the value should correspond to one of a plurality of predefined time ranges (by teaching that time data can be represented with a reduced resolution by binning the data into a reduced “alphabet” that may be represented with only a few bits. In this way, each bin represents a useful range of time that is not stored with unneeded resolution and therefore saves space while still having enough resolution to be actually useful [pg. 1, ¶1 – pg. 2, ¶1] [pg. 7, ¶1 – pg. 11, last ¶ carried over onto pg. 12]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the estimated completion times until the array operation is completed stored in the status register as taught by Cariello-Weinberg-Ma to be represented with bins that represent ranges of time values at a reduced resolution as taught by Jellema.
One of ordinary skill in the art would have been motivated to make this modification because often the resolution of data sets is unnecessarily large, which leads to wasted storage space, and reducing the resolution of the data can reduce the needed storage space while still maintaining enough resolution to be useful as taught by Jellema in [pg. 1-2] and [pg. 11].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Weinberg-ONFI_5.2-Ma in further view US Patent Application Publication No. US 2020/0401339 A1 (Sun).
Regarding claim 5:
The memory sub-system of claim 4 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg discloses, and a polling interval parameter that defines a second time period between sending follow-up operation status commands (by teaching the second interval that defines a time period between follow-up polling status commands [0015] [0021-0022])
Weinberg does not explicitly disclose, but Sun teaches, wherein the one or more polling parameters comprise: an initial delay parameter that defines a first time period between initiating the array operation at the memory device and sending the initial operation status command to the memory device (by disclosing an initial polling time (To), which is a time to wait to perform the first polling command (an initial delay parameter that defines a first time period between initiating the array operation at the memory device and sending the initial operation status command to the memory device), and then one or more other polling interval times which may be used after the initial polling time [See Fig. 5]. The polling times may be set based on the type of operation being performed and based on statistics of past command performance [0037] [0039-0041] [0058] [0065])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the polling at the first interval as taught by Weinberg to only occur after an initial interval that is determined based on statistical command performance as taught by Sun.
One of ordinary skill in the art would have been motivated to make this modification because this can set polling times with a better balance between issuing too many requests and improving the performance of the flash memory by not waiting too long to poll the memory device for its status as taught by Sun in [0067].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Weinberg-ONFI_5.2-Ma in view of US Patent Application Publication No. US 2016/0085465 A1 (Schmier).
Regarding claim 7:
The memory sub-system of claim 1 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg does not explicitly disclose, but Schmier teaches, wherein the adjusting of the one or more polling parameters comprises configuring a polling parameter such that no additional operation status commands are sent as part of polling to the memory device for the status information associated with the array operation (by teaching that if the read status in response to a polling status command (374) is a Busy (375) Error (376) status, which is confirmed by another status command (377) returning a Busy (378) Error (379) status, then the error status of a command such as a program command (array operation) may be confirmed and validated (E) [Fig. 4D], and no more polling status commands are sent (adjusting of the one or more polling parameters comprises configuring a polling parameter such that no additional operation status commands are sent as part of polling to the memory device), but instead a remedial action is performed, such as marking the block as a bad block [Fig. 4D] [0094]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified receiving the status from the memory device in response to the status request commands as taught by Weinberg with the ability to check and verify an error status, such that polling could end and the block could be marked as a bad block as taught by Schmier.
One of ordinary skill in the art would have been motivated to make this modification because ascertaining an accurate status of the storage with respect to memory operations, for example, ascertaining whether an operation has completed or failed, is necessary to ensure proper operation and endurance of the storage device as taught by Schmier in [0004].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Weinberg-ONFI_5.2-Ma in view of the article titled “Everything You Need to Know About Shift Registers”, published by IC Components Limited as preserved by the Internet Archive on 10 August 2024 (IC_Components).
Regarding claim 12:
The memory sub-system of claim 11 is made obvious by Weinberg-ONFI_5.2-Ma.
Weinberg does not explicitly disclose, but IC_Components teaches, wherein the subset of bits are accessed from the status register in multiple clock cycles (by teaching that the data in the register should be stored in a parallel-in, serial-out (PISO) shift register [pg. 2, last ¶]. They allow multiple bits of data to enter the register simultaneously in parallel, and then once the data is loaded, they shift the data out one bit at a time (according to the clock signal CLK – see circuit diagram in [Fig. 3]. In this way, data can be collected in parallel and converted to a serial form for transmission to a microcontroller, which facilitates efficient data communication [pg. 3, ¶1]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the multiple bit status register as taught by Weinberg to be a PISO shift register as taught by IC_Components.
One of ordinary skill in the art would have been motivated to make this modification because a PISO shift register allows for efficient data communication as taught by SR in [pg. 3, ¶1]. A serial shift register is efficient in terms of input/output pin usage, requiring only a single data line, and reducing the need for multiple data wires, physical connections, and reduces failure points as taught by IC_Components in [pg. 4, ¶¶1, 4-8]. Parallel data loading quickly loads large amounts of data into a system, and facilitate fast data exchange and high speed-data transfer as taught by IC_Components in [pg. 4, ¶2]. Also, shift registers are used to store and retrieve data in various memory applications to provide efficient data storage solutions with minimal circuitry, enabling efficient memory operations in computers as taught by IC_Components in [pg. 4, ¶6]. Shift registers offer low power consumption, cost effectiveness, and ease of use as taught by IC_Components in [pg. 5, ¶¶1-3]. Finally, shift registers are useful when you need to store data temporarily (such as storing the status information of a memory operation as taught by Weinberg) as taught by IC_Components in [pg. 8, ¶1].
Response to Arguments/Amendments
In response to the amendments to the claims, a new 35 USC §112(d) rejection has been made to claim 10.
In response to the amendments to the claims, the 35 USC §102 rejections have been withdrawn, and the 35 USC §101 rejection has been withdrawn.
In response to the amendments to the claims, the 35 USC §103 rejections have been updated as necessitated by the newly amended limitations to include rejections based on Weinberg-ONFI_5.2-Ma with combinations of Jellema, Sun, Schmier, and IC_Components.
Applicant’s arguments regarding Ma are not persuasive as the rejection is based upon a combination of references. For example, Applicant argues that Ma does not provide “further detail regarding how [the estimated completion time] is stored or provided by the ‘completion status register’”. However, Ma was not relied upon for these details. Instead, Ma was used to modify Weinberg, which already teaches a status register that stores a plurality of bits, where different subsets of the bits are designated to indicated different status information. Accordingly, one of ordinary skill in the art looking at the combination of Weinberg in view of Ma would have recognized that the predicted completion time taught by Ma could have been stored as an additional one of the different subsets of bits that are designated to store different status information as taught by Weinberg. Accordingly, the claimed limitation would have been obvious and Applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CURTIS JAMES KORTMAN whose telephone number is (303)297-4404. The examiner can normally be reached Monday through Friday 7:30 AM through 4:00 PM MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
Prosecution Insights