DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
35 USC § 112(f)
NOTE: Because the "means plus function" limitations of claims 35 and 50 meet the 3-prong analysis set forth in MPEP 2181, claims 35 and 50 are being treated under 35 U.S.C. 112(f).
The agile ring oscillator (104) is identified as the corresponding structure for the “means for generating phases ...” limitation.
The ARO controller (120) is identified as the corresponding structure for the “means for controlling” limitation.
The ARO controller (120) is identified as the corresponding structure for the “means for maintaining first and second calibration controls” limitation.
The ARO controller (120) is identified as the corresponding structure for the “means for maintaining first and second slower controls” limitation.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-48 of U.S. Patent No. 10,998,910. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-50 of the instant application are merely broad presentations of claims 1-48 of U.S. Patent No. 10,998,910.
Claims 1-50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-38 of U.S. Patent No. 11,296,712. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-50 of the instant application are merely broad presentations of claims 1-38 of U.S. Patent No. 11,296,712.
Claims 1-50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-37 of U.S. Patent No. 11,545,988. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-50 of the instant application are merely broad presentations of claims 1-37 of U.S. Patent No. 11,545,988.
Claims 1-50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-37 of U.S. Patent No. 11,936,394. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-50 of the instant application are merely broad presentations of claims 1-37 of U.S. Patent No. 11,936,394.
Claims 1-50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-35 of U.S. Patent No. 12,231,134. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-50 of the instant application are merely broad presentations of claims 1-35 of U.S. Patent No. 12,231,134.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 15, 19, 20, and 35 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Olariu (US 2021/0075432).
Regarding claim 1, Olariu teaches a circuit (figure 1) comprising:
an agile ring oscillator (117/150) configured to generate phases of an output clock (multi-phase output clock ph1-phk); and
an ARO controller (120) configured to control durations (The selection signals Sel provided to the multiplexers mux 1-mux K control how long (time duration) each selected input clock Ph<2N:1> is selected to be output from its respective multiplexer mux 1-mux k. Para. [0027]-[0030]) of the phases of the output clock (ph1-phk), independently, via outputs (independent control signals Sel 1-Sel k) to the ARO.
As for claim 2, Olariu teaches wherein the ARO controller (120) is further configured to: in a present cycle of the output clock (ph1-phk), effect a change to a high phase (e.g. phk) or a low phase (e.g. ph1) of the phases, or a combination thereof, in a next cycle of the output clock by updating a first output or a second output of the outputs, or a combination thereof, based on an indication of expected activity or inactivity of at least one other circuit expected in the next cycle (See feedback signal 130 from clock driven circuits 1-k).
As for claim 3, Olariu teaches wherein the circuit further includes an instruction decoder (702 in figure 7A) and wherein the instruction decoder is configured to identify instructions to be executed by at least one other circuit and wherein the indication represents whether the at least one other circuit will be executing at least one instruction in the next cycle (The input to decoder 702 comprises the selection signal SEL that is provided to all the multiplexers.).
Regarding claim 15, Olariu teaches wherein the output clock is used to clock at least one other circuit (See clock driven circuits 1-K) and wherein the at least one other circuit has a single clock domain.
Regarding claims 19 and 20, the methods as recited in the claims are inherently present in the structure discussed above in the rejection of claims 1 and 2.
Regarding claim 35, Olariu teaches an apparatus (figure 1) comprising:
means for generating (117/150) phases of an output clock (multi-phase output clock ph1-phk); and
means for controlling (120) durations (The selection signals Sel provided to the multiplexers mux 1-mux K control how long (time duration) each selected input clock Ph<2N:1> is selected to be output from its respective multiplexer mux 1-mux k. Para. [0027]-[0030]) of the phases, independently, via outputs (independent control signals Sel 1-Sel k) to said means for generating the phases.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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/LEVI GANNON/Primary Examiner, Art Unit 2849 March 9, 2026
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