DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 11-14 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US PGPUB 2022/0413699) in view of Oh et al. (US PGPUB 2019/0310774) and Srinivasan (US PGPUB 2019/0056989; hereinafter “Srin”).
With regard to Claim 1, Luo teaches a storage device comprising:
a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks (Fig. 2A: Superblocks 227. [0014] “A superblock, as used herein, can refer to a set of blocks that span multiple die that are written in an interleaved fashion. In some cases, a superblock may span all the die within an SSD. A superblock may contain multiple blocks from a single die.”); and
a memory controller configured to determine that a first super block, which is one of the first plurality of super blocks, comprises at least one initial bad block (Fig. 1: Memory Subsystem Controller 115. [0039] “the partial superblock memory management component 113 can include various circuitry to facilitate identifying a plurality of bad blocks in respective planes of a block of NAND memory cells.” [0040] “the memory sub-system controller 115 includes at least a portion of the partial superblock memory management component 113.” [0059] “At operation 332, a partial superblock memory management component (such as partial superblock memory management 113 in FIG. 1) can identify a respective quantity of bad blocks in a partial superblock”),
replace the at least one initial bad block with at least one reserved block ([0062] “At operation 336, an operation can be performed to reallocate a good block from a plane in another superblock of the plurality of superblocks to replace a bad block in the same plane of the partial superblock to form a number of partial superblocks each having quantify of bad blocks that is less than or equal to the bad block threshold.” [0055] “reallocating a good block from any partial superblock,” wherein the “partial superblock” which is the source of the “good block” being reallocated comprises the “reserved block”.).
With further regard to Claim 1, Luo does not teach the superblock classifier and bad block bitmap as described in claim 1. Oh teaches
update a bad block bitmap based on the at least one initial bad block ([0187] “referring to FIGS. 7 and 9 together, the controller 130 manages the good/bad states of the memory blocks grouped into the first super blocks... by a state bitmap G/B BITMAP.”), and
wherein the memory controller comprises a super block classifier configured to determine the first super block as a free block or a reserved block according to a number of the at least one initial bad block of the first super block based on the bad block bitmap ([0006] “the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks.” [0007] “The controller may manage remaining super blocks in each of which only good memory blocks are grouped, by classifying them as second super blocks, among the plurality of super blocks, the controller may manage first super blocks, each of which includes a number of bad memory which is equal to or less than a preset number, among the first super blocks, by classifying them as third super blocks, and the controller may manage first super blocks, each of which includes a number of bad memory blocks which exceeds the preset number, among the first super blocks, by classifying them as fourth super blocks,” wherein the “second super block” is a “free block” and the “fourth super block” is a “reserved block”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Luo with the superblock classifier and bad block bitmap as taught by Oh for purposes of “differently managing uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks,” (Oh [0016]) regarding the classifier, and so that “the controller 130 may quickly and accurately find good memory blocks” (Oh [0194]), regarding the bad block bitmap.
With further regard to Claim 1, Luo in view of Oh does not teach the free block list as described in claim 1. Srin teaches
based on the first super block being determined as the free block, insert the first super block into a free block list, wherein the free block list identifies a second plurality of super blocks ([0026] “An open superblock list (e.g., 122) may be associated with (e.g., formed as part of) the device controller 120 internal to the memory device system 104. Entries may, in a number embodiments, be stored, until removed (e.g., erased), in the open superblock list (e.g., as shown at 922 and described in connection with FIG. 9).”), and
the first plurality of super blocks comprises the second plurality of super blocks ([0017] “An ‘open superblock’ is intended to mean a partially written superblock, as described further herein,” wherein the super blocks entered in the “open superblock list,” i.e. the “second plurality of super blocks”, are necessarily a subset of all super blocks written and unwritten, i.e. the “first plurality of super blocks”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Luo in view of Oh with the free block list as taught by Srin in order to “provide benefits such as improving programming performance” (Srin [0027]).
With regard to Claim 2, Luo in view of Oh and Srin teaches all the limitations of Claim 1 as described above. Oh further teaches wherein the super block classifier is further configured to determine the first super block as the reserved block based on a number of initial bad blocks of the first super block being greater than N that is an integer greater than 0 ([0007] “the controller may manage first super blocks, each of which includes a number of bad memory blocks which exceeds the preset number, among the first super blocks, by classifying them as fourth super blocks,” wherein the “fourth super block” is a “reserved block”.).
With regard to Claim 3, Luo in view of Oh and Srin teaches all the limitations of Claim 1 as described above. Oh further teaches wherein the super block classifier is further configured to determine the first super block as the free block based on a number of initial bad blocks of the first super block being less than or equal to pre-set N that is an integer greater than 0 ([0007] “The controller may manage remaining super blocks in each of which only good memory blocks are grouped, by classifying them as second super blocks,” wherein the “second super block” is a “free block”.).
With regard to Claim 4, Luo in view of Oh and Srin teaches all the limitations of Claim 1 as described above. Oh further teaches wherein
the memory controller comprises a super block allocator configured to allocate the first super block for writing in response to a write command, and wherein the super block allocator is further configured to select the first super block from among the second plurality of super blocks identified in the free block list, determine whether the first super block is a normal super block based on the bad block bitmap, and, based on the first super block being the normal super block, allocate the first super block for the writing ([0018] “The method may further include: storing normal write data in the second super blocks.” [0026] “a memory device including... a second super block having only normal memory blocks; and ... the controller may control the memory device to program a first type of data into the first super block according to a first program scheme.” [0149] “Each of the remaining super memory blocks SUPER BLOCK<5:N−3, N−1, N> includes no bad memory block, and thus they are managed as normal super memory blocks.” [0164] “First, the controller 130 stores normal data, corresponding to a write command received from the host 102, in the second super blocks NORMAL SUPERBLOCK at step 1301.”).
With regard to Claims 11-14, these claims are equivalent in scope to Claims 1-4 rejected above, merely having a different independent claim type, and as such Claims 11-14 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1-4.
With regard to Claim 23, Luo teaches a storage device comprising:
a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks (Fig. 2A: Superblocks 227. [0014] “A superblock, as used herein, can refer to a set of blocks that span multiple die that are written in an interleaved fashion. In some cases, a superblock may span all the die within an SSD. A superblock may contain multiple blocks from a single die.”); and
a memory controller configured to determine whether a first super block, which is one of the first plurality of super blocks, comprises at least one initial bad block (Fig. 1: Memory Subsystem Controller 115. [0039] “the partial superblock memory management component 113 can include various circuitry to facilitate identifying a plurality of bad blocks in respective planes of a block of NAND memory cells.” [0040] “the memory sub-system controller 115 includes at least a portion of the partial superblock memory management component 113.” [0059] “At operation 332, a partial superblock memory management component (such as partial superblock memory management 113 in FIG. 1) can identify a respective quantity of bad blocks in a partial superblock”), and
replace the at least one initial bad block with at least one reserved block ([0062] “At operation 336, an operation can be performed to reallocate a good block from a plane in another superblock of the plurality of superblocks to replace a bad block in the same plane of the partial superblock to form a number of partial superblocks each having quantify of bad blocks that is less than or equal to the bad block threshold.” [0055] “reallocating a good block from any partial superblock,” wherein the “partial superblock” which is the source of the “good block” being reallocated comprises the “reserved block”.).
With further regard to Claim 23, Luo does not teach the superblock classifier as described in claim 23. Oh teaches wherein the memory controller comprises:
a super block classifier configured to determine the first super block as a free block based on a number of the at least one initial bad block of the first super block being less than or equal to pre-set K that is an integer greater than or equal to 1 ([0006] “the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks.” [0007] “The controller may manage remaining super blocks in each of which only good memory blocks are grouped, by classifying them as second super blocks, among the plurality of super blocks, the controller may manage first super blocks, each of which includes a number of bad memory which is equal to or less than a preset number, among the first super blocks, by classifying them as third super blocks, and the controller may manage first super blocks, each of which includes a number of bad memory blocks which exceeds the preset number, among the first super blocks, by classifying them as fourth super blocks,” wherein the “second super block” is a “free block”.), and
a super block allocator configured to allocate the first super block for writing in response to a write command ([0018] “The method may further include: storing normal write data in the second super blocks.” [0026] “a memory device including... a second super block having only normal memory blocks; and ... the controller may control the memory device to program a first type of data into the first super block according to a first program scheme.” [0149] “Each of the remaining super memory blocks SUPER BLOCK<5:N−3, N−1, N> includes no bad memory block, and thus they are managed as normal super memory blocks.” [0164] “First, the controller 130 stores normal data, corresponding to a write command received from the host 102, in the second super blocks NORMAL SUPERBLOCK at step 1301.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Luo with the superblock classifier and bad block bitmap as taught by Oh for purposes of “differently managing uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks,” (Oh [0016]) regarding the classifier, and so that “the controller 130 may quickly and accurately find good memory blocks” (Oh [0194]), regarding the bad block bitmap.
With further regard to Claim 23, Luo in view of Oh does not teach the free block list as described in claim 23. Srin teaches
insert the first super block into a free block list, wherein the free block list identifies a second plurality of super blocks ([0026] “An open superblock list (e.g., 122) may be associated with (e.g., formed as part of) the device controller 120 internal to the memory device system 104. Entries may, in a number embodiments, be stored, until removed (e.g., erased), in the open superblock list (e.g., as shown at 922 and described in connection with FIG. 9).”), and
the first plurality of super blocks comprises the second plurality of super blocks ([0017] “An ‘open superblock’ is intended to mean a partially written superblock, as described further herein,” wherein the super blocks entered in the “open superblock list,” i.e. the “second plurality of super blocks”, are necessarily a subset of all super blocks written and unwritten, i.e. the “first plurality of super blocks”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Luo in view of Oh with the free block list as taught by Srin in order to “provide benefits such as improving programming performance” (Srin [0027]).
With regard to Claim 24, Luo in view of Oh and Srin teaches all the limitations of Claim 23 as described above. Oh further teaches wherein the super block allocator is further configured to select a second super block, which is any one from among the second plurality of super blocks identified in the free block list, in response to a write command, determine whether at least one condition from among conditions for allocating the second super block is satisfied, and, based on the at least one condition being satisfied, allocate the second super block for the writing, and the conditions comprise a first condition that the second super block is a normal super block, a second condition that the write command is of a second type from between a first type and the second type, and a third condition that a number of super blocks identified in the free block list is less than M ([0018] “The method may further include: storing normal write data in the second super blocks.” [0026] “a memory device including... a second super block having only normal memory blocks; and ... the controller may control the memory device to program a first type of data into the first super block according to a first program scheme,” wherein the “first condition that the second super block is a normal super block” is satisfied. [0149] “Each of the remaining super memory blocks SUPER BLOCK<5:N−3, N−1, N> includes no bad memory block, and thus they are managed as normal super memory blocks.” [0164] “First, the controller 130 stores normal data, corresponding to a write command received from the host 102, in the second super blocks NORMAL SUPERBLOCK at step 1301.”).
Allowable Subject Matter
Claims 5-10, 15-17 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The above mentioned claims have been placed in condition for allowance due to the inclusion of a novel method and system for selecting which super blocks are be allocated for specific write commands. The prior art references teach various methods and systems for allocating and managing superblocks, but nowhere does any of the prior art disclose a method or system for allocating and managing superblocks which includes the specific set of steps disclosed in Applicant’s Claims 5, 8, 15 and 25, particularly with regard to the claim limitations which recite:
Claims 5 and 15: “select the first super block, which is a partial super block, from among the second plurality of super blocks identified in the free block list, and
allocate the first super block for writing based on the write command being of a second type from between a first type and the second type,
wherein the first type corresponds to a host command received from a host, and
wherein the second type corresponds to an internal command based on an internal operation of the memory controller.”
Claim 8: “select the first super block, which is a partial super block, from among the second plurality of super blocks identified in the free block list;
allocate the first super block for writing based on the write command being of a first type from between the first type and a second type and a number of free blocks identified in the free block list is less than M that is a positive integer; and
re-select one from among the second plurality of super blocks identified in the free block list for the writing based on the write command being of the first type and the number of free blocks identified in the free block list is greater than or equal to M,
wherein the first type corresponds to a host command received from a host.”
Claim 25: “wherein the super block allocator is further configured to select a third super block, which is any one of the second plurality of super blocks identified in the free block list, in response to the write command based on none of the conditions being satisfied.”
Claims 6-7, 9-10 and 16-17 have been indicated as reciting allowable subject matter since they depend from Claims 5, 8 and 15 respectively.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Horspool et al. (US PGPUB 2025/01110869) discloses a method for writing data to a solid-state drive (SSD) which comprises superblocks, as well as methods for optimizing garbage collection.
Jung et al. (“Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme,” 2010) discusses a superblock-based FTL scheme which combines a set of adjacent logical blocks into a superblock, as well as discussing a hybrid address translation scheme for NAND flash memory.
However, the above cited prior art does not teach a method or system for allocating and managing superblocks in the same manner as described by Applicant’s Independent Claims, particularly with regard to the limitations specifically pointed to above.
Conclusion
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 March 26, 2026
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