Prosecution Insights
Last updated: May 29, 2026
Application No. 19/020,753

WRITE PADDING DATA TO MEMORY DEVICE USING ON-DEVICE COPY

Non-Final OA §102
Filed
Jan 14, 2025
Priority
Jan 19, 2024 — provisional 63/623,022
Examiner
SIMONETTI, NICHOLAS J
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 9m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
357 granted / 464 resolved
+21.9% vs TC avg
Moderate +14% lift
Without
With
+13.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
18 currently pending
Career history
486
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
86.1%
+46.1% vs TC avg
§102
9.6%
-30.4% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 464 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation The Office notes that method Claim 20 has been found to recite the following contingent limitations: Claim 20: “performing the padding operation on the set of target blocks in response to determining that the padding operation is to be performed on the set of target blocks, the performing of the padding operation on the set of target blocks comprising performing an on-memory-device copy operation to copy at least a portion of padding data from a padding data source on the memory device to the set of target blocks.” As such, the Office has interpreted this claim language in accordance with MPEP 2111.04 (II), which recites, “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” The Office notes that the broadest reasonable interpretation of Claim 20 does not include performing the contingent “in response to” steps indicated above, since the claim does not recite the precedent conditions of “determining that the padding operation is to be performed on the set of target blocks.” The Office has examined Claim 20 in light of these contingent limitations. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raju et al. (US PGPUB 2023/0140773). With regard to Claim 20, Raju teaches a method comprising: determining whether to perform a padding operation on a set of target blocks of a plurality of blocks of a memory device ([0041] “the method 400 includes the processor 124 determining whether a valid count is higher than an SLC max valid count (at decision block 450). When the valid count is higher than the SLC max valid count (‘Yes’ at decision block 450), the method 400 includes the processor 124 padding the remainder of the QLC block and closes the QLC block (at block 455),” see Fig. 4, Steps 450 and 455.), each block of the plurality of blocks comprising a plurality of pages ([0039] “SLC block may hold max of 0x3000 (12,288) FMUs (each FMU is 4 k and indicates a valid count) and for QLC it is 0xC000 (49,152) FMUs (96 word lines*4 strings*32 KB page size).” [0042] “table 500 contains various operations necessary for performing basic NAND functions of the data storage device. For example, the table 500 includes... a QLC lower page, middle page, top page (LP/MP/TP) sense, a QLC upper page (UP) sense AP NR (AIPR (Asynchronous Independent Plane Read) Normal Read).”); and performing the padding operation on the set of target blocks in response to determining that the padding operation is to be performed on the set of target blocks, the performing of the padding operation on the set of target blocks comprising performing an on-memory-device copy operation to copy at least a portion of padding data from a padding data source on the memory device to the set of target blocks (Examiner’s Note: This step is not required given the broadest reasonable interpretation of the claim language, as the “performing” only occurs if it is determined “that the padding operation is to be performed”, as discussed above in the Claim Interpretation section.). Allowable Subject Matter Claims 1-19 are allowed. The following is an examiner’s statement of reasons for allowance: The above mentioned claims have been placed in condition for allowance due to the inclusion of a novel method and system for writing padding data using an on-device copy operation. The prior art references teach various methods and systems for performing a padding operation, but nowhere does any of the prior art disclose a method or system for performing a padding operation which includes the specific set of steps disclosed in Applicant’s Independent Claims 1, 16, particularly with regard to the limitations of exemplary Claim 1 which recites: “writing padding data to a padding data source on the memory device... the performing of the padding operation on the set of target blocks comprising performing an on-memory-device copy operation to copy at least a portion of the padding data from the padding data source on the memory device to the set of target blocks” (emphasis added). The fact that the independent claims of the instant application disclose novel subject matter not taught by the prior art, and not obvious in view of any combination of the prior art, has placed the aforementioned claims in condition for allowance. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows: Li et al. (US PGPUB 2025/0044979) discloses a data processing system and method, including storing padding data and performing padding operations. Bhardwaj et al. (US PGPUB 2024/0354003) discloses systems and methods for providing on-the-fly padding to feature maps of convolutional neural networks (CNNs). Avraham et al. (US PGPUB 2023/0409212) discloses a data storage device including a memory device and a controller, including padding data in flash memory units (FMU). Kim (US PGPUB 2008/0229000) discloses a memory system comprising a flash memory, including performing an on-memory-device copy-back operation to copy at least a portion of data from a data source on the memory device to a set of target blocks. However, the above cited prior art does not teach a method or system for performing a padding operation in the same manner as described by Applicant’s Independent Claims 1 and 16, particularly with regard to the limitations specifically pointed to above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J SIMONETTI whose telephone number is (571)270-7702. The examiner can normally be reached Monday-Thursday 10AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 April 21, 2026
Read full office action

Prosecution Timeline

Jan 14, 2025
Application Filed
May 05, 2026
Non-Final Rejection mailed — §102
May 11, 2026
Examiner Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+13.5%)
3y 1m (~1y 9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 464 resolved cases by this examiner. Grant probability derived from career allowance rate.

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