DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 11-12 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 3 and analogous claims 11 and 18:
Claim 3 recites, “the respective set of commands assigned to a third queue”. However, the claims never previously recite assigning a respective set of commands to a third queue. Instead, the claims only ever recite assigning respective sets of commands to the first and second queue in claim 1. Accordingly, the limitation lacks antecedent basis and the scope of the claim cannot be determined and the claim is indefinite.
Regarding claims 4, 12 and 19:
Claims 4, 12 and 19 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5 and analogous claims 13 and 20:
Claim 5 recites, “pause, after issuing the one or more commands, commands assigned to the third queue”. However, the specification never discloses pausing commands assigned to the third (lowest-priority) queue after issuing one or more commands from the third (lowest-priority) queue due to a threshold number of commands being issued from the first (highest-priority) queue without any commands being issued from the lowest priority queue. Instead, the specification only ever discloses pausing issuance of commands from the third (lowest-priority) queue based on the higher priority queues having commands assigned to them after previously being empty [0014] [0051] [0053] [0056]. However, claim 5 does not reflect the condition of the highest-priority queue being empty such that commands are issued from the lowest-priority queue, and then having commands again assigned to the highest-priority queue such that issuance of commands from the lower priority queue is paused because there are higher priority commands pending. Accordingly, the limitation is regarded as new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-10, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2021/0279001 A1 (Kanno) in view of US Patent Application Publication No. US 2002/0138670 A1 (Johnson).
Regarding claim 1 and analogous claims 9 and 16:
Kanno discloses, a memory system (SSD (3) [Fig. 1]), comprising: one or more memory devices (NAND flash memory (5), including a plurality of memory die (i.e., 1-32) [Figs. 1-2]); and a processing device (CPU (12)) coupled with the one or more memory devices (CPU (12) is coupled to NAND flash memory (5) including the plurality of die (i.e., 1-32) through the NAND I/F (13), it controls the operation of the memory by loading and executing a control program stored in the flash memory (5) or a ROM, loaded to SRAM (16), and may implement the scheduler (21) [0061]) and configured to cause the memory system to: assign respective sets of commands to a first queue or a second queue of a memory device of the one or more memory devices (by disclosing the controller (4) inputting commands to different queues (i.e., any of queues 0-7) for a NAND flash memory die according to a classification method, for example, different namespaces may be associated with each queue, and [Fig. 4] [0091] [0102]) wherein the first queue and the second queue are associated with a first priority and a second priority, respectively, the first priority greater than the second priority (by disclosing that the queues can function according to 8-level priority queueing, where all commands are issued from the highest priority queue until it is empty and then commands are issued from the next lowest priority command and so on and so forth. The priority order can be based on the queue number, such that queues with lower numbers are higher priority (i.e., queue #0 has higher priority than queue #1, queue #1 has higher priority than queue #2, and so on and so forth) [0115] [0168-0170]) and issue one or more commands of a respective set of commands assigned to the second queue based at least in part on issuance of a number of commands from the first queue without issuance of commands from the second queue (by disclosing that all commands would issue from the highest priority queue (queue #0), until it is empty (i.e., a number of commands from the first queue would issue without issuance of commands from the second queue), before any commands are issued from the next highest priority queue (queue #1) [0115]) [0169-0170]).
Kanno does not explicitly disclose, but Johnson teaches, and issue one or more commands of a respective set of commands assigned to the second queue based at least in part on issuance of a threshold number of commands from the first queue without issuance of commands from the second queue (by teaching that a starvation counter may provide a count of the number of high/priority requests that are issued while deferred low priority I/O requests are pending in the low priority I/O queue [0020]. In this way, if the starvation counter reaches a predetermined maximum value (i.e., threshold), a predetermined number of requests can be processed from the low priority I/O queue to prevent starvation of the low priority I/O requests, and then the starvation counter can be reset [0020] [0025]. As seen in [Fig. 4], the starvation counter only counts the number of high-priority requests that have issued without a command issuing form the lower-priority queue, as any time a low-priority request is issued the starvation counter is reset (160) (168) [Fig. 4] [0020-0026]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the priority queues that issue commands from the highest priority queue (i.e., queue #0) until it is empty before issuing commands from the next highest priority queue (i.e., queue #1) as taught by Kanno to include a starvation counter that counts the number of highest priority commands that have issued (i.e., such as from queue #0 as taught by Kanno) without issuing a deferred lower priority commands queue in a lower priority queue (i.e., such as queue #1 as taught by Kanno), and then if that count reaches a threshold, issuing a predetermined number of commands from the lower priority queue (i.e., such as queue #1 as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification because it can prevent starvation of the lower priority I/O requests if there is a stream of numerous high priority I/O requests as taught by Johnson in [0020].
Regarding claim 2 and analogous claims 10 and 17:
The memory system of claim 1 is made obvious by Kanno in view of Johnson (Kanno-Johnson).
Kanno-Johnson further make obvious, wherein the processing device is further configured to cause the memory system to: issue, prior to issuing the one or more commands of the respective set of commands assigned to the second queue one or more commands of a respective set of commands assigned to the first queue (through the analysis performed for claim 1).
Regarding claim 5 and analogous claims 13 and 20:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno does not explicitly disclose, but Johnson teaches wherein, the processing device is further configured to cause the memory system to: pause, after issuing the one or more commands, commands assigned to the second queue (by disclosing that only a predetermined number of commands (168) will be issued from the deferred low priority I/O requests in the low priority queue, and then commands will resume being issued from the high priority queue after the starvation counter is reset (i.e., the high priority commands will again issue without low priority commands issuing (i.e., pausing commands assigned to the second queue)) [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance of commands from the priority queues that issue commands from the highest priority queue (i.e., queue #0) until it is empty before issuing commands from the next highest priority queue (i.e., queue #1) as taught by Kanno to include a starvation counter that counts the number of highest priority commands that have issued (i.e., such as from queue #0 as taught by Kanno) without issuing a deferred lower priority commands queue in a lower priority queue (i.e., such as queue #1 as taught by Kanno), and then if that count reaches a threshold, issuing a predetermined number of commands from the lower priority queue (i.e., such as queue #1 as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification because it can prevent starvation of the lower priority I/O requests if there is a stream of numerous high priority I/O requests as taught by Johnson in [0020].
Regarding claim 6:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno-Johnson further make obvious, wherein the memory system further comprises: a counter configured to track a quantity of commands issued from the first queue, or the second queue (through the analysis performed for claim 1).
Regarding claim 7 and analogous claim 14:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses, wherein the memory device is associated with a respective sub-system of the memory system (by teaching that the NAND flash memory die (as seen in [Fig. 4]) associated with the plurality of queues (queues #1-#7) may be one of a plurality of memory dies in the memory system, as seen in [Figs. 1-3], which each have their own associated queues and scheduler (a respective sub-system) as seen in [Fig. 4] [0043] [0089-0091]).
Regarding claim 8 and analogous claim 15:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses, wherein a command included in a respective set of commands assigned to the first queue is a host read command (by disclosing that each of the commands (erase, program, and read) can be placed in a certain queue of the eight queues for the memory die. The command, for example, may be a read command from the host (host read command) that is placed in queue #0 (first queue) [0091-0094]).
Claims 3-4, 11-12 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno-Johnson in further view of US Patent Application Publication No. US 2018/0217951 A1 (Benisty) as motivated by the paper by Mustafa El Gili Mustafa, et. al., titled “The Effect of Queueing Mechanisms First in First out (FIFO), Priority Queuing (PQ) and Weighted Fair Queuing (WFQ) on Network’s Routers and Applications” published 31 May 2016 by Scientific Research Publishing in the Wireless Sensor Network Journal, Vol. 8, No. 5 (Mustafa).
Regarding claim 3 and analogous claims 11 and 18:
The memory system of claim 1 is made obvious by Kanno-Johnson.
Kanno further discloses the respective set of commands assigned to a third queue of the memory device (by disclosing the controller (4) inputting commands to different queues (i.e., any of queues 0-7) for a NAND flash memory die according to a classification method, for example, different namespaces may be associated with each queue, and [Fig. 4] [0091] [0102]. The queues can function according to 8-level priority queueing, where all commands are issued from the highest priority queue until it is empty and then commands are issued from the next lowest priority command and so on and so forth. The priority order can be based on the queue number, such that queues with lower numbers are higher priority (i.e., queue #0 has higher priority than queue #1, queue #1 has higher priority than queue #2, and so on and so forth) [0115] [0168-0170]).
Kanno does not explicitly disclose, but Benisty teaches, wherein the processing device is further configured to cause the memory system to: assign a command to the first queue or the second queue; and pause issuance of one or more second commands of the respective set of commands assigned to a third queue of the memory device based at least in part on assigning the command to the first queue or the second queue (by teaching that selection of commands for issuance from the low priority queues may only continue while the high and medium priority queues are empty – otherwise, selection of commands for issuance would switch to the higher priority queues (i.e., and therefore pause issuance of commands from the low priority queues) [0105]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue, such as queue #2, as taught by Kanno, to be interrupted so that a command from a higher priority queue may be issued and executed if the higher priority queues are no longer empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because priority queuing (where commands are queued from lower priority queues only if all the higher priority queues are empty) is relatively simple and places a low computational load on the system as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79]. Furthermore, it ensures that important commands get the fastest handling, and that strict priority can be given to important commands as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79].
Regarding claim 4 and analogous claims 12 and 19:
The memory system of claim 3 is made obvious by Kanno-Johnson in further view of Benisty in further view of Mustafa.
Kanno does not explicitly disclose, but Benisty teaches, wherein the processing device is further configured to cause the memory system to: issue the command assigned to the first queue or the second queue; and resume issuance of the one or more second commands of the respective set of commands assigned to the third queue based at least in part on issuing the command assigned to the first queue or the second queue (by teaching that selection of commands for issuance from the low priority queues may only continue while the high and medium priority queues are empty – otherwise, selection of commands for issuance would switch to the higher priority queues (i.e., and therefore pause issuance of commands from the low priority queues), however, upon the higher priority queues being empty again, commands would resume being issued from the low priority queues again [0105]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue, such as queue #2, as taught by Kanno, to be interrupted so that a command from a higher priority queue may be issued and executed if the higher priority queues are no longer empty as taught by Benisty, but then to resume issuance and execution of commands from the low priority queue again (such as queue #2 as taught by Kanno) if the higher priority queues are again empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because priority queuing (where commands are queued from lower priority queues only if all the higher priority queues are empty) is relatively simple and places a low computational load on the system as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79]. Furthermore, it ensures that important commands get the fastest handling, and that strict priority can be given to important commands as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79].
In Response to Amendments/Arguments
In response to the amendments to the claims, the previous 35 USC §112(b) rejection has been withdrawn. However, in response to the amendments to the claims, a new 35 USC §112(b) rejection has been made to claims 3-4, 11-12 and 18-19 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the previous 35 USC §112(a) rejection has been withdrawn. However, in response to the amendments to the claims, a new 35 USC §112(a) rejection has been made as seen in the corresponding rejection section above.
Applicant argues that Johnson does not teach tracking “issuance of a threshold number of commands from the first queue without issuance of commands from the second queue” because “Johnson’s starvation counter is incremented only upon receiving a completion message from the device driver indicating a high-priority I/O request was transmitted”. However, the Examiner finds that the broadest reasonable interpretation of issuing a request includes transmitting a request (in line with Applicant’s specification that discloses issuing a request as sending (i.e., transmitting) it to a memory controller [0049]). Furthermore, Johnson was not relied upon alone to make obvious the claimed invention. Accordingly, Applicant’s argument against the references individually is not persuasive where Kanno was relied upon to teach the high-priority I/O queue and the issuance of commands from the high-priority queue. Therefore, when read together, the starvation counter of Johnson can reasonably be applied to the teachings of Kanno to track the number of commands that are issued/transmitted from the high-priority queue taught by Kanno. Accordingly, Applicant’s argument is not persuasive.
Applicant further argues that Johnson’s starvation counter fails to “condition[] issuance from a lower-priority queue on the absence of issuance from that lower-priority queue during the counting period”. The Examiner respectfully disagrees. Johnson’s starvation counter explicitly counts high-priority commands being transmitted (i.e., issued) while low-priority commands are pending (i.e., not being issued). Any time that a high priority command is transmitted (150, and 154 – Yes) while there are pending low-priority commands (164 – Yes), the starvation counter is incremented (172). Then, any time that the low-priority commands are issued due to the starvation counter reaching a maximum (166 -Yes) or the number of pending/queue high-priority commands being 0 (158 – Yes), such that a low-priority command could finally issue (162), the starvation counter is reset (160) or (168). Accordingly, any time a low-priority command is issued, the starvation counter is reset, and therefore, the starvation counter only counts the number of high-priority commands that are issued without issuance of commands from the second queue as claimed. Therefore, Kanno in view of Johnson renders obvious the claimed invention according to the analysis performed above and in the corresponding claim rejection section and Applicant’s argument is not persuasive.
The rest of Applicant’s arguments depend from those above, which were not persuasive. Accordingly, the pending claims are still rejected with prior art under 35 USC §103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NVM Express, Revision 1.1a, dated 23 September 2023 (NVM) – teaches that there can be three strict priority classes associated with submission queues. The three classes are a highest priority class (admin), the middle priority class (urgent), and the lowest priority class (weighted round robin, within which there is high, medium, and low priorities). In this way, commands are always issued from the highest priority class queue if they are present, are issued from the medium priority class queue if none of the highest priority class queue commands are present, and then finally, are issued from the weighted round robin (lowest) class queue if there are no high or medium priority queue requests present [pgs. 61-62] [Fig. 37].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CURTIS JAMES KORTMAN whose telephone number is (303)297-4404. The examiner can normally be reached Monday through Friday 7:30 AM through 4:00 PM MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
Prosecution Insights