DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 5, 13 and 20:
The term “some” in claims 5, 13 and 20 is a relative term which renders the claim indefinite. The term “some” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For example, the definition of “some” includes an unspecified number, unit, or amount of something. Accordingly, the amount of commands that are required to issue so that “some” of the respective set of commands have been issued is not clear in the claims. The Examiner suggests amending the claim to recite “issue at least one command, but not all commands, of the respective set of commands” instead of “issue some, but not all of the respective set of commands”. For the purposes of applying prior art, the Examiner will interpret “issue some” as meaning “issue at least one command”.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 5, 13 and 20:
Claims 5, 13 and 20 recite “issuing some, but not all of the respective set of commands assigned to the third queue”. However, the limitation is regarded as new matter.
For discussion purposes, the “third queue” in the claims corresponds to a lowest priority queue for a die in the claims, which is a queue ending in “-b” in the specification.
The specification describes issuing commands from the lowest-priority queue when higher-priority queues are empty and pausing issuance from the lowest-priority queue when a command enters a high-priority queue. For example, the specification states that “the commands in the priority queue 310-b can be issued (e.g., individually; one by one) until a command is entered into either of the priority queue 310 or the priority queue 310-a,” after which any commands in the lowest priority queue may be paused until the commands in the higher-priority queues are issued and they are again empty [0051].
Therefore, [0051] describes issuing commands from the lowest-priority queue sequentially unless and until a higher-priority command is present rather than describing issuing only some, but not all commands in the lowest-priority queue. As the federal circuit explained, “[i]nherency, however, may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient.” In re Robertson, 169 F.3d 743, 745, 49 USPQ2d 1949, 1950-51 (Fed. Cir. 1999). Any scenario in which fewer than all commands from the lowest-priority queue are issued would occur incidentally, due to possible preemption by higher-priority commands while a number of lowest-priority commands remain pending, rather than as a step actually disclosed in the specification of preventing all commands in the lowest-priority queue from issuing. For example, there is no disclosure of stopping issuance of commands from the lowest-priority queue to prevent it from becoming empty or a mechanism for ensuring that it does not become empty (i.e., not issuing “all” of the commands from the lowest priority queue). Accordingly, disclosing the conditions in which the claimed limitation is possible but not required does not satisfy the written description requirement under 35 USC §112(a).
Additionally, although the specification further describes allowing a command from a lower-priority queue to issue after a threshold number of higher-priority commands have issued in order to prevent it from becoming stale [0061-0064], this only describes allowing a command from the lowest-priority queue to issue rather than describing issuing some, but not all, of the respective set of commands assigned to the lowest priority queue. Accordingly, the specification does not reasonably convey to one of ordinary skill in the art that the inventors had possession of a process in which some, but not all, of the commands assigned to the lowest-priority queue are allowed to issue, as required by the claims. Therefore, the limitation is regarded as new matter.
[The Examiner notes that the disclosed threshold of higher-priority commands that may be issued while a lower-priority command is pending in the queue before switching to issuing a lower-priority command appears to instead provide written description support of “issuing some, but not all, of the commands of the respective set of commands assigned to the first queue or the second queue” rather than the third queue as claimed].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2021/0279001 A1 (Kanno) in further view of US Patent Application Publication No. US 2018/0217951 A1 (Benisty) as motivated by the paper by Mustafa El Gili Mustafa, et. al., titled “The Effect of Queueing Mechanisms First in First out (FIFO), Priority Queuing (PQ) and Weighted Fair Queuing (WFQ) on Network’s Routers and Applications” published 31 May 2016 by Scientific Research Publishing in the Wireless Sensor Network Journal, Vol. 8, No. 5 (Mustafa).
Regarding claim 1 and analogous claims 9 and 16:
Kanno discloses, a memory system (SSD (3) [Fig. 1]), comprising: one or more memory devices (NAND flash memory (5), including a plurality of memory die (i.e., 1-32) [Figs. 1-2]); and a processing device (CPU (12)) coupled with the one or more memory devices (CPU (12) is coupled to NAND flash memory (5) including the plurality of die (i.e., 1-32) through the NAND I/F (13), it controls the operation of the memory by loading and executing a control program stored in the flash memory (5) or a ROM, loaded to SRAM (16), and may implement the scheduler (21) [0061]) and configured to cause the memory system to: assign respective sets of commands to a first queue, a second queue, or a third queue of a memory device of the one or more memory devices (by disclosing the controller (4) inputting commands to different queues (i.e., any of queues 0-7) for a NAND flash memory die according to a classification method, for example, different namespaces may be associated with each queue, and [Fig. 4] [0091] [0102]) wherein the first queue, the second queue, and the third queue are associated with a first priority, a second priority, and a third priority, respectively, the first priority greater than the second priority and the second priority greater than the third priority (by disclosing that when the queues have the same second weights, the queue with the smaller queue identifier may be selected by the scheduler (21) as the queue with the higher priority, such that queues with the higher priorities are relatively assigned to queues with smaller queue identifiers (i.e., queue 0 has a higher priority than queue 1, which is higher priority than queue 2, and so on and so forth, when they all have the same second weight) [0115]) and issue one or more commands of a respective set of commands assigned to the third queue based at least in part on one or both of the first queue or the second queue having their commands executed first (by disclosing that the queues can all have their first weights set to 0, such that the second weights are not varied and are maintained at the initial values throughout execution (i.e., the second weights would all be equal throughout operation, such that the queue identifiers would control priority (smaller queue identifier = higher priority, relatively)) [0115]) [0169-0170]).
Kanno does not explicitly disclose, but Benisty teaches and issue one or more commands of a respective set of commands assigned to the third queue based at least in part on one or both of the first queue or the second queue being empty (by teaching a strict priority arbitration scheme, where commands from a highest priority queue are selected before commands from lower priority queues. In this way, commands with the highest priority may be issued unless the highest priority queues are empty. Then, the commands from the medium priority queue may be issued so long as the highest priority queue remains empty. Finally, commands from the lower priority queue may be issued so long as the highest and medium priority queues are empty (based on at least in part on one or both of the first queue or the second queue being empty) [0105]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the 8-level priority arbitration policy between queues as taught by Kanno to be a strict priority arbitration scheme where commands from higher priority queues are always selected to issue first, while command from lower priority queues will only be selected for execution if the commands from the higher priority queues are empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because priority queuing (where commands are queued from lower priority queues only if all the higher priority queues are empty) is relatively simple and places a low computational load on the system as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79]. Furthermore, it ensures that important commands get the fastest handling, and that strict priority can be given to important commands as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79].
Regarding claim 2 and analogous claims 10 and 17:
The memory system of claim 1 is made obvious by Kanno in view of Benisty as motivated by Mustafa (Kanno-Benisty-Mustafa).
Kanno further discloses, wherein the processing device is further configured to cause the memory system to: issue, prior to issuing the one or more commands of the respective set of commands assigned to the third queue, one or more commands of a respective set of commands assigned to the second queue or one or more commands of a respective set of commands assigned to the first queue (by teaching that after the commands in queue #0 are executed (first queue), then the commands in queue #1 may be executed (second queue), and then the commands in queue #2 may be executed (third queue – i.e., the commands in the first and second queues are executed before the commands in the third queue) [0170]).
Regarding claim 3 and analogous claims 11 and 18:
The memory system of claim 1 is made obvious by Kanno in view of Benisty in further view of Mustafa (Kanno-Benisty-Mustafa).
Kanno does not explicitly disclose, but Benisty teaches, wherein the processing device is further configured to cause the memory system to: assign a command to the first queue or the second queue; and pause issuance of one or more second commands of the respective set of commands assigned to the third queue based at least in part on assigning the command to the first queue or the second queue (by teaching that selection of commands for issuance from the low priority queues may only continue while the high and medium priority queues are empty – otherwise, selection of commands for issuance would switch to the higher priority queues (i.e., and therefore pause issuance of commands from the low priority queues) [0105]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue, such as queue #2, as taught by Kanno, to be interrupted so that a command from a higher priority queue may be issued and executed if the higher priority queues are no longer empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because priority queuing (where commands are queued from lower priority queues only if all the higher priority queues are empty) is relatively simple and places a low computational load on the system as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79]. Furthermore, it ensures that important commands get the fastest handling, and that strict priority can be given to important commands as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79].
Regarding claim 4 and analogous claims 12 and 19:
The memory system of claim 3 is made obvious by Kanno-Benisty-Mustafa.
Kanno does not explicitly disclose, but Benisty teaches, wherein the processing device is further configured to cause the memory system to: issue the command assigned to the first queue or the second queue; and resume issuance of the one or more second commands of the respective set of commands assigned to the third queue based at least issuing the command assigned to the first queue or the second queue (by teaching that selection of commands for issuance from the low priority queues may only continue while the high and medium priority queues are empty – otherwise, selection of commands for issuance would switch to the higher priority queues (i.e., and therefore pause issuance of commands from the low priority queues), however, upon the higher priority queues being empty again, commands would resume being issued from the low priority queues again [0105]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the issuance and execution of commands from a lower priority queue, such as queue #2, as taught by Kanno, to be interrupted so that a command from a higher priority queue may be issued and executed if the higher priority queues are no longer empty as taught by Benisty, but then to resume issuance and execution of commands from the low priority queue again (such as queue #2 as taught by Kanno) if the higher priority queues are again empty as taught by Benisty.
One of ordinary skill in the art would have been motivated to make this modification because priority queuing (where commands are queued from lower priority queues only if all the higher priority queues are empty) is relatively simple and places a low computational load on the system as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79]. Furthermore, it ensures that important commands get the fastest handling, and that strict priority can be given to important commands as taught by Mustafa in [pg. 78, last ¶ - continued onto pg. 79].
Regarding claim 7 and analogous claim 14:
The memory system of claim 1 is made obvious by Kanno-Benisty-Mustafa.
Kanno further discloses, wherein the memory device is associated with a respective sub-system of the memory system (by teaching that the NAND flash memory die (as seen in [Fig. 4]) associated with the plurality of queues (queues #1-#7) may be one of a plurality of memory dies in the memory system, as seen in [Figs. 1-3], which each have their own associated queues and scheduler (a respective sub-system) as seen in [Fig. 4] [0043] [0089-0091]).
Regarding claim 8 and analogous claim 15:
The memory system of claim 1 is made obvious by Kanno-Benisty-Mustafa.
Kanno further discloses, wherein a command included in a respective set of commands assigned to the first queue is a host read command (by disclosing that each of the commands (erase, program, and read) can be placed in a certain queue of the eight queues for the memory die. The command, for example, may be a read command from the host (host read command) that is placed in queue #0 (first queue) [0091-0094]).
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno-Benisty-Mustafa in further view of US Patent Application Publication No. US 2013/0219088 A1 (Rawe).
Regarding claim 5 and analogous claims 13 and 20:
The memory system of claim 1 is made obvious by Kanno-Benisty-Mustafa.
Kanno does not explicitly disclose, but Rawe teaches wherein, to issue the one or more commands of the respective set of commands assigned to the third queue, the processing device is configured to cause the memory system to: issue some, but not all, of the respective set of commands assigned to the third queue (by disclosing that a higher priority queue may have its “high priority” designation removed if it has executed too many commands in a row or if it has executed commands for an elapsed time that reaches a threshold value. In this case, the queue may have its “high priority” designation removed so that commands from a lower-priority queue may be executed [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified queue #2 as taught by Kanno-Benisty-Mustafa to include a threshold value that may cause it’s higher priority status to be revoked (compared to lower priority queues such as #3-#7) if it has executed too many commands in a row, or has been executing commands for a threshold elapsed time as taught by Rawe.
One of ordinary skill in the art would have been motivated to make this modification because it prevents a higher priority queue from starving other lower priority queues as taught by Rawe in [0025].
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kanno-Benisty-Mustafa in further view of US Patent Application Publication No. US 2002/0138670 A1 (Johnson).
Regarding claim 6:
The memory system of claim 1 is made obvious by Kanno-Benisty-Mustafa.
Kanno does not explicitly disclose, but Johnson teaches, wherein the memory system further comprises: a counter configured to track a quantity of commands issued from the first queue, the second queue, or the third queue (by teaching that a starvation counter (28) may count a number of high priority I/O requests (i.e. a counter to track a quantity of commands that are issued from at least the first queue) that are issued while low priority I/O requests are pending in a low priority I/O queue (24). If the starvation counter (28) reaches a predetermined maximum value, then requests are processed from the low priority I/O queue to prevent starvation of the low priority I/O requests in the event there is a stream of numerous high priority I/O requests [0020] [0025-0026]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a starvation counter to count issued high priority commands (i.e., such as commands from one or more of the higher priority queues as taught by Kanno) while commands are pending in a low priority queue (i.e., one or more of the lower priority queues as taught by Kanno) so that if the counter reaches a threshold, commands may be issued from the low priority queue (i.e., one or more of the lower priority queues as taught by Kanno) as taught by Johnson.
One of ordinary skill in the art would have been motivated to make this modification because it would prevent starvation of the low priority I/O requests as taught by Johnson in [Johnson, 0020], which is a problem otherwise associated with priority queuing as taught by Mustafa in [Mustafa, pg. 78, last ¶ - continued onto pg. 79].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NVM Express, Revision 1.1a, dated 23 September 2023 (NVM) – teaches that there can be three strict priority classes associated with submission queues. The three classes are a highest priority class (admin), the middle priority class (urgent), and the lowest priority class (weighted round robin, within which there is high, medium, and low priorities). In this way, commands are always issued from the highest priority class queue if they are present, are issued from the medium priority class queue if none of the highest priority class queue commands are present, and then finally, are issued from the weighted round robin (lowest) class queue if there are no high or medium priority queue requests present [pgs. 61-62] [Fig. 37].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CURTIS JAMES KORTMAN whose telephone number is (303)297-4404. The examiner can normally be reached Monday through Friday 7:30 AM through 4:00 PM MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139