DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-9, 11-13, 18-23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (US PGPUB 2020/0151108).
With regard to Claim 1, Yen teaches a memory system, comprising:
one or more memory devices (Fig. 1: RAM 112, ROM 113 and Memory Storage Device 10. See also Fig. 6, wherein [0051] “The memory interface 706 is coupled to the memory management circuit 702 and accesses the rewritable non-volatile memory module 406.”); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (Fig. 6: Memory Management Circuit 702, wherein [0047] “the memory management circuit 702 has a microprocessor unit... When the memory storage device 10 is operated, the control commands are executed by the microprocessor unit to perform writing, reading and erasing operations on data.”):
update, in volatile memory of the memory system, a plurality of logical-to-physical (L2P) address mappings, each of the plurality of L2P address mappings corresponding to a respective L2P table in non-volatile memory of the memory system ([0054] “The buffer memory 710 is coupled to the memory management circuit 702 and used to temporarily store data and command from the host system 11 or data from the rewritable non-volatile memory module 406,” wherein the “buffer memory” temporarily stores data and as such is the “volatile memory of the memory system.” [0070] “when the host system 11 performs a write operation, the MMC 702 records the mapping information of the updated data corresponding to the write operation into the P2L table 600 as shown in FIG. 9B in the buffer memory 710.” [0071] “After the P2L table 600 is full...,” wherein the “P2L” table becomes full by updating “a plurality of logical-to-physical (L2P) address mappings,” i.e. the physical-logical mappings in Yen.);
determine whether to update the respective L2P tables in the non-volatile memory based at least in part on a quantity of the respective L2P tables of the updated plurality of L2P address mappings satisfying a first threshold or a quantity of updated L2P address mappings of the plurality of updated L2P address mappings satisfying a second threshold ([0007] “when... the physical-logical mapping table is full,” wherein the “first threshold” is the “full” amount. [0064] “the MMC 702 stores a L2P table in the RNVM module 406.” [0065] “the space required to store all of the L2P tables may vary depending on the capacity of the RNVM module 406.”); and
update the respective L2P tables in the non-volatile memory with the updated plurality of L2P address mappings in the volatile memory based at least in part on the determination ([0007] “when... the physical-logical mapping table is full, the memory management circuit loads the corresponding logical-physical mapping table according to the mapping information in the physical-logical mapping table to update the mapping information between the logical page and the physical programming unit.” [0071] “After the P2L table 600 is full, the corresponding L2P table is loaded into the buffer memory 710 according to the mapping information (i.e., the logical address corresponding to the updated data) in the P2L table 600, thereby updating the mapping relationship between the logical units LBA(0) to LBA(3) and the PEUs 410(0) to 410(5).” [0107] “in step S1207, the MMC 702 loads the first L2P table corresponding to the first updated logical unit from the plurality of L2P tables. In step S1209, the MMC 702 updates the mapping information in the first L2P table according to the mapping information of the first updated logical unit in the P2L table 600. Finally, in step S1211, the MMC 702 stores the updated first L2P table back to the RNVM module.”).
With regard to Claim 2, Yen teaches the memory system of claim 1, wherein, to determine whether to update the respective L2P tables, the processing circuitry is configured to cause the memory system to:
determine to update the respective L2P tables in the non-volatile memory based at least in part on the quantity of respective L2P tables of the updated L2P address mappings satisfying the first threshold ([0007] “when... the physical-logical mapping table is full,” wherein the “first threshold” is the “full” amount. [0064] “the MMC 702 stores a L2P table in the RNVM module 406.” [0065] “the space required to store all of the L2P tables may vary depending on the capacity of the RNVM module 406.”).
With regard to Claim 3, Yen teaches the memory system of claim 2, wherein, to determine to update the respective L2P tables, the processing circuitry is configured to cause the memory system to:
determine to update the respective L2P tables in the non-volatile memory before the quantity of updated L2P address mappings of the plurality of updated L2P address mappings satisfies the second threshold ([0092] “In the second embodiment of the present disclosure, the MMC 702 may, for example, set a threshold (also referred to as a second threshold) in advance. When the updated data count corresponding to a logical unit is less than the second threshold, the MMC 702 loads the L2P table of the logical unit into the buffer memory 710, and updates the L2P table of the logical unit according to the information in the P2L table 600.”).
With regard to Claim 8, Yen teaches the memory system of claim 1, wherein each L2P table corresponds to a respective region of memory cells of the one or more memory devices ([0065] “the MMC 702 groups the logical units LBA(0)˜LBA(H) into a plurality of logical regions LZ(0)˜LZ(M), and assigns one L2P table for each of the logical regions. Specifically, when the MMC 702 is to update the mapping of a certain logical unit, the L2P table corresponding to the logical region to which the logical unit belongs is loaded into the buffer memory 710 to be updated.”).
With regard to Claim 9, Yen teaches the memory system of claim 1, wherein the processing circuitry is configured to cause the memory system to:
update the plurality of L2P address mappings based at least in part on one or more write operations responsive to one or more write commands received at the memory system ([0070] “when the host system 11 performs a write operation, the MMC 702 records the mapping information of the updated data corresponding to the write operation into the P2L table 600 as shown in FIG. 9B in the buffer memory 710.”).
With regard to Claims 11-13 and 18-19, these claims are equivalent in scope to Claims 1-3 and 8-9 rejected above, merely having a different independent claim type, and as such Claims 11-13 and 18-19 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1-3 and 8-9.
With further regard to Claim 11, the claim recites additional elements not specifically addressed in the rejection of Claim 1. The Yen reference also anticipates these additional elements of Claim 11, for example, Yen teaches:
A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to perform operations (Fig. 6: Memory Management Circuit 702, wherein [0047] “the memory management circuit 702 has a microprocessor unit... When the memory storage device 10 is operated, the control commands are executed by the microprocessor unit to perform writing, reading and erasing operations on data.” [0048] “the read only memory has a boot code, and when the memory controlling circuit unit 404 is enabled, the microprocessor unit executes the boot code first to load the control command stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 702. Thereafter, the microprocessor unit runs the control commands to perform writing, reading and erasing operations on data,” wherein “read only memory” is a type of “non-transitory computer-readable medium.”).
With regard to Claims 21-23 and 25, these claims are equivalent in scope to Claims 1-3 and 8 rejected above, merely having a different independent claim type, and as such Claims 21-23 and 25 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1-3 and 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 10, 14-16, 20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yen as applied to Claims 1, 11 and 21 above, and further in view of Akavaram et al. (US PGPUB 2024/0370378).
With regard to claim 4, Yen teaches all the limitations of claim 1 as described above. Yen does not teach the update indication as described in claim 4. Akavaram teaches wherein the processing circuitry is further configured to cause the memory system to:
store an indication of the quantity of respective L2P tables; and determine whether to update the respective L2P tables based at least in part on the stored indication ([0008] “setting, by the memory controller, a bit in a second memory of the memory module indicating the update to the first L2P table, and transmitting, to a host device coupled to the memory controller through a first interface, an indication of the update to the first L2P table after setting the bit.” [0064] “when the L2P table 414 of the memory system 404 is updated, the memory system 404 may set a bit in a register of the memory system 404, such as a bit in SRAM of the memory system also storing the L2P table 414 or another memory of the memory system 404. Setting the bit may trigger transmission of an interrupt to the host device 402. When the host device 402 receives the interrupt, the host device 402 may request information indicating the updates to the L2P table 414 of the memory system 404.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Yen with the update indication as taught by Akavaram in order “to maintain synchronization between the L2P table 408 of the host device 402 and the L2P table 414 of the memory system 404” (Akavaram [0064]).
With regard to Claim 5, Yen in view of Akavaram teaches all the limitations of Claim 4 as described above. Akavaram further teaches wherein, to store the indication, the processing circuitry is configured to cause the memory system to:
set, in response to updating one of the plurality of L2P address mappings, a bit indicating that at least one of a set of multiple L2P tables has been updated, wherein the quantity of the respective L2P tables is determined based at least in part on setting the bit ([0008] “setting, by the memory controller, a bit in a second memory of the memory module indicating the update to the first L2P table, and transmitting, to a host device coupled to the memory controller through a first interface, an indication of the update to the first L2P table after setting the bit.” [0064] “when the L2P table 414 of the memory system 404 is updated, the memory system 404 may set a bit in a register of the memory system 404, such as a bit in SRAM of the memory system also storing the L2P table 414 or another memory of the memory system 404. Setting the bit may trigger transmission of an interrupt to the host device 402. When the host device 402 receives the interrupt, the host device 402 may request information indicating the updates to the L2P table 414 of the memory system 404.”).
With regard to claim 6, Yen teaches all the limitations of claim 1 as described above. Yen does not teach the update indication as described in claim 6. Akavaram teaches wherein the processing circuitry is further configured to cause the memory system to:
refrain from performing one or more access operations in response to updating the respective L2P tables ([0071] “7. At block 702, the memory system 110 may update an L2P table and may set an L2P bit... At 704, the memory system 110 may transmit an L2P interrupt to the host device 102... In some embodiments, upon receipt of the L2P interrupt, the host device 102 may suspend one or more read or write operations in a command queue.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Yen with the update indication as taught by Akavaram in order “to maintain synchronization between the L2P table 408 of the host device 402 and the L2P table 414 of the memory system 404” (Akavaram [0064]).
With regard to Claim 10, Yen teaches the memory system of claim 1,
wherein the non-volatile memory comprises NAND memory of the one or more memory devices ([0064] “the MMC 702 stores a L2P table in the RNVM module 406.” [0040] “the rewritable non-volatile memory module 406 is a trinary level cell (TCL) NAND flash memory module”).
With further regard to claim 10, Yen does not teach the static random access memory (SRAM) as described in claim 10. Akavaram teaches
Wherein the volatile memory comprises static random access memory associated with the processing circuitry ([0061] “In some embodiments, the L2P table 414 may be stored in SRAM.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Yen with the SRAM as taught by Akavaram since SRAM is well-known to provide fast access speeds while being low-cost to implement in a memory system as compared to other types of memory technologies.
With regard to Claims 14-16 and 20, these claims are equivalent in scope to Claims 4-6 and 10 rejected above, merely having a different independent claim type, and as such Claims 14-16 and 20 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 4-6 and 10.
With regard to Claim 24, this claim is equivalent in scope to Claim 4 rejected above, merely having a different independent claim type, and as such Claim 24 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 4.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yen as applied to Claims 1 and 11 above, and further in view of Della Monica et al. (US PGPUB 2021/0055966; hereinafter “Della”).
With regard to claim 7, Yen teaches all the limitations of claim 1 as described above. Yen does not teach the checkpoint operation as described in claim 7. Della teaches
wherein updating the respective L2P tables is associated with a checkpoint operation ([0076] “When the real allocated memory consumes all available memory for a changelog, an update checkpoint can be triggered. A checkpoint occurs when the L2P changelog becomes [full] and the checkpoint procedure can include loading all the PPTs that are in the L2P changelog into an L2P cache in order to update PPTs and then flush (store) the modified PPTs into a memory device, for example, a NAND memory device.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Yen with the checkpoint operation as taught by Della such that “continuously swapping in/out L2P Tables from the RAM can be avoided” (Della [0028]).
With regard to Claim 17, this claim is equivalent in scope to Claim 7 rejected above, merely having a different independent claim type, and as such Claim 17 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Pardoe (US PGPUB 2017/0185335) discloses a system comprising a solid state drive (SSD) with power loss protection (PLP), wherein newly entered data is maintained in a temporary logical-to-physical (L2P) update log which is used to update the L2P table stored in the SSD upon encountering a threshold condition.
Wu et al. (“Understanding and Exploiting the Full Potential of SSD Address Remapping,” 2022) discusses improvements to the way which remap operations modify the logical-to-physical (L2P) address mapping table while the physical-to-logical (P2L) mappings persisted on flash memory remain unchanged, including discussion regarding the use of local logs stored in DRAM which record relevant P2L mapping changes.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 March 21, 2026
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