Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 9, 12 – 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over the Xilinx Answer 56616 7 Series PCIe Link Training Debug Guide (NPL), hereinafter the Xilinx Debug Guide, in view of Ross (NPL, Reducing Alert Noise: Rates of Change, retrieved from the Internet Archive).
Regarding claim 1, the Xilinx Debug Guide teaches a memory system, comprising:
one or more memory devices (Page 1, the connected device which is not the host; Page 51 states an example where one side of the link may be a Virtex FPGA);
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (Page 1, the PCIe block itself):
perform, during a first duration, a first quantity of link recovery procedures on at least one input/output (I/O) port (Page 5, there is a link that can go into recovery; Page 18, entering Recovery state) established between the memory system and a host system (Page 51, one example use case involves a link between Virtex FPGAs and a host system);
determine, based at least in part on the first quantity of link recovery procedures satisfying a threshold (Page 51, when the link “frequently” goes into Recovery state, it is an indication of a poor link; There must be some threshold used to determine what constitutes frequent recovery; The concept of a poor link frequently going into recovery is also stated in page 58) a rate of change in the quantity of link procedures (The noted frequency of recovery state), and
initiate a lane margining procedure in response to the rate of change of link recovery procedures increasing (Page 51, frequent Recovery state indicates a poor link. Page 50 final sentence advises that signal integrity checks discussed on page 41 – 50, including margin testing, should be performed in response to the poor link; Page 43, when a link is marginal and goes in and out of recovery, the in-system eye scan provides valuable debug information).
The Xilinx Debug Guide does not explicitly teach that an increase in link recovery procedures is detected by determining a rate of change between the first quantity of link recovery procedures and at least a second quantity of link recovery procedures, wherein the at least second quantity of link recovery procedures is identified over a second duration that is subsequent in time to the first duration (It only states that a high amount of recovery procedures indicates instability, and does not explicitly compare two times).
Ross teaches determining, based at least in part on the first quantity satisfying a threshold (Page 2, both conditions of a threshold and rate of change need to be met to fire a detector, i.e. the determination of the rate of change is based at least in part on the threshold also being met), a rate of change between the first quantity and at least a second quantity, wherein the at least second quantity is identified over a second duration that is subsequent in time to the first duration (The image on page 2, the rate of change is based on the timestamps, which are continuous and in chronological order, i.e. contain some small duration being compared to another small duration), and determining an issue in response to the rate of change increasing (Page 2, the rate of changing increasing is a condition for firing an alert).
It would be obvious to one of ordinary skill in the art that detecting an abnormally high number of link recovery procedures as described in the Xilinx Debug Guide would include detecting an increase over time as taught by Ross. It would be obvious because determining a rate of change is a fundamental method for observing data that one of ordinary skill in the art would perform naturally, and because there may be a scenario in which the rate of change is negative (Ross page 2). In such a scenario, the problematic quantity reaches a threshold, but may be in the process of resolving itself (Ross page 2), making the threshold produce a false positive (Ross page 1). The method of Ross allows for the detector to avoid false positives (Ross page 3). One of ordinary skill in the art would be motivated to avoid false positives in order to reduce the amount of times the margining process needs to be performed.
Regarding claim 2, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
monitor, during the first duration, communications over the at least one I/O port established between the memory system and the host system (Xilinx Debug Guide page 11, probing to determine if the link is training down to a lower speed);
identify one or more failures in the communications over the at least one I/O port, wherein performing the first quantity of link recovery procedures is based at least in part on identifying the one or more failures (Xilinx Debug Guide pages 11 and 12, entering the recovery states is based on a Component A changing the speed to a higher speed to address the low link speed. Furthermore, although not explicitly stated by the Xilinx Debug Guide, it would be clear to one of ordinary skill in the art familiar with the LTSSM that entering the Recovery state in general is based on identifying failures.).
Regarding claim 3, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1, wherein, to determine the rate of change, the processing circuitry is configured to cause the memory system to:
perform a differential computation between the first quantity of link recovery procedures and the at least second quantity of link recovery procedures (Determining a rate of change implicitly includes a differential computation, because the change has to be computed; Ross page 3 shows that what is being considered as the rate of change is the slope of a function).
Regarding claim 4, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine that the first quantity of link recovery procedures satisfies the threshold (Xilinx Debug Guide page 51, noting the link frequently enters recovery), wherein determining the rate of change is based at least in part on the determination (Ross page 2, both conditions need to be met, i.e. the rate of change is only relevant based on the threshold).
Regarding claim 9, Xilinx Debug Guide in view of Ross teaches the memory system of claim 1, wherein the threshold comprises a user-programmable threshold (The image in Ross page 3 shows a GUI where the thresholds are entered by a user programming the detector).
Claim 12 recites similar language to claim 1, and is similarly rejected.
Claim 13 recites similar language to claim 2, and is similarly rejected.
Claim 14 recites similar language to claim 3, and is similarly rejected.
Claim 15 recites similar language to claim 4, and is similarly rejected.
Claim 20 recites similar language to claim 9, and is similarly rejected.
Claims 5 – 8 and 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over the Xilinx Debug Guide in view of Ross as applied to claim 1 above, and further in view of the PIC Express Card Electromechanical Specification Revision 2.0, (NPL, referred to by Xilinx Debug Guide), hereinafter the PCIe Spec.
Regarding claim 5, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1, wherein, to perform the lane margining procedure, the processing circuitry is configured to cause the memory system to:
measure the at least one I/O port to obtain eye pattern information, the eye pattern information comprising an eye width and an eye height of the at least one I/O port (Xilinx Debug Guide page 42, probing the eye diagram. The eye diagram has a height and width as seen in page 44).
The Xilinx Debug Guide in view of Ross does not explicitly state that it determines that the eye width of the at least one I/O port satisfies an eye width threshold, that the eye height of the at least one I/O port satisfies an eye height threshold, or both.
However, the Xilinx Debug Guide refers to the PCIe Spec on page 42, citing a section that describes requirements for the Eye Diagram that must be met.
The cited section of the PCIe Spec (Section 4.7, page 49) teaches determining that the eye width of the at least one I/O port satisfies an eye width threshold (The minimum eye width TTXA), that the eye height of the at least one I/O port satisfies an eye height threshold (The minimum differential peak-peak output voltages VTXA and VTXA_D), or both.
It would be obvious to one of ordinary skill in the art that the margining procedure described in the Xilinx Debug Guide performs the determinations taught by the PCIe Spec. The noted section of the PCIe Spec is directly cited by the Xilinx Debug Guide. One of ordinary skill in the art would clearly understand that details on the eye diagram that the Xilinx Debug Guide does not explicitly teach may be found in the PCIe Spec.
Regarding claim 6, the Xilinx Debug Guide in view of Ross and the PCIe Spec teaches the memory system of claim 5, wherein, to perform the lane margining procedure, the processing circuitry is configured to cause the memory system to:
identify a time during a unit interval to sample signals received from the at least one I/O port based at least in part on the eye width satisfying the eye width threshold (Xilinx Debug Guide page 42 states that a high sampling scope must be used for eye capture. PCIe Spec page 49 describes a sample size of 106 UI).
Regarding claim 7, the Xilinx Debug Guide in view of Ross and the PCIe Spec teaches the memory system of claim 5, wherein, to perform the lane margining procedure, the processing circuitry is configured to cause the memory system to:
identify a reference voltage to compare with a sampled value of signals received from the at least one I/O port based at least in part on the eye height satisfying the eye height threshold (The voltages in the table in PCIe Spec page 49 are voltages based on a reference load. As part of finding the eye diagram and determining the eye height satisfies the eye height threshold, actual voltages are compared to these reference voltages).
Regarding claim 8, the Xilinx Debug Guide in view of Ross and the PCIe Spec teaches the memory system of claim 5, wherein the eye width comprises a time domain metric associated with signals transmitted over the at least one I/O port (PCIe Spec page 49, the eye width is a time), and the eye height comprises a voltage metric associated with the signals transmitted over the at least one I/O port (PCIe Spec page 49, the eye height is a voltage).
Claim 16 recites similar language to claim 5, and is similarly rejected.
Claim 17 recites similar language to claim 6, and is similarly rejected.
Claim 18 recites similar language to claim 7, and is similarly rejected.
Claim 19 recites similar language to claim 8, and is similarly rejected.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over the Xilinx Debug Guide as applied to claim 1 above, and further in view of Kumar et al. (US Patent Application Publication 2019/0042458), hereinafter Kumar.
Regarding claim 10, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1.
The Xilinx Debug Guide does not explicitly teach that the threshold is stored in a mode register of the memory system.
The Xilinx Debug Guide does, however, teach that mode registers of the memory system exist (Page 11 discloses configuration registers).
Kumar teaches two different thresholds which are stored in a mode register of a memory system (Paragraphs 0048 – 0054).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that any relevant threshold used by a memory system such as the one described in the Xilinx Debug Guide in view of Ross could be stored in a mode register of the system, as taught by Kumar. It would be obvious because a register allows the system to store and use the threshold value, as well as configure it as taught by Kumar. Registers are a well-known components for storing values, and the Xilinx Debug Guide operates on systems containing mode registers. It would be clear to one of ordinary skill in the art that a basic component such as a register would be used when implementing the memory system of the Xilinx Debug Guide in view of Ross.
Claim 21 recites similar language to claim 10, and is similarly rejected.
Claims 11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over the Xilinx Debug Guide in view of Ross as applied to claim 1 above, and further in view of the Wikipedia article for PCI Express (NPL, archived).
Regarding claim 11, the Xilinx Debug Guide in view of Ross teaches the memory system of claim 1.
The Xilinx Debug Guide in view of Ross does not explicitly teach that the memory system comprises a solid state drive.
The Wikipedia article for PCI Express teaches that memory systems using PCIe include SSDs (Header).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the PCIe link described in the Xilinx Debug Guide could comprise an SSD as taught by PCIe. It would have been obvious because PCIe is a well-known standard commonly used with SSDs (Wikipedia Header). One of ordinary skill in the art would understand that the use cases of the link described in the Xilinx Debug Guide would include common uses for PCIe, including systems comprising SSDs.
Claim 22 recites similar language to claim 11, and is similarly rejected.
Claims 23 – 25 are rejected under 35 U.S.C. 103 as being unpatentable over the Xilinx Debug Guide in view of Ross and well-known methods for executing computer processes.
Regarding claim 23, the Xilinx Debug Guide does not explicitly teach a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors.
The Xilinx Debug Guide is, however, directed to a computer process.
The Examiner takes official notice that it is well-known that computer processes such as those taught by the Xilinx Debug Guide are executing by using a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors.
It would have been obvious for one of ordinary skill in the art that the process of the Xilinx Debug Guide would be performed by using a non-transitory computer-readable medium storing code. It would be obvious because it is a standard method for executing a computer process.
Claim 23 otherwise recites similar language to claim 1, and is similarly rejected.
Claim 24 recites similar language to claim 2, and is similarly rejected.
Claim 25 recites similar language to claim 3, and is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hammad et al. (US Patent Application 2014/0270030) teaches margining methods. Jeon et al. (US Patent Application Publication 2021/0391973) teaches methods for initiating margining in a PCIe link.
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/B.P.H./ Examiner, Art Unit 2114
/ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114