DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's terminal disclaimer concerning the nonstatutory double-patenting rejections have been considered. In view of the terminal disclaimer filed August 17, 2026, the nonstatutory double-patenting rejections over U.S. Patent No. 12,230,232 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-5, 7-9 and 11-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over HELMICK et al. [US 2021/0374003 A1] in view of Kuzmin et al. [US 2014/0215129 A1].
Claim 2 is rejected over HELMICK and Kuzmin.
HELMICK teaches “A memory system, comprising: processing circuitry configured to couple with one or more memory devices, wherein the processing circuitry is configured to cause the memory system to:” as “The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones.” [Abstract]
“receive a write command to write data in a zone of the memory system;” as “the first zone 306a is associated with Z.sub.aSLBA, the second zone 306b is associated with Z.sub.bSLBA, the third zone 306c is associated with Z.sub.cSLBA, the fourth zone 306d is associated with Z.sub.dSLBA, and the n.sup.th zone 306n (i.e., the last zone) is associated with Z.sub.nSLBA. Each zone 306 is identified by its ZSLBA, and is configured to receive sequential writes (i.e., writing data to the NVM 110 in the order the write commands are received).” [¶0045]
HELMICK does not explicitly teach write the data to the zone using a type of write operation that is in accordance with a quantity of the data, wherein the type of the write operation comprises one of a first type of the write operation associated with writing to multiple planes of the memory system or a second type of the write operation associated with writing to one plane of the memory system; and
write an indication of the type of the write operation in accordance with writing the data to the zone.
However, Kuzmin teaches “write the data to the zone using a type of write operation that is in accordance with a quantity of the data, wherein the type of the write operation comprises one of a first type of the write operation associated with writing to multiple planes of the memory system or a second type of the write operation associated with writing to one plane of the memory system; and” as “ A returned command status code can further specify whether the requested amount of space was available, whether the request was satisfied or whether further calls are required. The host then directs its writes as appropriate, directly specifying addresses for pertinent memory operations.” [¶0093]
“write an indication of the type of the write operation in accordance with writing the data to the zone.” as “At step 1813, host software screens whether each suggested candidate is an appropriate candidate for relocation; for example, due to policy or other considerations, it might be desired to not relocate certain types of data (e.g., a host policy is in effect that groups certain types of data together at one location based on read-write characteristics).” [¶0175]
Helmick and Kuzmin are analogous arts because they teach storage system and memory access controlling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Helmick and Kuzmin before him/her, to modify the teachings of Helmick to include the teachings of Kuzmin with the motivation of host commands advantageously equate physical and logical space from the vantage point of the flash memory controller, because those commands directly address physical pages, EUs or other unit that are the target of intended operations, with at most insubstantial address translation in the memory controller. [Kuzmin, ¶0036]
Claim 3 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the type of the read operation comprises one of a first type of the read operation associated with reading from multiple planes of the memory system or a second type of the read operation associated with reading from one plane of the memory system.” as “the controller 108 can read data from and write data to the plurality of logical blocks associated with the plurality of erase blocks of the NVM 110.” [¶0026] and “Each of the one or more planes comprises one or more erase blocks.” [¶0042]
HELMICK does not explicitly teach wherein the processing circuitry is further configured to cause the memory system to: read the data from the memory system in accordance with a type of read operation associated with the type of the write operation used to write the data,
However, Kuzmin teaches “wherein the processing circuitry is further configured to cause the memory system to: read the data from the memory system in accordance with a type of read operation associated with the type of the write operation used to write the data,” as “a host policy is in effect that groups certain types of data together at one location based on read-write characteristics” [¶0093]
Claim 4 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the first type of the read operation includes parallel read operations on the multiple planes.” as “to partially fill each block in a parallel fashion (i.e., writing the first NAND location of each erase block before writing to the second NAND location of each erase block).” [¶0043]
Claim 5 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the first type of the read operation includes sequential read operations on the one plane.” as “when writing data to a particular zone 306, data may be written to the plurality of erase blocks one block at a time, in sequential order of NAND locations or wordline-by-wordline, until moving to an adjacent block (i.e., write to a first erase block until the first erase block is full before moving to the second erase block), or to multiple blocks at once, in sequential order of NAND locations or wordline-by-wordline, ” [¶0043]
Claim 7 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the processing circuitry is further configured to cause the memory system to: receive a read command to read the data from the zone; and” as “When the controller 308 receives a command, such as from a host device (not shown) or the submission queue of a host device, the controller 308 can read data from and write data to the plurality of logical blocks associated with the plurality of erase blocks (EBs) of the ZNS 302. Each of the logical blocks is associated with a unique LBA or sector.” [¶0041]
“access the indication of the type of the write operation in accordance with receiving the read command to read the data,” as “The interrupt signal indicates that the command has been executed and data associated with the command is available in the memory device. ” [¶0038]
“wherein the type of the read operation is in accordance with accessing the indication of the type of the write operation.” as “The interrupt signal further notifies the host device that the completion queue is ready to be read or processed.” [¶0038]
Claim 8 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the type of the read operation is in accordance with a second quantity of the data associated with the read operation and a buffer availability.” as “Unwritten user or host data may comprise small lengths or amount of data (e.g., less than the size of one or more wordlines) that are stored in a parking location or buffer until the aggregated size of the data reaches a minimum size (e.g., the size of one or more wordlines), in which case the unwritten user data is written to the NVM 110.” [¶0059] (Read and write commands are based on same type, so, the teaching of write buffer can be applied to read command as well.)
Claim 9 is rejected over HELMICK and Kuzmin.
HELMICK does not explicitly teach wherein, to write the indication of the type of the write operation, the processing circuitry is further configured to cause the memory system to: write the indication of the type of the write operation in a bit field of a logical-to- physical mapping.
However, Kuzmin teaches “wherein, to write the indication of the type of the write operation, the processing circuitry is further configured to cause the memory system to: write the indication of the type of the write operation in a bit field of a logical-to- physical mapping.” as “ At step 1813, host software screens whether each suggested candidate is an appropriate candidate for relocation; for example, due to policy or other considerations, it might be desired to not relocate certain types of data (e.g., a host policy is in effect that groups certain types of data together at one location based on read-write characteristics).” [¶0175]
Claim 11 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the first type of the write operation includes parallel write operations in the multiple planes.” as “to partially fill each block in a parallel fashion (i.e., writing the first NAND location of each erase block before writing to the second NAND location of each erase block).” [¶0043]
Claim 12 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the second type of the write operation includes sequential write operations in the one plane.” as “when writing data to a particular zone 306, data may be written to the plurality of erase blocks one block at a time, in sequential order of NAND locations or wordline-by-wordline, until moving to an adjacent block (i.e., write to a first erase block until the first erase block is full before moving to the second erase block), or to multiple blocks at once, in sequential order of NAND locations or wordline-by-wordline, ” [¶0043]
Claim 13 is rejected over HELMICK and Kuzmin under the same rationale of rejection of claim 2 considering the teaching of write command can be applied to read command as well.
Claim 14 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein to read the data form the zone, the processing circuitry is further configured to cause the memory system to: read the data via multiple planes of the memory system based at least in part on the indication of the type of the write operation indicating the first type of the write operation.” as “the controller 108 can read data from and write data to the plurality of logical blocks associated with the plurality of erase blocks of the NVM 110.” [¶0026] and “Each of the one or more planes comprises one or more erase blocks.” [¶0042]
Claim 15 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein to read the data from the zone, the processing circuitry is further configured to cause the memory system to: read the data via one plane of the memory system based at least in part on the indication of the type of the write operation indicating the second type of the write operation.” as “when writing data to a particular zone 306, data may be written to the plurality of erase blocks one block at a time, in sequential order of NAND locations or wordline-by-wordline, until moving to an adjacent block (i.e., write to a first erase block until the first erase block is full before moving to the second erase block), or to multiple blocks at once, in sequential order of NAND locations or wordline-by-wordline, ” [¶0043]
Claim 16 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the data is read from the zone in accordance with a type of read operation, and wherein the type of the read operation is in accordance with the quantity of the data and a buffer availability.” as “Unwritten user or host data may comprise small lengths or amount of data (e.g., less than the size of one or more wordlines) that are stored in a parking location or buffer until the aggregated size of the data reaches a minimum size (e.g., the size of one or more wordlines), in which case the unwritten user data is written to the NVM 110.” [¶0059] (Read and write commands are based on same type, so, the teaching of write buffer can be applied to read command as well.)
Claim 17 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the processing circuitry is further configured to cause the memory system to: write the data in a buffer in response to the data being read from the zone; and” as “In a full zone, the write pointer points to the end of the writeable capacity of the zone. Read commands of data stored in full zones may still be executed.” [¶0050]
“transmit the data from the buffer to a host system in response to writing the data in the buffer.” as “the controller includes three available controller RAM or buffer regions 504a, 504b, 504c for storing host write commands and one available parity RAM or buffer region 506 for storing parity data. T” [¶0071]
Claim 18 is rejected over HELMICK and Kuzmin.
HELMICK teaches “wherein the processing circuitry is further configured to cause the memory system to: receive an additional access command from the host system; and overwrite the data in the buffer with second data associated with the additional access command.” as “Throughout times 1-3, a previous write command, such as the first host write command 532, in the first controller buffer region 534a has been successfully written to the NVM, and the data in the first controller buffer region 534a can be overwritten with the data of a new host write command, such as the fourth host write command 556.” [¶0079]
Claim 19 is rejected over HELMICK and Kuzmin under the same rationale of rejection of claim 2.
Claim 20 is rejected over HELMICK and Kuzmin under the same rationale of rejection of claim 3.
Claim 21 is rejected over HELMICK and Kuzmin under the same rationale of rejection of claim 4.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over HELMICK et al. [US 2021/0374003 A1] in view of Kuzmin et al. [US 2014/0215129 A1] and in further view of Frans [US 2020/0111514 A1].
Claim 6 is rejected over HELMICK, Kuzmin and Frans.
The combination of HELMICK and Kuzmin does not explicitly teach wherein the first type of the read operation is associated with a first read rate, and the second type of the read operation is associated with a second read rate,and wherein the first read rate is greater than the second read rate.
However, Frans teaches “wherein the first type of the read operation is associated with a first read rate, and the second type of the read operation is associated with a second read rate,and wherein the first read rate is greater than the second read rate.” as “ in response to a first read command, receive read data from a second DRAM die at a first data rate and to transfer the read data to a memory controller at a second data rate that is higher than the first data rate.” [Claim 2]
HELMICK, Kuzmin and Frans are analogous arts because they teach storage system and memory access controlling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of HELMICK, Kuzmin and Frans before him/her, to modify the teachings of combination of HELMICK and Kuzmin to include the teachings of Frans with the motivation of providing an efficient way of coupling two or more memory die with through-die vias. [Frans, ¶0066]
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over HELMICK et al. [US 2021/0374003 A1] in view of Kuzmin et al. [US 2014/0215129 A1] and in further view of ZITLAW [US 2013/0262907 A1].
Claim 10 is rejected over HELMICK, Kuzmin and ZITLAW.
The combination of HELMICK and Kuzmin does not explicitly teach wherein, a first bit value of the bit field indicates the first type of the write operation, and a second bit value indicates the second type of the write operation.
However, ZITLAW teaches “wherein, a first bit value of the bit field indicates the first type of the write operation, and a second bit value indicates the second type of the write operation.” as “ Bit 15 (Burst Type) indicates whether the burst of the transaction output is continuous or wrapped. For instance, a Burst Type value of 0 indicates a wrapped burst, whereas a value of 1 indicates a continuous burst.” [¶0073]
HELMICK, Kuzmin and ZITLAW are analogous arts because they teach storage system and memory access controlling.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of HELMICK, Kuzmin and ZITLAW before him/her, to modify the teachings of combination of HELMICK and Kuzmin to include the teachings of ZITLAW with the motivation of providing for implementing reduced pin count memory bus interfaces that exhibit lower initial latencies and higher sustained throughputs. [ZITLAW, ¶0022]
Response to Arguments
Applicant's arguments filed August 17, 2026 have been fully considered but are not persuasive with respect to the rejection of claims 2–21 under 35 U.S.C. § 103.
Applicant argues that Kuzmin does not teach or suggest writing data using a type of write operation selected in accordance with a quantity of the data, wherein the type of write operation comprises a first type associated with writing to multiple planes or a second type associated with writing to one plane. Applicant further argues that Kuzmin merely describes determining where data is written and does not disclose determining how the data is written. Applicant additionally argues that Kuzmin's discussion of grouping data based on read-write characteristics does not teach writing an indication identifying a type of write operation.
The arguments are respectfully not persuasive because they address the teachings of Kuzmin individually rather than the teachings of Helmick and Kuzmin as combined in the rejection. The rejection does not rely upon Kuzmin, standing alone, for the entirety of the claimed write-operation functionality. Helmick teaches a memory system capable of performing different write operations depending upon the amount and organization of data to be written. In particular, Helmick teaches parallel operations involving multiple planes/erase blocks as well as sequential operations in which data is written one block at a time. Thus, Helmick establishes that the memory system supports alternative write modes corresponding to writing data in parallel across multiple memory portions or writing data to a more limited memory portion.
Kuzmin is relied upon for the additional teaching of using information associated with a requested memory operation in determining how the memory operation is to be carried out. As discussed in the Office Action, Kuzmin teaches that a host may request an amount of memory space, receive information concerning whether the requested amount is available, and thereafter direct memory operations as appropriate. Kuzmin further teaches policies that group or process data based upon read-write characteristics. One of ordinary skill in the art, considering these teachings together with Helmick's expressly disclosed alternative parallel and sequential memory operations, would have found it obvious to select an appropriate available write operation based upon the quantity of data presented for writing.
Applicant's distinction between determining where data is written and determining how data is written therefore does not establish nonobviousness of the claimed subject matter. The rejection is based upon what the combined teachings would have suggested to one of ordinary skill in the art, rather than upon whether Kuzmin expressly uses Applicant's terminology of a “first type” and “second type” of write operation. Helmick provides the alternative write-operation mechanisms, while Kuzmin provides teachings concerning the use of data/request characteristics and host/controller information in directing memory operations. Applying Kuzmin's selection/control teachings to Helmick's available write modes would have been no more than the predictable use of known memory-control techniques according to their established functions.
Applicant further argues that Kuzmin does not teach “write an indication of the type of the write operation.” This argument is also not persuasive. Kuzmin's teachings concerning maintaining and communicating information used to control memory operations, when considered with Helmick's different available write modes, would have suggested maintaining an indication identifying the selected write operation so that the memory system can subsequently process the written data consistently with the manner in which the data was written. The claimed “indication” does not require any particular format or encoding beyond indicating the selected type of write operation.
Accordingly, Applicant's arguments have been considered but are not persuasive, and the rejection of independent claim 2 under 35 U.S.C. § 103 over Helmick in view of Kuzmin is maintained.
Applicant argues that independent claims 13 and 19 are allowable for reasons similar to claim 2 and that dependent claims 3-12, 14-18, 20, and 21 are allowable because they depend from allegedly allowable independent claims. These arguments are likewise not persuasive because, for the reasons discussed above, Applicant has not established error in the rejection of the underlying independent claims. Moreover, the additional limitations of the dependent claims remain taught or suggested by the respective references identified in the Office Action. Accordingly, the rejections of claims 2–21 under 35 U.S.C. § 103 are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MASUD K KHAN/ Primary Examiner, Art Unit 2132
Prosecution Insights