DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/020,975 filed on 1/14/2025, which is a continuation of application 19/020,975 filed on 10/21/2022, which is a continuation of application 17/215,581 filed on 3/29/2021, which is a continuation of 16/536,941 filed on 8/9/2019, which is a continuation of application 15/669,300 filed on 8/4/2017, which is a continuation of PCT/US2016/015027 filed on 1/27/2016, which claims priority to 62/112,843 filed on 2/6/2015.
Claims 1-20 have been examined.
Information Disclosure Statement
In an attempt to fulfill Applicant's duty to disclose information, which is material to patentability according to 37 CFR 1.56, applicants have submitted a large number of documents for the Examiner to consider. However, it appears from a cursory review of the documents that the vast majority of them are not material to patentability and should not have been submitted. In fact, the sheer number of documents creates an undue burden on the Examiner since if each document is material to patentability, each document must be carefully considered.
According to MPEP 609 (emphasis added): "Although a concise explanation of the relevance of the information is not required for English language information, applicants are encouraged to provide a concise explanation of why the English- language information is being submitted and how it is understood to be relevant. Concise explanations (especially those which point out the relevant pages and lines) are helpful to the Office, particularly where documents are lengthy and complex and applicant is aware of a section that is highly relevant to patentability or where a large number of documents are submitted and applicant is aware that one or more are highly relevant to patentability."
Additionally, Applicant is made aware of the court decision in Penn Yan Boats, Inc. v. Sea Lark Boats, Inc., et al., 175 USPQ 260 (DC SFla, 1972) which stated that "Applicant has obligation to call most pertinent prior patent to attention of Patent Office in a proper fashion and to attempt to patentably distinguish his claimed invention from disclosure of patent; failure to take these affirmative steps, particularly when coupled with misrepresentations made to the Patent Office, renders unenforceable the patent issued on his application." Apparently, a good reference was buried in the mountain of prior art in the case and never pointed out by the Applicant.
Applicant is reminded that only documents which are "material to patentability" should be submitted. See 37 CFR 1.56 for definition of materiality.
Accordingly, in view of the limited amount of time available to the Examiner to review the numerous references cited by the applicant, each reference has received only a cursory review by the Examiner. Applicant has a duty to point out any of these references which are particularly relevant to the claims of the instant invention so that those references may receive an in-depth review. Applicant's submission of such an excessive number of references has limited the Examiner's ability to consider any of them in detail since each of them must be considered to some degree and the Examiner has a limited amount of time to work on this case.
Applicant is instructed that the duty of disclosure of material is not satisfied by presenting the Examiner with "a mountain of largely irrelevant (material) from which he is presumed to have been able, with his expertise and with adequate time, to have found the critical (material). It ignores the real world conditions under which examiners work." Rohm & Haas Co. v. Crystal Chemical Co., 722 F.2d 1556, 1573 (220 USPQ 289) (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
Applicant is reminded of the duty not just to disclose pertinent prior art references but to make that disclosure in such way as not to "bury" it within other disclosures of less relevant prior art; See Go/den Valley Microwave Foods Inc. v. Gealer Popcorn Co. Inc., 24 USPQ2d 1801 (N.D. Ind. 1992)., Molins PLC v. Textron Inc.t 26 USPQ2d 1889, at 1899 (D.Del. 1992)., Penn Yan Boats, Inc. v. Sea Lark Boats, Inc. et al., 175 USPQ 260, at 272 (S.D. FI. 1972).
Applicant should highlight those documents which have been specifically brought to applicant's attention and/or are known to be of most significance. See Penn Yan Boats, Inc. v. Sea Lark Boats, Inca, 359 F. Supp. 948, 175 USPQ 260 (S.D. Fla. 1972), aff'd, 479 F.2d 1338, 178 USPQ 577 (5th Cir. 1973), cert. denied, 414 U.S. 874 (1974). But cf. Molins PLC v. Textron Inc., 48 F.3d 1 172, 33 USPQ2d 1823 (Fed. Cir. 1995).
It is impractical for the examiner to review the references thoroughly with the number of references cited in this case. By initializing each of the cited references on the accompanying 1449 forms, the examiner is merely acknowledging the submission of the cited references and indicating that only a cursory review has been made of the cited references.
MPEP § 2004.13 states: It is desirable to avoid the submission of long lists of documents if it can be avoided. Eliminate clearly irrelevant and marginally pertinent cumulative information. If a long list is submitted, highlight those documents, which have been specifically brought to applicant's attention and/or are known to be of most significance. See Penn Yan Boats, Inc. v. Sea Lark Boats, Inc., 359 F. Supp. 948, 175 USPQ 260 (S.D. Fla. 1972), aff'd, 479 F.2d 1338, 178 USPQ 577 (5th Cir. 1973), cert. denied, 414 U.S. 874 (1974). But cf. Molins PLC v. Textron Inc., 48 F.3d 1172, 33 USPQ2d 1823 (Fed. Cir. 1995).
The information disclosure statement (IDS) submitted on 2/25/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 7-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp et al. (US 5,689,653) and Panwar et al. (US 7,889,741).
With respect to claim 1, Karp teaches of a memory system, comprising: at least one memory device (fig. 1-2; column 3, line 63-column 4, line 8; where the computer system includes a memory hierarchy); and
at least one controller coupled with the at least one memory device (fig. 1-2; column 3, line 63-column 8, column 6, lines 48-column 7, line 19, column 9, lines 10-33; vector prefetch unit, register file controller, and memory controller),
wherein the at least one controller is configured to: iterate through indices of an index vector, wherein the indices correspond to a respective portion of a first vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer);
merge, in a buffer of the at least one controller, the respective portions of the first vector to obtain a second vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
output the second vector in accordance with merging the respective portions of the first vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer and the store vector buffer loads the elements into a contiguous vector).
Karp fails to explicitly teach of at least one memory device comprising a plurality of memory banks.
However, Panwar teaches of at least one memory device comprising a plurality of memory banks (fig. 4; column 11, lines 32-56; where action descriptor memory includes multiple memory banks).
Karp and Panwar are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp and Panwar before the time of the effective filing of the claimed invention to incorporate the multiple memory banks of Panwar into the memory of Karp. Their motivation would have been to more efficiently access the memory.
With respect to claim 2, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 3, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in the buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
transmit one or more instructions to gather the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 11, lines 16-38; as the second load vector buffer loads the data elements from the memory at addresses indexed by the elements of the first load vector buffer, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be loaded by the second load vector buffer).
With respect to claim 7, Karp teaches of wherein the buffer of the at least one controller is a first buffer, and wherein the at least one controller comprises a plurality of additional buffers configured to bin the indices of the index vector (column 11, lines 16-38; where the first load vector buffer is the claimed first buffer and the second load vector buffer gathers the discontinuous vector elements and stored them into the store vector buffer as a contiguous vector).
With respect to claim 8, Karp teaches of wherein the second vector is output to a host system coupled with the memory system (column 4, lines 19-22, column 11, lines 16-38; where the load vector buffers transfers the data to the registers of the processor).
With respect to claim 9, the combination of Karp and Panwar teaches of wherein the second vector is output to one or more banks of the plurality of memory banks (Karp, column 4, lines 19-22, column 11, lines 16-38; Panwar fig. 4; column 11, lines 32-56; where the store vector buffer transfers data back into the memory hierarchy. In the combination, the memory hierarchy includes the memory banks of Panwar).
With respect to claim 10, Karp teaches of a memory system, comprising: at least one memory device (fig. 1-2; column 3, line 63-column 4, line 8; where the computer system includes a memory hierarchy); and
at least one controller coupled with the at least one memory device (fig. 1-2; column 3, line 63-column 8, column 6, lines 48-column 7, line 19, column 9, lines 10-33; vector prefetch unit, register file controller, and memory controller),
wherein the at least one controller is configured to: obtain a first vector comprising data to be written to the at least one memory device (column 11, lines 16-38; where the mode value indicates a scatter operation and the first load buffer loads data elements of a contiguous vector);
iterate through indices of an index vector, wherein each index of the index vector corresponds to a respective location of the at least one memory device to which a respective portion of the first vector is to be written (column 11, lines 16-38; where the mode value indicates a scatter operation and the first load buffer loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer); and
write the first vector to the at least one memory device in accordance with the indices of the index vector (column 4, lines 19-23; column 11, lines 16-38; where the first load buffer loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer and the store vector buffer is used to vector transfer data back to the memory hierarchy).
Karp fails to explicitly teach of at least one memory device comprising a plurality of memory banks.
However, Panwar teaches of at least one memory device comprising a plurality of memory banks (fig. 4; column 11, lines 32-56; where action descriptor memory includes multiple memory banks).
Karp and Panwar are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp and Panwar before the time of the effective filing of the claimed invention to incorporate the multiple memory banks of Panwar into the memory of Karp. Their motivation would have been to more efficiently access the memory.
With respect to claim 11, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 12, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in a buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the second load vector buffer is an index vector and the first load vector loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer); and
transmit one or more instructions to scatter the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 4, lines 19-23; column 11, lines 16-38; as the store vector buffer stores the data elements of a contiguous vector in the first load buffer and the store vector buffer transfers data back to the memory hierarchy, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be stored back into the memory hierarchy including Panwar’s memory banks).
With respect to claim 15, Karp teaches of wherein the buffer of the at least one controller is a first buffer, and wherein the at least one controller comprises a plurality of additional buffers configured to bin the indices of the index vector (column 11, lines 16-38; where the second load vector buffer is the claimed first buffer and the first load vector loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer).
Claim(s) 4, 13, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp, Panwar, and Walker (US 2010/0312990).
With respect to claim 4, the combination of Karp and Panwar fails to explicitly teach of herein each bank of the plurality of memory banks is coupled with a compute component.
However, Walker teaches of herein each bank of the plurality of memory banks is coupled with a compute component (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
The combination of Karp, Panwar, and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from a corresponding memory bank of the plurality of memory banks in response to the one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar); and
output the respective portions of the first vector to the at least one controller in response to the obtaining, wherein merging the respective portions of the first vector is in accordance with the output of the respective portions of the first vector (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar and provides them to the second load vector buffer of Karp).
Karp, Panwar, and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp and Panwar. Their motivation would have been to more quickly process operations.
With respect to claim 13, the combination of Karp and Panwar fails to explicitly teach of herein each bank of the plurality of memory banks is coupled with a compute component.
However, Walker teaches of herein each bank of the plurality of memory banks is coupled with a compute component (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
The combination of Karp, Panwar, and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from one controller in response to one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the index vector from the store vector buffer of Karp); and
write the respective portions of the first vector to a corresponding memory bank of the plurality of memory banks in response to the obtaining, wherein writing the first vector to the at least one memory device corresponds to writing, by each compute component, the respective portions of the first vector to the corresponding memory bank of the plurality of memory banks. (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker writes the data elements in the store vector buffer to the memory buffers in the memory hierarchy).
Karp, Panwar, and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp and Panwar. Their motivation would have been to more quickly process operations.
With respect to claim 16, the combination of Karp and Panwar teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
The combination of Karp and Panwar fails to explicitly teach of a processor in memory (PIM) device comprising: a plurality of memory banks each coupled with a compute component; and at least one controller coupled with the PIM device.
However, Walker teaches of a processor in memory (PIM) device comprising: a plurality of memory banks each coupled with a compute component; and at least one controller coupled with the PIM device (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
Karp, Panwar, and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp and Panwar. Their motivation would have been to more quickly process operations.
With respect to claim 17, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 18, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in the buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
transmit one or more instructions to gather the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 11, lines 16-38; as the second load vector buffer loads the data elements from the memory at addresses indexed by the elements of the first load vector buffer, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be loaded by the second load vector buffer).
With respect to claim 19, the combination of Karp, Panwar, and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from a corresponding memory bank of the plurality of memory banks in response to the one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar); and
output the respective portions of the first vector to the at least one controller in response to the obtaining, wherein merging the respective portions of the first vector is in accordance with the output of the respective portions of the first vector (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar and provides them to the second load vector buffer of Karp).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 16.
Claim 5, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable Karp, Panwar, and Walker as applied to claim 4, 13, and 19 above and in further view of Shin et al. (US 2002/0157054).
With respect to claims 5 and 20, the combination of Karp, Panwar, and Walker fails to explicitly teach of wherein the one or more instructions to gather the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks.
However, Shin teaches of wherein the one or more instructions to gather the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks (paragraph 154; where the access layer receives commands and data from the transport layer, directs the arbiter to connect the port to the appropriate memory bank, and transmits commands and data to the memory bank. In the combination, the commands are the gather commands of Karp (column 4, lines 19-23; column 11, lines 16-38)).
Karp, Panwar, Walker, and Shin are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Walker, and Shin at the time of the effective filing of the invention to incorporate the arbiter directing commands to the appropriate memory bank into the combination of Karp, Panwar, and Walker. Their motivation would have been to more efficiently access the memory.
With respect to claim 14, Shin teaches of wherein the one or more instructions to scatter the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks (paragraph 154; where the access layer receives commands and data from the transport layer, directs the arbiter to connect the port to the appropriate memory bank, and transmits commands and data to the memory bank. In the combination, the commands are the scatter commands of Karp (column 4, lines 19-23; column 11, lines 16-38)).
The reasoning for obviousness is the same as indicated above with respect to claim 5.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable Karp, Panwar, and Walker as applied to claim 4 and in further view of Borchers et al. (US 2010/0262767).
The combination of Karp, Panwar, and Walker fails to explicitly teach of wherein the respective portions of the first vector are output from each bank of the plurality of memory banks via an out-of-band (OOB) bus.
However, Borchers teaches of wherein the respective portions of the first vector are output from each bank of the plurality of memory banks via an out-of-band (OOB) bus (fig. 5; paragraph 6, 13, 16, 74-77).
Karp, Panwar, Walker, and Borchers are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Walker, and Borchers at the time of the effective filing of the invention to incorporate the out of band bus of Borchers into the combination of Karp, Panwar, and Walker. Their motivation would have been to enable execution of commands while minimizing processing impact and overhead (Borchers, paragraph 5).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 14 of U.S. Patent No. 12,230,354. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of US 12,230,354 anticipate the limitations of claim 10 of the present invention.
Claims 1 and 7 are rejected on the ground of obviousness nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 12,230,354 in view of Panwar et al. (US 7,889,741).
U.S. Patent No. 12,230,354 fails to explicitly claim that the at least one memory device comprising a plurality of memory banks. However, Panwar discloses at least one memory device comprising a plurality of memory banks (fig. 4; column 11, lines 32-56; where action descriptor memory includes multiple memory banks).
U.S. Patent No. 12,230,354’s claims and Panwar are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of U.S. Patent No. 12,230,354’s claims and Panwar before the time of the effective filing of the claimed invention to incorporate the multiple memory banks of Panwar into the memory of U.S. Patent No. 12,230,354’s claims. Their motivation would have been to more efficiently access the memory.
See the chart below for a mapping of the rejected claims.
Application 19/020,975
US 12,230,354
Claim 1: A memory system, comprising: at least one memory device comprising a plurality of memory banks; and
Claim 1: A system, comprising: a host configured to generate a block of instructions including instructions for a gather operation; and … a memory device to which the controller is coupled…
at least one controller coupled with the at least one memory device, wherein the at least one controller is configured to:
a controller configured to: receive the block of instructions; and execute the gather operation by: … a memory device to which the controller is coupled…
iterate through indices of an index vector, wherein the indices correspond to a respective portion of a first vector;
iterating through indices of an index vector stored in a memory device to which the controller is coupled, the indices pointing to respective first vector portions corresponding to the gather operation;
merge, in a buffer of the at least one controller, the respective portions of the first vector to obtain a second vector; and
reading the respective first vector portions from an array of the memory device; merging, in a buffer of the controller, the first vector portions read from the array; and
output the second vector in accordance with merging the respective portions of the first vector.
writing the merged first vector portions to a second vector corresponding to the gather operation, wherein the second vector is stored in the array.
Claim 7
Claim 6
Claim 10: A memory system, comprising: at least one memory device comprising a plurality of memory banks; and
Claim 9: A system, comprising: a host configured to generate a block of instructions including instructions for a scatter operation; and
Claim 14: wherein the array comprises multiple banks…
at least one controller coupled with the at least one memory device, wherein the at least one controller is configured to:
a controller configured to: receive the block of instructions; …an array of a memory device to which the controller is coupled…
obtain a first vector comprising data to be written to the at least one memory device;
and execute the scatter operation by: iterating through indices of an index vector stored in an array of a memory device to which the controller is coupled,
iterate through indices of an index vector, wherein each index of the index vector corresponds to a respective location of the at least one memory device to which a respective portion of the first vector is to be written; and
iterating through indices of an index vector stored in an array of a memory device to which the controller is coupled, the indices pointing to respective locations in the array to which respective portions of a first vector corresponding to the scatter operation are to be written;
write the first vector to the at least one memory device in accordance with the indices of the index vector.
reading, from the array, a second vector corresponding to the scatter operation, the second vector comprising data to be written at the respective locations in the array to which the respective portions of the first vector correspond; and writing the first vector to the array, the respective portions of the first vector being written at the respective locations in array pointed to by the respective indices of the index vector.
Conclusion
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138