DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 6/23/2026.
Claims 1, 10, and 16 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Terminal Disclaimer
The terminal disclaimer filed on 6/23/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 12,230,354 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 7-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp et al. (US 5,689,653), Panwar et al. (US 7,889,741), and Van Berkel (US 2009/0300310)
With respect to claim 1, Karp teaches of a memory system, comprising: at least one memory device (fig. 1-2; column 3, line 63-column 4, line 8; where the computer system includes a memory hierarchy); and
at least one controller coupled with the at least one memory device (fig. 1-2; column 3, line 63-column 8, column 6, lines 48-column 7, line 19, column 9, lines 10-33; vector prefetch unit, register file controller, and memory controller),
wherein the at least one controller is configured to: iterate through indices of an index vector, wherein each index of the index vector corresponds to a respective portion of a first vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by each element of the first load buffer);
merge, in a buffer of the at least one controller, the respective portions of the first vector to obtain a second vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
output the second vector in accordance with merging the respective portions of the first vector (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer and the store vector buffer loads the elements into a contiguous vector).
Karp fails to explicitly teach of at least one memory device comprising a plurality of memory banks.
However, Panwar teaches of at least one memory device comprising a plurality of memory banks (fig. 4; column 11, lines 32-56; where action descriptor memory includes multiple memory banks).
The combination of Karp and Panwar fails to explicitly teach of merge, in a buffer of the at least one controller, the respective portions of the first vector received from respective memory banks of the plurality of memory banks in accordance with the indices of the index vector to obtain a second vector, wherein at least a first portion of the first vector corresponding to a first index of the index vector is received from a first memory bank of the plurality of memory banks and a second portion of the first vector corresponding to a second index of the index vector is received from a second, different memory bank of the plurality of memory banks.
However, Van Berkel teaches of merge, in a buffer of the at least one controller, the respective portions of the first vector received from respective memory banks of the plurality of memory banks in accordance with the indices of the index vector to obtain a second vector, wherein at least a first portion of the first vector corresponding to a first index of the index vector is received from a first memory bank of the plurality of memory banks and a second portion of the first vector corresponding to a second index of the index vector is received from a second, different memory bank of the plurality of memory banks (paragraph 4; where scatter/gather operations allow storing/loading in/from P locations in/from P different memory banks. In these operations, a vector of P addresses is provided to the data memory, the vector being such that it contains one memory address per bank so that the memory banks can be addressed mutually independently. In combination with Karp, the received data elements are all from different locations in different memory banks and are merged into the store vector).
Karp and Panwar are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp and Panwar before the time of the effective filing of the claimed invention to incorporate the multiple memory banks of Panwar into the memory of Karp. Their motivation would have been to more efficiently access the memory.
Karp, Panwar, and Van Berkel are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, and Van Berkel before the time of the effective filing of the claimed invention to incorporate the multiple memory banks performing scatter/gather operations in parallel of Van Berkel into the memory of the combination of Karp and Panwar. Their motivation would have been to more quickly access the memory (Van Berkel, paragraph 3).
With respect to claim 2, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 3, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in the buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
transmit one or more instructions to gather the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 11, lines 16-38; as the second load vector buffer loads the data elements from the memory at addresses indexed by the elements of the first load vector buffer, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be loaded by the second load vector buffer).
With respect to claim 7, Karp teaches of wherein the buffer of the at least one controller is a first buffer, and wherein the at least one controller comprises a plurality of additional buffers configured to bin the indices of the index vector (column 11, lines 16-38; where the first load vector buffer is the claimed first buffer and the second load vector buffer gathers the discontinuous vector elements and stored them into the store vector buffer as a contiguous vector).
With respect to claim 8, Karp teaches of wherein the second vector is output to a host system coupled with the memory system (column 4, lines 19-22, column 11, lines 16-38; where the load vector buffers transfers the data to the registers of the processor).
With respect to claim 9, the combination of Karp, Panwar, and Van Berkel teaches of wherein the second vector is output to one or more banks of the plurality of memory banks (Karp, column 4, lines 19-22, column 11, lines 16-38; Panwar fig. 4; column 11, lines 32-56; where the store vector buffer transfers data back into the memory hierarchy. In the combination, the memory hierarchy includes the memory banks of Panwar).
With respect to claim 10, Karp teaches of a memory system, comprising: at least one memory device (fig. 1-2; column 3, line 63-column 4, line 8; where the computer system includes a memory hierarchy); and
at least one controller coupled with the at least one memory device (fig. 1-2; column 3, line 63-column 8, column 6, lines 48-column 7, line 19, column 9, lines 10-33; vector prefetch unit, register file controller, and memory controller),
wherein the at least one controller is configured to: obtain a first vector comprising data to be written to the at least one memory device (column 11, lines 16-38; where the mode value indicates a scatter operation and the first load buffer loads data elements of a contiguous vector);
iterate through indices of an index vector, wherein each index of the index vector corresponds to a respective location of the at least one memory device to which a respective portion of the first vector is to be written (column 11, lines 16-38; where the mode value indicates a scatter operation and the first load buffer loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer); and
write the first vector to the at least one memory device in accordance with the indices of the index vector (column 4, lines 19-23; column 11, lines 16-38; where the first load buffer loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer and the store vector buffer is used to vector transfer data back to the memory hierarchy).
Karp fails to explicitly teach of at least one memory device comprising a plurality of memory banks.
However, Panwar teaches of at least one memory device comprising a plurality of memory banks (fig. 4; column 11, lines 32-56; where action descriptor memory includes multiple memory banks).
The combination of Karp and Panwar fails to explicitly teach of wherein at least a first portion of the first vector corresponding to a first index of the index vector is written to a first memory bank of the plurality of memory banks and a second portion of the first vector corresponding to a second index of the index vector is written to a second, different memory bank of the plurality of memory banks.
However, Van Berkel teaches of wherein at least a first portion of the first vector corresponding to a first index of the index vector is written to a first memory bank of the plurality of memory banks and a second portion of the first vector corresponding to a second index of the index vector is written to a second, different memory bank of the plurality of memory banks (paragraph 4; where scatter/gather operations allow storing/loading in/from P locations in/from P different memory banks. In these operations, a vector of P addresses is provided to the data memory, the vector being such that it contains one memory address per bank so that the memory banks can be addressed mutually independently. In combination with Karp, the written data elements are all written to different locations in different memory).
Karp and Panwar are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp and Panwar before the time of the effective filing of the claimed invention to incorporate the multiple memory banks of Panwar into the memory of Karp. Their motivation would have been to more efficiently access the memory.
Karp, Panwar, and Van Berkel are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, and Van Berkel before the time of the effective filing of the claimed invention to incorporate the multiple memory banks performing scatter/gather operations in parallel of Van Berkel into the memory of the combination of Karp and Panwar. Their motivation would have been to more quickly access the memory (Van Berkel, paragraph 3).
With respect to claim 11, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 12, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in a buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the second load vector buffer is an index vector and the first load vector loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer); and
transmit one or more instructions to scatter the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 4, lines 19-23; column 11, lines 16-38; as the store vector buffer stores the data elements of a contiguous vector in the first load buffer and the store vector buffer transfers data back to the memory hierarchy, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be stored back into the memory hierarchy including Panwar’s memory banks).
With respect to claim 15, Karp teaches of wherein the buffer of the at least one controller is a first buffer, and wherein the at least one controller comprises a plurality of additional buffers configured to bin the indices of the index vector (column 11, lines 16-38; where the second load vector buffer is the claimed first buffer and the first load vector loads data elements of a contiguous vector which are then stored by the store vector buffer at addresses indexed by the data elements of the second load vector buffer).
Claim(s) 4, 13, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp, Panwar, Van Berkel and Walker (US 2010/0312990).
With respect to claim 4, the combination of Karp, Panwar, and Van Berkel fails to explicitly teach of herein each bank of the plurality of memory banks is coupled with a compute component.
However, Walker teaches of herein each bank of the plurality of memory banks is coupled with a compute component (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
The combination of Karp, Panwar, Van Berkel and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from a corresponding memory bank of the plurality of memory banks in response to the one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar); and
output the respective portions of the first vector to the at least one controller in response to the obtaining, wherein merging the respective portions of the first vector is in accordance with the output of the respective portions of the first vector (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar and provides them to the second load vector buffer of Karp).
Karp, Panwar, Van Berkel and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Van Berkel and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp, Panwar, and Van Berkel. Their motivation would have been to more quickly process operations.
With respect to claim 13, the combination of Karp, Panwar and Van Berkel fails to explicitly teach of herein each bank of the plurality of memory banks is coupled with a compute component.
However, Walker teaches of herein each bank of the plurality of memory banks is coupled with a compute component (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
The combination of Karp, Panwar, Van Berkel and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from one controller in response to one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the index vector from the store vector buffer of Karp); and
write the respective portions of the first vector to a corresponding memory bank of the plurality of memory banks in response to the obtaining, wherein writing the first vector to the at least one memory device corresponds to writing, by each compute component, the respective portions of the first vector to the corresponding memory bank of the plurality of memory banks. (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker writes the data elements in the store vector buffer to the memory buffers in the memory hierarchy).
Karp, Panwar, Van Berkel and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Van Berkel and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp, Panwar, and Van Berkel. Their motivation would have been to more quickly process operations.
With respect to claim 16, the combination of Karp, Panwar, and Van Berkel teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
The combination of Karp, Panwar, and Van Berkel fails to explicitly teach of a processor in memory (PIM) device comprising: a plurality of memory banks each coupled with a compute component; and at least one controller coupled with the PIM device.
However, Walker teaches of a processor in memory (PIM) device comprising: a plurality of memory banks each coupled with a compute component; and at least one controller coupled with the PIM device (fig. 2; paragraph 7, 18, 34-35; where the memory device is a PIM device and the ALUs are coupled to the memory banks in the memory array via buffer 107).
Karp, Panwar, Van Berkel and Walker are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Van Berkel and Walker before the time of the effective filing of the claimed invention to incorporate the PIM device of Walker into the memory of the combination of Karp, Panwar, and Van Berkel. Their motivation would have been to more quickly process operations.
With respect to claim 17, Panwar teaches of wherein the at least one controller is configured to: receive, from a host system coupled to the memory system, the index vector (fig. 3-4; column 8, lines 19-column 9, line 7; where the first find set bit module generates the index vector and provides it to the action module); and
store the index vector in one or more memory banks of the plurality of memory banks based at least in part on receiving the index vector from the host system (fig. 4; column 11, line 10-column 12, line 3; where the index vectors are stored in the queue for the memory bank that they address).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 18, Karp teaches of wherein the at least one controller is configured to: store the indices of the index vector in the buffer of the at least one controller, wherein iterating through the indices of the index vector is based at least in part on storing the indices of the index vector in the buffer of the at least one controller (column 11, lines 16-38; where the first load vector buffer is an index vector and the second load vector buffer loads data elements from the memory at addresses indexed by the element of the first load buffer); and
transmit one or more instructions to gather the respective portions of the first vector from the plurality of memory banks based at least in part on iterating through the indices of the index vector (column 11, lines 16-38; as the second load vector buffer loads the data elements from the memory at addresses indexed by the elements of the first load vector buffer, there must be instructions that are transmitted to the memory (Panwar’s memory banks, in the combination) for the data elements to be loaded by the second load vector buffer).
With respect to claim 19, the combination of Karp, Panwar, Van Berkel and Walker teaches of wherein each compute component is configured to: obtain the respective portions of the first vector from a corresponding memory bank of the plurality of memory banks in response to the one or more instructions (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar); and
output the respective portions of the first vector to the at least one controller in response to the obtaining, wherein merging the respective portions of the first vector is in accordance with the output of the respective portions of the first vector (Karp, column 11, lines 16-38; Walker, fig. 2; paragraph 7, 18, 34-35; Panwar, fig. 4; column 11, line 10-column 12, line 3; where in the combination the ALU of Walker obtains the data addressed by the index vector from the memory banks in the arrays of Panwar and provides them to the second load vector buffer of Karp).
The reasoning for obviousness is the same as indicated above with respect to claims 1 and 16.
Claim 5, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable Karp, Panwar, Van Berkel and Walker as applied to claim 4, 13, and 19 above and in further view of Shin et al. (US 2002/0157054).
With respect to claims 5 and 20, the combination of Karp, Panwar, Van Berkel and Walker fails to explicitly teach of wherein the one or more instructions to gather the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks.
However, Shin teaches of wherein the one or more instructions to gather the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks (paragraph 154; where the access layer receives commands and data from the transport layer, directs the arbiter to connect the port to the appropriate memory bank, and transmits commands and data to the memory bank. In the combination, the commands are the gather commands of Karp (column 4, lines 19-23; column 11, lines 16-38)).
Karp, Panwar, Van Berkel, Walker, and Shin are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Van Berkel, Walker, and Shin at the time of the effective filing of the invention to incorporate the arbiter directing commands to the appropriate memory bank into the combination of Karp, Panwar, Van Berkel and Walker. Their motivation would have been to more efficiently access the memory.
With respect to claim 14, Shin teaches of wherein the one or more instructions to scatter the respective portions of the first vector are transmitted to a bank arbiter associated with the plurality of memory banks and forwarded from the bank arbiter to a one or more banks of the plurality of memory banks (paragraph 154; where the access layer receives commands and data from the transport layer, directs the arbiter to connect the port to the appropriate memory bank, and transmits commands and data to the memory bank. In the combination, the commands are the scatter commands of Karp (column 4, lines 19-23; column 11, lines 16-38)).
The reasoning for obviousness is the same as indicated above with respect to claim 5.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable Karp, Panwar, Van Berkel and Walker as applied to claim 4 and in further view of Borchers et al. (US 2010/0262767).
The combination of Karp, Panwar, Van Berkel and Walker fails to explicitly teach of wherein the respective portions of the first vector are output from each bank of the plurality of memory banks via an out-of-band (OOB) bus.
However, Borchers teaches of wherein the respective portions of the first vector are output from each bank of the plurality of memory banks via an out-of-band (OOB) bus (fig. 5; paragraph 6, 13, 16, 74-77).
Karp, Panwar, Van Berkel, Walker, and Borchers are analogous art because they are from the same field of endeavor, as they are directed to memory access.
It would have been obvious to one of ordinary skill in the art having the teachings of Karp, Panwar, Van Berkel, Walker, and Borchers at the time of the effective filing of the invention to incorporate the out of band bus of Borchers into the combination of Karp, Panwar, Van Berkel and Walker. Their motivation would have been to enable execution of commands while minimizing processing impact and overhead (Borchers, paragraph 5).
Response to Arguments
Applicant's arguments with respect to independent claims 1, 10, and 16 have been considered but are moot because of the new reference(s) being applied, in light of the amendment, to the particular limitations the arguments are referencing. Thereby the arguments no longer apply to the rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Reid (US 2013/0080737) discloses performing scatter/gather operations where a vector of addresses is provided to the data memory, the vector being such that it contains one memory address per bank so that the memory banks can be addressed mutually independently.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
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