DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8-11 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al (US 2019/0273491) in view of Chung (KR 20230103987) and Penzo et al (US 10,536,070).
For claim 1, Hu teaches a dynamic two-step gate driver circuit (Figure 10), comprising:
a power device (10) functioning as a high-speed switching component and having a gate terminal (G), a source terminal (S), and a drain terminal (D);
a driver (110) configured to generate a gate drive signal (SC) and transmit it to control a switching process of the power device (as understood by examination of Figure 10) and having a gate turn- on terminal (bottom terminal of S1) and a gate turn-off terminal (top terminal of S2);
a first gate turn-on resistor (R1) electrically connected between the gate turn-on terminal of the driver and the gate terminal of the power device (as understood by examination of Figure 10);
a gate turn-off resistor (R2) electrically connected between the gate turn-off terminal of the driver and the gate terminal of the power device (as understood by examination of Figure 10);
Hu fails to teach:
the driver is an integrated circuit; and
a gate protection sub-circuit electrically connected between the first gate turn-on resistor and the gate terminal of the power device, wherein the gate protection sub-circuit comprises a diode and a second gate turn-on resistor for controlling a gate voltage of the power device during a turn-on process, and wherein the diode has an anode electrically connected to the first gate turn-on resistor and a cathode electrically connected to the gate terminal of the power device and is connected in parallel with the second gate turn-on resistor.
It is noted that Hu’s transistor 10 is a GaN FET [95].
However, Chung teaches in Figures 1 and 3 replacing a single resistor between a gate driver and the gate of a GaN HEMT (Figure 1) with two diodes (D1, D2) and two resistors (both instances of R2) in order to provide optimal switching characteristics (Abstract).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to replace Hu’s resistor R2 with the two-diode, two-resistor arrangement taught by Chung in order to improve switching characteristics.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Hu and Chung as cited above teaches:
a first gate turn-on resistor (R1, Hu) electrically connected between the gate turn-on terminal of the driver and the gate terminal of the power device (as understood by the combination of references);
a gate turn-off resistor (the R2 to the right of D1, Chung) electrically connected between the gate turn-off terminal of the driver and the gate terminal of the power device (as understood by the combination of references);
a gate protection sub-circuit (D1, D2 and the R2 in parallel with the combination of D1, D2 and the gate turn-off resistor, Chung) electrically connected between the first gate turn-on resistor and the gate terminal of the power device (as understood by the combination of references), wherein the gate protection sub-circuit comprises a diode (D2) and a second gate turn-on resistor (R2 in parallel with the combination of D1, D2 and the gate turn-off resistor) for controlling a gate voltage of the power device during a turn-on process (as understood by the combination of references as cited above), and wherein the diode has an anode electrically connected to the first gate turn-on resistor (as understood by the combination of references as cited above) and a cathode electrically connected to the gate terminal of the power device and is connected in parallel with the second gate turn-on resistor (as understood by the combination of references as cited above).
The combination of Hu and Chung fails to teach:
the driver is an integrated circuit.
However, Penzo teaches a driver for a GaN transistor (Figure 1) wherein the system including the driver can be implemented as “a single or multiple integrated circuit packages” (col. 3, lines 29-40).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the combination of Hu and Chung as an integrated circuit for the advantage of its small size when compared to other implementations.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Penzo.
For claim 2, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 1 and Hu further teaches:
the power device has a configuration established by a GaN enhancement-mode high-electron- mobility transistor (HEMT), established by a GaN/SiC cascode power device, or established by using one or more GaN HEMTs and one or more GaN/SiC cascode power devices (as understood by examination of Hu’s Figure 10).
For claims 3-6, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 1 but fails to teach the specific component values for each element in the combination circuit.
However, any person having ordinary skill in the art who knows that the such relationships can be easily set by selecting specific values for the resistances, diode voltage ratings and diode current ratings because creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also that the Aller holding is consistent with the Supreme Court decision in KSR International v. Teleflex, Inc., 82 USPQ2d 1385 (2007) which also discussed the obviousness of "design optimization" where a reference is silent on such optimized values.
Note MPEP 2144.05-II-A and 2144.05-III-A which state:
In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Applicants can rebut a prima facie case of obviousness by showing the criticality of the range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims… In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)…
… In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946) (“Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies.”)
For claim 8, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 1 and Hu further teaches:
the diode is implemented using a plurality of sub-diodes connected in series (D1, D2), and a second gate turn-on resistor is connected in parallel with the sub-diodes (as understood by the combination of references as cited above).
For claims 9-10, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 8 but fails to teach whether the sub-diodes are identical or whether forward voltage drops increase or decrease sequentially.
However, any person having ordinary skill in the art who knows that the such relationships can be easily set by selecting specific values for the diodes since creating the claimed relationships would only involve routine "design optimization", which has been held to be within the ordinary capabilities of a person having ordinary skill in the art. Applicant should note In re Aller, 105 USPQ 233 (1955) where it was held that optimizing particular values is obvious to a person of ordinary skill in the art (who would easily be able to set different values within the range of possible values in order to arrive at the best value by simple experimentation). Note also that the Aller holding is consistent with the Supreme Court decision in KSR International v. Teleflex, Inc., 82 USPQ2d 1385 (2007) which also discussed the obviousness of "design optimization" where a reference is silent on such optimized values.
Note MPEP 2144.05-II-A and 2144.05-III-A which state:
In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Applicants can rebut a prima facie case of obviousness by showing the criticality of the range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims… In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)…
… In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946) (“Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies.”)
For claim 11, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 1 and Penzo further teaches:
the diode, the second gate turn-on resistor, and the power device collectively form a monolithically integration structure (see rejection of claim 1 above).
For claim 17, Hu teaches a dynamic two-step gate driver circuit (Figure 10), comprising:
a power device (10) functioning as a high-speed switching component and having a gate terminal (G), a source terminal (S), and a drain terminal (D);
a driver (110) configured to generate a gate drive signal (SC) and transmit it to control a switching process of the power device (as understood by examination of Figure 10) and having a gate turn- on terminal (bottom terminal of S1) and a gate turn-off terminal (top terminal of S2);
a first gate turn-on resistor (R2) electrically connected between the gate turn-on terminal of the driver IC and the gate terminal of the power device (as understood by examination of Figure 10);
a gate turn-off resistor (R1) electrically connected between the gate turn-off terminal of the driver IC and the gate terminal of the power device.
Hu fails to teach:
the driver is an integrated circuit; and
a gate protection sub-circuit electrically connected between the gate turn-on terminal of the driver IC and the first gate turn-on resistor, wherein the gate protection sub-circuit comprises a diode and a second gate turn-on resistor for controlling a gate voltage of the power device during a turn-on process, and wherein the diode has an anode electrically connected to the gate turn-on terminal of the driver IC and a cathode electrically connected to the first gate turn-on resistor, and the diode is connected in parallel with the second gate turn-on resistor.
It is noted that Hu’s transistor 10 is a GaN FET [95].
However, Chung teaches in Figures 1 and 3 replacing a single resistor between a gate driver and the gate of a GaN HEMT (Figure 1) with two diodes (D1, D2) and two resistors (both instances of R2) in order to provide optimal switching characteristics (Abstract).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to replace Hu’s resistor R2 with the two-diode, two-resistor arrangement taught by Chung in order to improve switching characteristics.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
The combination of Hu and Chung as cited above teaches:
a first gate turn-on resistor (R2 to the right of D1, Chung) electrically connected between the gate turn-on terminal of the driver IC and the gate terminal of the power device (as understood by the combination of references as cited above);
a gate turn-off resistor (R1, Hu) electrically connected between the gate turn-off terminal of the driver IC and the gate terminal of the power device (as understood by the combination of references as cited above); and
a gate protection sub-circuit (D1, D2 and the R2 in parallel to D1 and D2, Chung) electrically connected between the gate turn-on terminal of the driver IC and the first gate turn-on resistor (as understood by the combination of references as cited above), wherein the gate protection sub-circuit comprises a diode (D2) and a second gate turn-on resistor (R2 in parallel with D1 and D2) for controlling a gate voltage of the power device during a turn-on process (as understood by the combination of references as cited above), and wherein the diode has an anode electrically connected to the gate turn-on terminal of the driver IC and a cathode electrically connected to the first gate turn-on resistor (as understood by the combination of references as cited above), and the diode is connected in parallel with the second gate turn-on resistor (as understood by the combination of references as cited above).
The combination of Hu and Chung fails to teach:
the driver is an integrated circuit.
However, Penzo teaches a driver for a GaN transistor (Figure 1) wherein the system including the driver can be implemented as “a single or multiple integrated circuit packages” (col. 3, lines 29-40).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to implement the combination of Hu and Chung as an integrated circuit for the advantage of its small size when compared to other implementations.
Furthermore, the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art, as evidenced by Penzo.
For claim 18, the combination of Hu, Chung and Penzo as cited above teaches the limitations of claim 17 and Hu further teaches:
the diode, the second gate turn-on resistor, and the driver IC collectively form a monolithically integration structure with a shared substrate (single integrated circuit package, Penzo).
Allowable Subject Matter
Claims 7 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Specifically, the circuit arrangement across the claimed layers are not anticipated in view of the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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