DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ORIMO (US 2019/0318874).
Regarding claim 1, ORIMO discloses a multilayer ceramic electronic component (Fig. 1-12) comprising: a multilayer body (Fig. 1, 11) including a plurality of stacked ceramic layers (Fig. 3, 110), a first main surface (Fig. 1, top) and a second main surface (Fig. 1, bottom) facing each other in a height direction (Fig. 1, T), a first end surface and a second end surface (Fig. 1, front and back ) facing each other in a length direction (Fig. 1, L) orthogonal or substantially orthogonal to the height direction (Fig. 1), and a first side surface and a second side surface (Fig. 1, left and right) facing each other in a width direction (Fig. 1, W) orthogonal or substantially orthogonal to the height direction and the length direction (Fig. 1); a plurality of first inner electrode layers (Fig. 3, 111-113a) on the plurality of ceramic layers and extending to the first end surface (Fig. 3); a plurality of second inner electrode layers (Fig. 3, 111-113b) on the plurality of ceramic layers and extending to the second end surface (Fig. 3); a first outer electrode (Fig. 3, 12a) on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the first inner electrode layers (Fig. 3); and a second outer electrode (Fig. 3, 12b) on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the second inner electrode layers (Fig. 3); wherein the first outer electrode includes a first base electrode layer (Fig. 3, 121a) on the multilayer body, a first lower plating layer (Fig. 3, 123a) on the first base electrode layer, and a first upper plating layer (Fig. 3, 124a) on the first lower plating layer except for a first plating exposed region (Fig. 3, 13a) exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region (Fig. 3); and the second outer electrode includes a second base electrode layer (Fig. 3, 121b) on the multilayer body, a second lower plating layer (Fig. 3, 123b) on the second base electrode layer, and a second upper plating layer (Fig. 3, 124b) on the second lower plating layer except for a second plating exposed region (Fig. 3, 13b) exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region (Fig. 3).
Regarding claim 5, ORIMO further discloses that a first ratio of an area of the first plating exposed region to an area of an exposed region of the first outer electrode on the first main surface when viewed in a direction of the first main surface is about 0.4% or more and about 83.4% or less (1-12% [0059]); and a second ratio of an area of the second plating exposed region to an area of an exposed region of the second outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 6, ORIMO further discloses that the first ratio and the second ratio are about 1.17% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 7, ORIMO further discloses that the first ratio and the second ratio are about 1.40% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 8, ORIMO further discloses that the first ratio and the second ratio are about 1.40% or more and about 25.0% or less (1-12% [0059]).
Regarding claim 10, ORIMO further discloses that a thickness of the first lower plating layer is about 2 µm or more and about 7 µm or less (3 µm [0117]).
Claim(s) 1, 9, 16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HATANAKA et al (US 2017/0330689).
Regarding claim 1, HATANAKA discloses a multilayer ceramic electronic component (Fig. 1-5) comprising: a multilayer body (Fig. 1, 1) including a plurality of stacked ceramic layers (Fig. 1, 1), a first main surface (Fig. 1, 1b) and a second main surface (Fig. 1, 1a) facing each other in a height direction (Fig. 1, Z), a first end surface and a second end surface (Fig. 1, 1c/1d ) facing each other in a length direction (Fig. 1, X) orthogonal or substantially orthogonal to the height direction (Fig. 1), and a first side surface and a second side surface (Fig. 1, 1e/1f) facing each other in a width direction (Fig. 1, Y) orthogonal or substantially orthogonal to the height direction and the length direction (Fig. 1); a plurality of first inner electrode layers (Fig. 1, 2a) on the plurality of ceramic layers and extending to the first end surface (Fig. 1); a plurality of second inner electrode layers (Fig. 1, 2b) on the plurality of ceramic layers and extending to the second end surface (Fig. 1); a first outer electrode (Fig. 1, 3a) on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the first inner electrode layers (Fig. 1); and a second outer electrode (Fig. 1, 3b) on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the second inner electrode layers (Fig. 1); wherein the first outer electrode includes a first base electrode layer (Fig. 3, 4) on the multilayer body, a first lower plating layer (Fig. 3, 5c) on the first base electrode layer, and a first upper plating layer (Fig. 3, 5b) on the first lower plating layer except for a first plating exposed region (Fig. 3, 13a) exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region (Fig. 3, at 6a); and the second outer electrode includes a second base electrode layer (Fig. 3, 4) on the multilayer body, a second lower plating layer (Fig. 3, 5c) on the second base electrode layer, and a second upper plating layer (Fig. 3, 5b) on the second lower plating layer except for a second plating exposed region (Fig. 3, 6a) exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region (Fig. 3).
Regarding claim 9, HATANAKA further discloses that the first plating exposed region is on the first main surface (Fig. 2, exposed portion on top).
Regarding claim 16, HATANAKA further discloses that a portion of the first base electrode layer is exposed on the first main surface (Fig. 2, exposed portion on top).
Regarding claim 18, HATANAKA discloses a mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to Claim 1 (as shown above); and a mounting substrate (Fig. 4, 9) on which the multilayer ceramic electronic component is mounted (Fig. 4); wherein the first plating exposed region is provided on the first main surface (Fig. 4), and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate (Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 11-14, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over ORIMO (US 2019/0318874) in view of MAKINO et al (US 2017/0271083).
Regarding claim 2, ORIMO teaches a multilayer ceramic electronic component (Fig. 1-12) comprising: a multilayer body (Fig. 1, 11) including a plurality of stacked ceramic layers (Fig. 3, 110), a first main surface (Fig. 1, top) and a second main surface (Fig. 1, bottom) facing each other in a height direction (Fig. 1, T), a first end surface and a second end surface (Fig. 1, front and back ) facing each other in a length direction (Fig. 1, L) orthogonal or substantially orthogonal to the height direction (Fig. 1), and a first side surface and a second side surface (Fig. 1, left and right) facing each other in a width direction (Fig. 1, W) orthogonal or substantially orthogonal to the height direction and the length direction (Fig. 1); a plurality of first inner electrode layers (Fig. 3, 111-113a) on the plurality of ceramic layers and extending to the first end surface (Fig. 3); a plurality of second inner electrode layers (Fig. 3, 111-113b) on the plurality of ceramic layers and extending to the second end surface (Fig. 3); a first outer electrode (Fig. 3, 12a) on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the first inner electrode layers (Fig. 3); and a second outer electrode (Fig. 3, 12b) on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the second inner electrode layers (Fig. 3); wherein the first outer electrode includes a first base electrode layer (Fig. 3, 121a) on the multilayer body, a first lower plating layer (Fig. 3, 123a) on the first base electrode layer, and a first upper plating layer (Fig. 3, 124a) on the first lower plating layer except for a first plating exposed region (Fig. 3, 13a) exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region (Fig. 3); and the second outer electrode includes a second base electrode layer (Fig. 3, 121b) on the multilayer body, a second lower plating layer (Fig. 3, 123b) on the second base electrode layer, and a second upper plating layer (Fig. 3, 124b) on the second lower plating layer except for a second plating exposed region (Fig. 3, 13b) exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region (Fig. 3).
However, ORIMO fails to teach that the capacitor is configured to have a four external electrode configuration so that the first and second outer electrodes contact a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface and a third and fourth outer electrode contact a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface.
MAKINO teaches a capacitor (Fig. 5-7) is configured to have a four external electrode configuration (Fig. 5, 110/120/210/220) so that the first and second outer electrodes contact a plurality of first inner electrode layers (Fig. 6B, 335) on the plurality of ceramic layers and extending to the first end surface and the second end surface (Fig. 6) and a third and fourth outer electrode contact a plurality of second inner electrode layers (Fig. 6B, 336) on the plurality of ceramic layers and extending to the first side surface and the second side surface (Fig. 6).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of MAKINO to the invention of ORIMO, in order to construct the devices using known specifications and designs in the art to meet user needs based on known design possibilities as four terminal multilayer capacitors are well known in the art.
Regarding claim 3, ORIMO, as modified by MAKINO, further teach that the third upper plating layer is provided on the third lower plating layer except for a third plating exposed region exposed on a surface of the third outer electrode so that the third lower plating layer includes the third plating exposed region (Fig. 3, external electrode configuration of ORIMO would be the same for all external electrodes); and the fourth upper plating layer is provided on the fourth lower plating layer except for a fourth plating exposed region exposed on a surface of the fourth outer electrode so that the fourth lower plating layer has the fourth plating exposed region (Fig. 3, external electrode configuration of ORIMO would be the same for all external electrodes).
Regarding claim 17, ORIMO, as modified by MAKINO, further teach that at least one of a third ratio of an area of the third plating exposed region to an area of an exposed region of the third outer electrode on the first main surface when viewed in a direction of the first main surface and a fourth ratio of an area of the fourth plating exposed region to an area of an exposed region of the fourth outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 11, ORIMO, as modified by MAKINO, further teach that a first ratio of an area of the first plating exposed region to an area of an exposed region of the first outer electrode on the first main surface when viewed in a direction of the first main surface is about 0.4% or more and about 83.4% or less (1-12% [0059]); and a second ratio of an area of the second plating exposed region to an area of an exposed region of the second outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 12, ORIMO, as modified by MAKINO, further teach that the first ratio and the second ratio are about 1.17% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 13, ORIMO, as modified by MAKINO, further teach that the first ratio and the second ratio are about 1.40% or more and about 83.4% or less (1-12% [0059]).
Regarding claim 14, ORIMO, as modified by MAKINO, further teach that the first ratio and the second ratio are about 1.40% or more and about 25.0% or less (1-12% [0059]).
Claim(s) 2, 4, 15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over HATANAKA et al (US 2017/0330689) in view of MAKINO et al (US 2017/0271083)
Regarding claim 2, HATANAKA teaches a multilayer ceramic electronic component (Fig. 1-5) comprising: a multilayer body (Fig. 1, 1) including a plurality of stacked ceramic layers (Fig. 1, 1), a first main surface (Fig. 1, 1b) and a second main surface (Fig. 1, 1a) facing each other in a height direction (Fig. 1, Z), a first end surface and a second end surface (Fig. 1, 1c/1d ) facing each other in a length direction (Fig. 1, X) orthogonal or substantially orthogonal to the height direction (Fig. 1), and a first side surface and a second side surface (Fig. 1, 1e/1f) facing each other in a width direction (Fig. 1, Y) orthogonal or substantially orthogonal to the height direction and the length direction (Fig. 1); a plurality of first inner electrode layers (Fig. 1, 2a) on the plurality of ceramic layers and extending to the first end surface (Fig. 1); a plurality of second inner electrode layers (Fig. 1, 2b) on the plurality of ceramic layers and extending to the second end surface (Fig. 1); a first outer electrode (Fig. 1, 3a) on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the first inner electrode layers (Fig. 1); and a second outer electrode (Fig. 1, 3b) on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the second inner electrode layers (Fig. 1); wherein the first outer electrode includes a first base electrode layer (Fig. 3, 4) on the multilayer body, a first lower plating layer (Fig. 3, 5c) on the first base electrode layer, and a first upper plating layer (Fig. 3, 5b) on the first lower plating layer except for a first plating exposed region (Fig. 3, 13a) exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region (Fig. 3, at 6a); and the second outer electrode includes a second base electrode layer (Fig. 3, 4) on the multilayer body, a second lower plating layer (Fig. 3, 5c) on the second base electrode layer, and a second upper plating layer (Fig. 3, 5b) on the second lower plating layer except for a second plating exposed region (Fig. 3, 6a) exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region (Fig. 3).
However, HATANAKA fails to teach that the capacitor is configured to have a four external electrode configuration so that the first and second outer electrodes contact a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface and a third and fourth outer electrode contact a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface.
MAKINO teaches a capacitor (Fig. 5-7) is configured to have a four external electrode configuration (Fig. 5, 110/120/210/220) so that the first and second outer electrodes contact a plurality of first inner electrode layers (Fig. 6B, 335) on the plurality of ceramic layers and extending to the first end surface and the second end surface (Fig. 6) and a third and fourth outer electrode contact a plurality of second inner electrode layers (Fig. 6B, 336) on the plurality of ceramic layers and extending to the first side surface and the second side surface (Fig. 6).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of MAKINO to the invention of HATANAKA, in order to construct the devices using known specifications and designs in the art to meet user needs based on known design possibilities as four terminal multilayer capacitors are well known in the art.
Regarding claim 15, HATANAKA, as modified by MAKINO, further teaches that the first plating exposed region is on the first main surface (Fig. 2, exposed portion on top).
Regarding claim 19, HATANAKA, as modified by MAKINO, further teaches a mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to Claim 2 (as shown above); and a mounting substrate (Fig. 4, 9) on which the multilayer ceramic electronic component is mounted (Fig. 4); wherein a positive potential is applied to the first outer electrode and the second outer electrode (Fig. 2, exposed portion on top).
Regarding claim 4, HATANAKA teaches a multilayer ceramic electronic component (Fig. 1-5) comprising: a multilayer body (Fig. 1, 1) including a plurality of stacked ceramic layers (Fig. 1, 1), a first main surface (Fig. 1, 1b) and a second main surface (Fig. 1, 1a) facing each other in a height direction (Fig. 1, Z), a first end surface and a second end surface (Fig. 1, 1c/1d ) facing each other in a length direction (Fig. 1, X) orthogonal or substantially orthogonal to the height direction (Fig. 1), and a first side surface and a second side surface (Fig. 1, 1e/1f) facing each other in a width direction (Fig. 1, Y) orthogonal or substantially orthogonal to the height direction and the length direction (Fig. 1); a plurality of first inner electrode layers (Fig. 1, 2a) on the plurality of ceramic layers and extending to the first end surface (Fig. 1); a plurality of second inner electrode layers (Fig. 1, 2b) on the plurality of ceramic layers and extending to the second end surface (Fig. 1); a first outer electrode (Fig. 1, 3a) on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the first inner electrode layers (Fig. 1); and a second outer electrode (Fig. 1, 3b) on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface (Fig. 1), and being connected to the second inner electrode layers (Fig. 1); wherein the first outer electrode includes a first base electrode layer (Fig. 3, 4) on the multilayer body, a first lower plating layer (Fig. 3, 5c) on the first base electrode layer, and a first upper plating layer (Fig. 3, 5b) on the first lower plating layer except for a first plating exposed region (Fig. 3, 13a) exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region (Fig. 3, at 6a); and the second outer electrode includes a second base electrode layer (Fig. 3, 4) on the multilayer body, a second lower plating layer (Fig. 3, 5c) on the second base electrode layer, and a second upper plating layer (Fig. 3, 5b) on the second lower plating layer except for a second plating exposed region (Fig. 3, 6a) exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region (Fig. 3).
However, HATANAKA fails to teach that the capacitor is configured to have a four external electrode configuration so that the first and second outer electrodes contact a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface and a third and fourth outer electrode contact a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface.
MAKINO teaches a capacitor (Fig. 5-7) is configured to have a four external electrode configuration (Fig. 5, 110/120/210/220) so that the first and second outer electrodes contact a plurality of first inner electrode layers (Fig. 6B, 335) on the plurality of ceramic layers and extending to the first end surface and the second end surface (Fig. 6) and a third and fourth outer electrode contact a plurality of second inner electrode layers (Fig. 6B, 336) on the plurality of ceramic layers and extending to the first side surface and the second side surface (Fig. 6), and because all electrodes of NATANAKA would have the same configuration the third and fourth outer electrodes would have the exposed region similar to the first and second outer electrodes when combined.
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of MAKINO to the invention of HATANAKA, in order to construct the devices using known specifications and designs in the art to meet user needs based on known design possibilities as four terminal multilayer capacitors are well known in the art.
Regarding claim 20, HATANAKA, as modified by MAKINO, further teaches a mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to Claim 4 (as shown above); and a mounting substrate (Fig. 4, 9) on which the multilayer ceramic electronic component is mounted (Fig. 4); wherein a positive potential is applied to the first outer electrode and the second outer electrode (Fig. 2, exposed portion on top).
Additional Relevant Prior Art:
MASUNARI (US 2017/0256359) teaches relevant art in Fig. 12-14.
WOO et al (US 2018/0332715) teaches relevant art in Fig. 1-9.
Park et al (US 2022/0037089) teaches relevant art in Fig. 1-11.
Chen et al (US 11917761) teaches relevant art in Fig. 1-5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
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