Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 and 3-5 are currently pending in the present application.
Claims 1 and 3 are currently amended; claim 2 has been canceled by the applicant; and claims 4-5 are original.
Response to Amendment
The amendment dated 31 July 2026 has been entered into the record.
Response to Arguments
Applicant argues that with respect to claim 1, as currently amended to include the limitations of now-canceled claim 2, prior art reference of record Son fails to disclose the claim limitation that a through hole is formed on the common metal interconnection in a region in which the signal line crosses the scanning line. This argument is not persuasive. Referring to Figure 1 of Son, common metal interconnection 270 not only extends in the aperture of the depicted pixel but also extends into the region covered by light block 220. Figure 2 of Son depicts the view identified as II-II from Figure 1. From Figure 2 of Son, the common metal interconnection 270 has a hole in it that goes completely through the layer in its entirety. Figure 2 also shows that the through hole in common metal interconnection 270 is disposed over the drain portion 175 of the depicted transistor 175, 173, 124, 151, 154. This same transistor is depicted in Figure 1 as being located in the non-display region of the pixel. The non-display region of the pixel in is covered in its entirety by light block 220 so that various transistor connections and wiring is not visible to a viewer of the displayed image. Figure 1 of Son further discloses that areas where the data line 171 and the gate line 121 intersect are also located in the non-display region of the pixel that is covered by light block 221. Given that the common metal interconnect 270 is located in the non-display region of the pixel and that both instances of the gate line 121 intersecting with a data line 171 are located in the non-display region of the pixel, Son does in fact disclose the claim limitation that a through hole formed on the common metal interconnection 270 is in a region (the non-display region of the pixel depicted in Figures 1 & 2 that is covered by light block 220) in which the signal line 171 crosses the scanning line 121.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (KR 102168874; citations made to attached English translation), of record, in view of Son (US 20150062521), of record.
Re: claim 1, Choi discloses pixel electrodes 130 (Fig. 1); a common electrode 140 (Fig. 1); a capacitive insulating film 135 between the pixel electrodes and the common electrode (position between disclosed in Fig. 1); a scanning line GL extending in a first direction (Fig. 8a discloses gate line extending in a horizontal direction; see also para. 30); a signal line DL extending in a second direction intersecting the first direction (Fig. 8a discloses data line extending in a vertical direction that intersects the horizontal direction; para. 30 discloses intersection); a common metal interconnection 215 (para. 29 discloses opaque conductive material) covering the scanning line and the signal line (para. 34 “The black matrix (215) is formed to correspond to gate wiring, data wiring…”); a slit formed on the common electrode at the portion corresponding to the pixel electrodes (slits in CE 140 corresponding to PE 130 disclosed in Fig. 1); and the slit is present on both sides of the common electrode (slits on both sides of CEs 140 disclosed in Fig. 1), wherein the common electrode 140 covers the common metal interconnection 215 (covering by overlapping disclosed in Fig. 1),
Choi does not explicitly disclose an alignment film covering the common electrode and a through hole being formed on the common metal interconnection in a region in which the signal line crosses the scanning line.
Son discloses an alignment film covering the common electrode 260 (para. 86 discloses alignment layer being coated onto PE 191, where Fig. 2 further discloses that the alignment layer covers both PE 191 and CE 260), and a through hole (Fig. 2, the hole in element 270 that is filled with element 326) formed on the common metal interconnection 270 in a region in which the signal line 171 crosses the scanning line 121 (disposition in region of crossing of scan and signal lines disclosed in Figs. 1, 2).
It would have been obvious to a person of ordinary skill in the art at a time before the effective filing date of the claimed invention to have an alignment film covering the common electrode and to have a through hole be formed on the common metal interconnection in a region in which the signal line crosses the scanning line, as disclosed by Son, applied to the device disclosed by Choi for the purposes of providing liquid crystal molecules disclosed in proximity to the alignment film a pre-tilt so that the switching speed of the molecules is increased and of connecting conductors while optimizing the aperture size of a pixel by having the connection performed in a light shielded region.
Re: claim 3, Choi and Son disclose the limitations of claim 2, and Son further discloses a spacer 325, 326 disposed in the through hole (disposition disclosed in Fig. 2).
It would have been obvious to a person of ordinary skill in the art at a time before the effective filing date of the claimed invention to have a spacer disposed in the through hole, as disclosed by Son, as applied to the device disclosed by Choi for the purpose of preventing the alignment layer from being scratched if the array and/or opposite substrates come into physical contact while optimizing the aperture size of the pixel by having the spacer disposed in a light shielded region.
Re: claim 4, Choi and Son disclose the limitations of claim 1, and Choi further discloses that the signal line DL is present between the pixel electrodes 130 (disposition between disclosed in Fig. 1 when viewing in plan view).
Re: claim 5, Choi and Son discloses the limitations of claim 1, and Choi further discloses that the capacitive insulating film 135 is formed to cover the pixel electrode 130 (coverage disclosed in Fig. 1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELA MEDICH whose telephone number is (313)446-4819. The examiner can normally be reached M-T & Th-F 10:00 AM - 7:00 PM ET.
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/ANGELA M. MEDICH/ Primary Examiner, Art Unit 2871