DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priorities
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0027379, filed on 02/26/2024.
Information Disclosure Statement
The information disclosure statements filed 01/15/2025 has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. (US Pub. 2020/0286972 A1).
Regarding claim 1; Seo teaches a display device (a display device 1, Figs. 1 and 3), comprising:
PNG
media_image1.png
506
474
media_image1.png
Greyscale
(Fig.3 of Seo reproduced)
a display panel (a display panel 10, Fig.3) including an active area (a display area DA) in which one or more optical areas are disposed (the display area DA includes a sensor area SA in which one or more sensors are disposed, para. [0169]); and
one or more sensor modules overlapped with the one or more optical areas (para. [0067-0068]), wherein the one or more optical areas are divided into a pixel area in which a plurality of pixels is disposed (Fig.3; para. [0044], the sensor area SA comprises a plurality of auxiliary sub-pixels Pa) and a transmissive area (a transmissive area TA; Fig.3) through which light of the one or more sensor modules is to pass (para. [0043]), and
wherein among a plurality of constant power lines (Fig.6, para. [0081], a plurality of driving voltage lines PL are configured to transmit a first power voltage ELVDD to a plurality of pixel circuits) configured to apply at least one constant power to the plurality of pixels disposed in the pixel area (para. [0081 and 0113], the driving voltage lines PL provide constant voltage (e.g., +5V) to a plurality of pixels), adjacent constant power lines are connected to each other (Fig.6, para. [0114], a plurality of electrode voltage lines HL are electrically connected to the driving voltage lines PL to form a mesh structure in the display area. In other words, adjacent driving voltage lines PL would be connected together by the electrode voltage line HL).
Regarding claim 2; Seo teaches the display device of claim 1 as discussed above. Seo further teaches the plurality of constant power lines includes: a plurality of main lines (a first sub-line 162 and a second sub-line 163, Fig.3) disposed at an outside of the active area (Fig.3, the first sub-line 162 and the second sub-line 163 are disposed in a non-display area NDA); and a plurality of sub lines (Fig.3, the driving voltage lines PL) which is branched from at least one of the plurality of main lines to be connected to the plurality of pixels (Fig.3; the plurality of driving voltage lines PL are branched from the first sub-line 162 and the second sub-line 163 to be connected to the plurality of pixels Pm).
Regarding claim 3; Seo teaches the display device of claim 2 as discussed above. Seo further teaches among the plurality of sub lines, adjacent sub lines are connected by a connection line (Fig.6, para. [0114], the electrode voltage lines HL are connected to the driving voltage lines PL to form a mesh structure. In other words, two adjacent driving voltage lines PL would be connected by the electrode voltage line HL).
Regarding claim 9; Seo teaches the display device of claim 3 as discussed above. Seo further teaches the adjacent sub lines and the connection line are disposed on different layers (para. [0115], the driving voltage line PL and the electrode voltage line HL are disposed on different layers with an insulating layer interposed therebetween).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US Pub. 2020/0286972 A1) in view of Song et al. (US Pub. 2020/0058728 A1).
Regarding claim 4; Seo teaches the display device of claim 2 as discussed above. Seo further teaches the plurality of main lines includes: a first main line (a first sub-line 162, Fig.3) disposed at one side of the active area (Fig.3); and a second main line (the second sub-line 163, Fig.3) disposed at another side of the active area (Fig.3).
Seo does not teach that the plurality of sub lines includes: a plurality of first sub lines branched from the first main line; and a plurality of second sub lines branched from the second main line.
Song teaches the plurality of sub lines (Figs. 4 and 7, a plurality of driving voltage lines PL) includes: a plurality of first sub lines (Fig.4, first driving voltage lines PL1) branched from the first main line (Fig.4, the first driving voltage lines PL1 are branched from a first power supply line 160); and a plurality of second sub lines (Fig.4, a plurality of second driving voltage lines PL2) branched from the second main line (Fig.4, the second driving voltage lines PL2 are branched from a second power supply line 163. In addition, the driving voltage lines do not pass through a transmissive area TA).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Seo to include the teaching of Song of providing driving voltage lines including first driving voltage lines branched from a first power supply line and second driving voltage lines branched from a second power supply line without extending to the transmissive area. The motivation would have been in order to increase the light transmittance of the transmissive area.
Regarding claim 7; Seo in view of Song teaches the display device of claim 4 as discussed above. Seo does not teach that a first sub line, among the plurality of first sub lines, which does not extend to the transmissive area is in contact with a second sub line, among the plurality of second sub lines, which does not extend to the transmissive area.
Song teaches a first sub line (a first driving line PL2_1, Fig.7), among the plurality of first sub lines (driving voltage lines PL2_1 to PL2_7, Fig.7), which does not extend to the transmissive area (Fig.7, the first driving line PL2_1 does not extend to a transmissive area TA) is in contact with a second sub line, among the plurality of second sub lines, which does not extend to the transmissive area (Fig.7, the first driving line PL2_1 is electrically connected to a second driving line PL1_1 through a driving voltage line PL3_1 via contact holes CNT. Therefore, the first driving voltage line PL2_1 is in contact with the second driving voltage line PL1_1. In addition, the second driving voltage line PL1_1 does not extend to the transmissive area TA).
The motivation is the same as the rejection of claim 4.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US Pub. 2020/0286972 A1) in view of Choi et al. (US Pub. 2023/0200166 A1).
Regarding claim 8; Seo teaches the display device of claim 3 as discussed above. Seo does not teach that the adjacent sub lines and the connection line are disposed on a same layer.
Choi teaches the adjacent sub lines (Fig.14, main power lines 195 and 196) and the connection line (auxiliary power line 178, Fig.14) are disposed on a same layer (Fig.14, para. [0166-0167], the main power lines 195 and 196 and the auxiliary power line 178 are disposed in a same layer).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Seo to include the teaching of Choi of disposing two main power lines and an auxiliary power line in the same layer. The motivation would have been in order to reduce the resistance.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US Pub. 2020/0286972 A1) in view of Byun et al. (US Pub. 2021/0350740 A1).
Regarding claim 11; Seo teaches the display device of claim 1 as discussed above. Seo does not teach each of the plurality of pixels includes: a light emitting diode, and a pixel circuit connected to the light emitting diode, and wherein the pixel circuit includes: a driving transistor configured to supply a driving current to the light emitting diode; a bias transistor configured to apply a bias voltage to a first electrode of the driving transistor; a reset transistor configured to apply a reset voltage to an anode electrode of the light emitting diode; and an initialization transistor configured to apply an initialization voltage to a gate electrode of the driving transistor.
Byun teaches each of the plurality of pixels includes: a light emitting diode (a light emitting diode LED, Fig.2), and a pixel circuit connected to the light emitting diode (a pixel circuit as shown in Fig.2 includes the light emitting diode LED), and wherein the pixel circuit includes: a driving transistor (a driving transistor T1, Fig.2) configured to supply a driving current to the light emitting diode (para. [0090]); a bias transistor (an eighth transistor T8, Fig.2) configured to apply a bias voltage to a first electrode of the driving transistor (para. [0087], a bias voltage VEH is transmitted to a first electrode of the driving transistor T1 according to the bias control signal GB[n]); a reset transistor (a seventh transistor T7, Fig.2) configured to apply a reset voltage to an anode electrode of the light emitting diode (para. [0112], a second initialization voltage Vint2 is supplied to an anode of the light emitting diode LED during an anode reset section); and an initialization transistor (a fourth transistor T4, Fig.2) configured to apply an initialization voltage to a gate electrode of the driving transistor (para. [0085], a first initialization voltage Vint1 is transmitted to the gate electrode of the driving transistor T1 via the fourth transistor T4).
PNG
media_image2.png
454
456
media_image2.png
Greyscale
(Fig.2 of Byun reproduced)
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Seo to include the pixel circuit of Byun. The motivation would have been in order to stably display desired luminance of the pixel (Byun, para. [0047]).
Regarding claim 12; Seo in view of Byun teaches the display device of claim 11 as discussed above. Seo does not teach the at least one constant power which is to be applied to the plurality of pixels is at least one of the bias voltage, the reset voltage, and the initialization voltage.
Byun teaches the at least one constant power which is to be applied to the plurality of pixels is at least one of the bias voltage, the reset voltage, and the initialization voltage (para. [0085-0087], a constant level of voltage is applied to the initialization voltage (e.g., Vint1 and Vint2) and a bias voltage VEH).
The motivation is the same as the rejection of claim 11.
Regarding claim 13; Seo in view of Byun teaches the display device of claim 11 as discussed above. Seo does not teach a plurality of transistors included in the pixel circuit includes the driving transistor, the bias transistor, the reset transistor, and the initialization transistor, and wherein the plurality of transistors included in the pixel circuit includes both a p-type transistor and an n-type transistor.
Byun teaches a plurality of transistors included in the pixel circuit includes the driving transistor (the driving transistor T1, Fig.2), the bias transistor (the eight transistor T8), the reset transistor (the seventh transistor T7), and the initialization transistor (the fourth transistor T4), and wherein the plurality of transistors included in the pixel circuit includes both a p-type transistor and an n-type transistor (Fig.2, the driving transistor T1, the seventh transistor T7, and the eight transistor T8 are p-type transistors. The fourth transistor T4 is a n-type transistor).
The motivation is the same as the rejection of claim 11.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US Pub. 2020/0286972 A1) in view of Song et al. (US Pub. 2020/0058728 A1) as applied to claim 4 above; further in view of Bok et al. (US Pub. 2024/0184390 A1).
Regarding claim 16; Seo in view of Song teaches the display device of claim 4 as discussed above. Seo does not teach that the one or more optical areas are disposed in a center of the active area.
Bok teaches the one or more optical areas are disposed in a center of the active area (Fig.8C, para. [0257], a component area CA is located at a center of a display area DA).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Seo to include the teaching of Bok of placing a component area CA at a center of a display area. The motivation would have been in order to obtain a preferred design.
Regarding claim 17; Seo in view of Song and Bok teaches the display device of claim 16 as discussed above. Seo does not teach a length of the plurality of first sub lines is equal to a length of the plurality of second sub lines.
Bok teaches that the component area CA is located at a center of a display area (see the analysis of claim 16).
The motivation is the same as the rejection of claim 16.
Therefore, in a combination of Seo, Song, and Bok; a length of the first driving voltage line PL1 would be equal to a length of the second driving voltage line PL2 because the transmissive area TA is located at the center of the display area. Accordingly, the combination of Seo, Song, and Bok further teaches a length of the plurality of first sub lines is equal to a length of the plurality of second sub lines.
Allowable Subject Matter
Claims 5-6, 10, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach all limitations recited in claims 5, 6, 10, and 14-15.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
Prosecution Insights