DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 3 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8-11, 13, 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nitta et al. (US 9,769,411 B2)(hereinafter Nitta).
Re claim 1, Nitta discloses an imaging device comprising: a plurality of pixels each configured to output a pixel signal (see col. 6 lines 1-8 for a plurality of pixels each configured to output a pixel signal (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); a first output line and a second output line each connected to a corresponding pixel (see col. 6 lines 1-8 for a first output line and a second output line each connected to a corresponding pixel (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (see col. 6 lines 51-65 for an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)); a first memory and a second memory each configured to hold the pixel data (see col. 7 lines 36-49 for a first memory and a second memory each configured to hold the pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)); and a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (see col. 7 lines 50-55 for a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)), wherein in a first mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate first pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate second pixel data (see col. 6 lines 53-65 for in a first mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate first pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate second pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)), the first memory stores the first pixel data, the second memory stores the second pixel data (see col. 7 lines 36-49 for the first memory stores the first pixel data, the second memory stores the second pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)), and the scanning circuit causes the first memory to output the first pixel data and causes the second memory to output the second pixel data (see col. 7 lines 50-55 for the scanning circuit causes the first memory to output the first pixel data and causes the second memory to output the second pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)), and wherein in a second mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate third pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate fourth pixel data (see col. 6 lines 53-65 for in a second mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate third pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate fourth pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)), the first memory stores the third pixel data and the fourth pixel data (see col. 7 lines 36-49 for the first memory stores the third pixel data and the fourth pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)), and the scanning circuit causes the first memory to output the third pixel data and the fourth pixel data (see col. 7 lines 50-55 for the scanning circuit causes the first memory to output the third pixel data and the fourth pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62))
Re claim 5, Nitta as discussed in claim 1 above discloses all the claim limitations with additional claimed feature wherein each of the third pixel data and the fourth pixel data is 1-bit digital data (see fig. 1 col. 7 lines 50-55 for each of the third pixel data and the fourth pixel data is 1-bit digital data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m)))
Re claim 6, Nitta as discussed in claim 1 above discloses all the claim limitations with additional claimed feature wherein the analog-to-digital conversion unit includes a comparator and a counter, wherein the comparator compares a potential of the first output line or the second output line with a potential of a reference signal, and the counter outputs, to the first memory or the second memory, a signal corresponding to a time when an output signal of the comparator changes (see col. 7 lines 1-3 to lines 22-49 for the analog-to-digital conversion unit includes a comparator and a counter, wherein the comparator compares a potential of the first output line or the second output line with a potential of a reference signal, and the counter outputs, to the first memory or the second memory, a signal corresponding to a time when an output signal of the comparator changes (i.e. the comparator 31 compares the signal voltage Vx of the column signal line 22-m according to signals output from the unit pixels 11 in the m-th column of the pixel array unit 12 with the reference voltage Vref of a ramp waveform supplied from the reference-voltage supplying unit 15, for example, when the reference voltage Vref is higher than the signal voltage Vx, the output Vco is in a “H” level, when the reference voltage Vref is equal to or lower than the signal voltage Vx, the output Vco is in a “L” level, the up/down counter 32 is an asynchronous counter, the timing control circuit 18 supplies a clock CK to the up/down counter 32 and the DAC 151 at the same time under control by the control signal CS2, which is supplied from the timing control circuit 18, accordingly, the up/down counter 32 performs up/down count in synchronization with the clock CK in order to measure comparison time from the start to the end of the comparing operation in the comparator 31, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 4-21 to lines 50-55))
Re claim 8, Nitta as discussed in claim 1 above discloses all the claim limitations with additional claimed feature wherein the plurality of pixels are arranged to form a plurality of columns, wherein the first output line is connected to pixels in one of the plurality of columns, and wherein the second output line is connected to pixels in another one of the plurality of columns (see col. 6 lines 1-8 for the plurality of pixels are arranged to form a plurality of columns, wherein the first output line is connected to pixels in one of the plurality of columns, and wherein the second output line is connected to pixels in another one of the plurality of columns (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns as described in fig. 1 col. 6 lines 19-24))
Re claim 9, Nitta as discussed in claim 8 above discloses all the claim limitations with additional claimed feature wherein the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein the plurality of processing circuits are arranged so as to respectively correspond to the plurality of columns (see col. 6 lines 30-35 for the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein the plurality of processing circuits are arranged so as to respectively correspond to the plurality of columns (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as shown in fig. 1))
Re claim 10, Nitta as discussed in claim 8 above discloses all the claim limitations with additional claimed feature wherein the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein one of the plurality of processing circuits is arranged so as to correspond to two or more of the plurality of columns (see col. 6 lines 30-35 for the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein one of the plurality of processing circuits is arranged so as to correspond to two or more of the plurality of columns (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as shown in fig. 1))
Re claim 11, Nitta as discussed in claim 8 above discloses all the claim limitations with additional claimed feature further comprising a state switching unit, wherein the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein the state switching unit switches between a first state in which the plurality of processing circuits are arranged so as to respectively correspond to the plurality of columns and a second state in which one of the plurality of processing circuits is arranged so as to correspond to two or more of the plurality of columns (see col. 14 lines 36-41 for a state switching unit, wherein the analog-to-digital conversion unit includes a plurality of processing circuits each having an analog-to-digital conversion function, and wherein the state switching unit switches between a first state in which the plurality of processing circuits are arranged so as to respectively correspond to the plurality of columns and a second state in which one of the plurality of processing circuits is arranged so as to correspond to two or more of the plurality of columns (i.e. a pair of column processing units 14A and 14B, a pair of reference-voltage supplying units 15A and 15B, a pair of column scanning circuits 16A and 16B, and a pair of horizontal output lines 17A and 17B are disposed on both sides of the pixel array unit 12 in the column direction, further, selecting switches 71A and 71B are disposed between the pixel array unit 12 and the column processing units 14A and 14B, the selecting switches 71A and 71B operate in a complimentary manner so as to connect one of two adjoining column signal lines to the column processing unit 14A when the other column signal line is connected to the column processing unit 14B, and vice versa. as described in fig. 10 col. 14 lines 19-29 to lines 42-46). Also, see col. 14 lines 47-67, col. 15 lines 1-11)
Re claim 13, Nitta as discussed in claim 1 above discloses all the claim limitations with additional claimed feature wherein in the second mode, the scanning circuit causes the first memory to simultaneously output the third pixel data and the fourth pixel data (see col. 13 lines 1-43 to lines 64-67, col. 14 lines 1-3 for in the second mode, the scanning circuit causes the first memory to simultaneously output the third pixel data and the fourth pixel data (i.e. after the adding operation, the addition result is transferred to the memory device 34 in each column, and the addition results of the odd-numbered columns and the even-numbered columns are input to the digital adder 31 through the horizontal output lines 17-1 and 17-2, respectively, at this time, control signals M1, M2, M3, output from the column scanning circuit 16 are simultaneously output in pairs of M1 and M2, M3 and M4, accordingly, the digital values (addition results) held in the memory devices 34 are simultaneously output to the horizontal output line 17-1 or 17-2 in units of two columns, in the timing chart shown in FIG. 9, the addition result in the odd-numbered columns is output to signal output A and the addition result in the even-numbered columns is output to signal output B, specifically, the addition result of the pixels 11-11 and 11-21 is output as a top signal of the signal output A and the addition result of the pixels 11-12 and 11-22 is output as a top signal of the signal output B, as a result, the addition result of the four pixels 11-11, 11-12, 11-21, and 11-22 is output as the top output of the digital adder 61 as described in fig. 8 col. 13 lines 44-63))
Re claim 16, Nitta as discussed in claim 1 above discloses all the claim limitations with additional claimed feature further comprising a mode witching unit configured to switch between the first mode and the second mode by switching an output destination of a signal from the analog-to-digital conversion unit to one of the first memory and the second memory (see col. 6 lines 55-65 for a mode witching unit configured to switch between the first mode and the second mode by switching an output destination of a signal from the analog-to-digital conversion unit to one of the first memory and the second memory (i.e. each of the ADCs 23-1 to 23-m is capable of selectively performing AD conversion according to each operation mode: the operation mode is switched under control of control signals CS2 and CS3 supplied from the timing control circuit 18 as described in fig. 1 col. 6 lines 53-55 to lines 59-61, furthermore, the transfer switch 33 is turned on (closed) when the count operation of the up/down counter 32 on the unit pixel 11 of a row has been completed under control by the control signal CS3 supplied from the timing control circuit 18, and transfers the count result of the up/down counter 32 to the memory device 34 in the normal-frame-rate mode, on the other hand, in a high-frame-rate mode where N=2, the transfer switch 33 is kept in an off-state (open) when the count operation of the up/down counter 32 on the unit pixel 11 of a row is completed, then, after the count operation of the up/down counter 32 on the unit pixel 11 of the next row has been completed, the transfer switch 33 is turned on and transfers the count result of the vertical two pixels in the up/down counter 32 to the memory device 34, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 3 col. 7 lines 36-55))
Re claim 17, Nitta discloses an imaging device comprising: a plurality of pixels each configured to output a pixel signal (see col. 6 lines 1-8 for a plurality of pixels each configured to output a pixel signal (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); a first output line and a second output line each connected to a corresponding pixel (see col. 6 lines 1-8 for a first output line and a second output line each connected to a corresponding pixel (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (see col. 6 lines 51-65 for an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)); a first memory and a second memory each configured to hold the pixel data (see col. 7 lines 36-49 for a first memory and a second memory each configured to hold the pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)); a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (see col. 7 lines 50-55 for a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)); and a mode switching unit configured to switch an output destination of a signal from the analog-to-digital conversion unit to one of the first memory and the second memory (see col. 6 lines 55-65 for a mode switching unit configured to switch an output destination of a signal from the analog-to-digital conversion unit to one of the first memory and the second memory (i.e. each of the ADCs 23-1 to 23-m is capable of selectively performing AD conversion according to each operation mode: the operation mode is switched under control of control signals CS2 and CS3 supplied from the timing control circuit 18 as described in fig. 1 col. 6 lines 53-55 to lines 59-61, furthermore, the transfer switch 33 is turned on (closed) when the count operation of the up/down counter 32 on the unit pixel 11 of a row has been completed under control by the control signal CS3 supplied from the timing control circuit 18, and transfers the count result of the up/down counter 32 to the memory device 34 in the normal-frame-rate mode, on the other hand, in a high-frame-rate mode where N=2, the transfer switch 33 is kept in an off-state (open) when the count operation of the up/down counter 32 on the unit pixel 11 of a row is completed, then, after the count operation of the up/down counter 32 on the unit pixel 11 of the next row has been completed, the transfer switch 33 is turned on and transfers the count result of the vertical two pixels in the up/down counter 32 to the memory device 34, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 3 col. 7 lines 36-55))
Re claim 18, Nitta discloses equipment comprising: the imaging device according to claim 1 an imaging device comprising: a plurality of pixels each configured to output a pixel signal (see col. 6 lines 1-8 for a plurality of pixels each configured to output a pixel signal (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); a first output line and a second output line each connected to a corresponding pixel (see col. 6 lines 1-8 for a first output line and a second output line each connected to a corresponding pixel (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)); an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (see col. 6 lines 51-65 for an analog-to-digital conversion unit configured to perform analog-to-digital conversion on the pixel signal to generate pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)); a first memory and a second memory each configured to hold the pixel data (see col. 7 lines 36-49 for a first memory and a second memory each configured to hold the pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)); and a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (see col. 7 lines 50-55 for a scanning circuit configured to perform scanning for causing the first memory and the second memory to output the pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)), wherein in a first mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate first pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate second pixel data (see col. 6 lines 53-65 for in a first mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate first pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate second pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)), the first memory stores the first pixel data, the second memory stores the second pixel data (see col. 7 lines 36-49 for the first memory stores the first pixel data, the second memory stores the second pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)), and the scanning circuit causes the first memory to output the first pixel data and causes the second memory to output the second pixel data (see col. 7 lines 50-55 for the scanning circuit causes the first memory to output the first pixel data and causes the second memory to output the second pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)), and wherein in a second mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate third pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate fourth pixel data (see col. 6 lines 53-65 for in a second mode, the analog-to-digital conversion unit performs analog-to-digital conversion on a pixel signal from the first output line to generate third pixel data and performs analog-to-digital conversion on a pixel signal from the second output line to generate fourth pixel data (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35)), the first memory stores the third pixel data and the fourth pixel data (see col. 7 lines 36-49 for the first memory stores the third pixel data and the fourth pixel data (i.e. in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)), and the scanning circuit causes the first memory to output the third pixel data and the fourth pixel data (see col. 7 lines 50-55 for the scanning circuit causes the first memory to output the third pixel data and the fourth pixel data (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)); and at least any one of: an optical device adapted for the imaging device, a control device configured to control the imaging device, a processing device configured to process a signal output from the imaging device, a display device configured to display information obtained by the imaging device, a storage device configured to store information obtained by the imaging device, and a mechanical device configured to operate based on information obtained by the imaging device (see col. 5 lines 48-58, col. 6 lines 1-8 for at least any one of: an optical device adapted for the imaging device, a control device configured to control the imaging device, a processing device configured to process a signal output from the imaging device, a display device configured to display information obtained by the imaging device, a storage device configured to store information obtained by the imaging device, and a mechanical device configured to operate based on information obtained by the imaging device (i.e. in this system configuration, the timing control circuit 18 generates clock signals and control signals serving as reference of the operations of the row scanning circuit 13, the column processing unit 14, the reference-voltage supplying unit 15, the column scanning circuit 16, and so on, based on a master clock MCK, and supplies the signals to the row scanning circuit 13, the column processing unit 14, the reference-voltage supplying unit 15, the column scanning circuit 16, and so on as described in fig. 1 col. 5 lines 58-67))
Re claim 20, Nitta discloses a method of driving imaging device including a plurality of pixels each configured to output a pixel signal (see col. 6 lines 1-8 for a plurality of pixels each configured to output a pixel signal (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)), a first output line and a second output line each connected to a corresponding pixel (see col. 6 lines 1-8 for a first output line and a second output line each connected to a corresponding pixel (i.e. in the pixel array unit 12, unit pixels 11 of m columns and n rows are two-dimensionally arranged, row control lines 21 (21-1 to 21-n) are arranged for the respective rows in the m columns and n rows of the unit pixels, and column signal lines 22 (22-1 to 22-m) are arranged for the respective columns, one end of each of the row control lines 21-1 to 21-n is connected to a corresponding output terminal of the row scanning circuit 13 as described in fig. 1 col. 6 lines 19-29)), and a first memory and a second memory each configured to hold pixel data generated by analog-to-digital conversion on the pixel signal (see col. 7 lines 36-49 for a first memory and a second memory each configured to hold the pixel data generated by analog-to-digital conversion on the pixel signal (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35, furthermore, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)), the method comprising: in a first mode, generating first pixel data by performing analog-to-digital conversion on a pixel signal from the first output line to store the first pixel data in the first memory and generating second pixel data by performing analog-to-digital conversion on a pixel signal from the second output line to store the second pixel data in the second memory (see col. 6 lines 53-65 for in a first mode, generating first pixel data by performing analog-to-digital conversion on a pixel signal from the first output line to store the first pixel data in the first memory and generating second pixel data by performing analog-to-digital conversion on a pixel signal from the second output line to store the second pixel data in the second memory (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35, furthermore, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)); and outputting the first pixel data from the first memory and outputting the second pixel data from the second memory (see col. 7 lines 50-55 for outputting the first pixel data from the first memory and outputting the second pixel data from the second memory (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62)), and in a second mode, generating third pixel data by performing analog-to-digital conversion on a pixel signal from the first output line to store the third pixel data in the first memory and generating fourth pixel data by performing analog-to-digital conversion on a pixel signal from the second output line to store the fourth pixel data in the first memory (see col. 6 lines 53-65 for in a second mode, generating third pixel data by performing analog-to-digital conversion on a pixel signal from the first output line to store the third pixel data in the first memory and generating fourth pixel data by performing analog-to-digital conversion on a pixel signal from the second output line to store the fourth pixel data in the first memory (i.e. the column processing unit 14 includes ADCs (analog-digital converters) 23-1 to 23-m, which are provided for the respective column signal lines 22-1 to 22-m of the pixel array unit 12, the ADCs 23-1 to 23-m convert analog signals output from the unit pixels 11 in the columns of the pixel array unit 12 to digital signals and output the digital signals as described in fig. 1 col. 6 lines 30-35, furthermore, in this way, analog signals supplied from the unit pixels 11 of the pixel array unit 12 through the column signal lines 22-1 to 22-m are converted to N-bit digital signals by the respective comparators 31 and the up/down counters 32 of the ADCs 23 (23-1 to 23-m), and the digital signals are stored in the memory devices 34 (34-1 to 34-m) as described in fig. 1 col. 7 lines 50-55)); and outputting the third pixel data and the fourth pixel data from the first memory (see col. 7 lines 50-55 for outputting the third pixel data and the fourth pixel data from the first memory (i.e. the column scanning circuit 16 includes a shift register or the like and controls a column address and column scanning of the ADCs 23-1 to 23-m in the column processing unit 14, under the control by the column scanning circuit 16, the N-bit digital signals which have been AD converted by the ADCs 23-1 to 23-m are sequentially read to the horizontal output line 17 and are output there through as image data as described in col. 7 lines 56-62))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of Shizukuishi (US 2004/0021788 A1)(hereinafter Shizukuishi).
Re claim 2, Nitta as discussed in claim 1 above discloses all the claimed limitations but fails to explicitly teach wherein the first memory has a storage capacity of k bits (k is an integer of two or more), wherein each of the first pixel data and the second pixel data is digital data of m bits (m is an integer of two or more and k or less), and wherein each of the third pixel data and the fourth pixel data is digital data of n bits (n is an integer of one or more and m/2 or less). However, the reference of Shizukuishi explicitly teaches wherein the first memory has a storage capacity of k bits (k is an integer of two or more), wherein each of the first pixel data and the second pixel data is digital data of m bits (m is an integer of two or more and k or less), and wherein each of the third pixel data and the fourth pixel data is digital data of n bits (n is an integer of one or more and m/2 or less) (see ¶s 34, 36, 38 for the first memory has a storage capacity of k bits (k is an integer of two or more), wherein each of the first pixel data and the second pixel data is digital data of m bits (m is an integer of two or more and k or less), and wherein each of the third pixel data and the fourth pixel data is digital data of n bits (n is an integer of one or more and m/2 or less) (i.e. the memory space (memory capacity) of one frame is the number of bits (N bits) per pixel.times.the horizontal pixel number (m).times.the vertical pixel number (n) of the light receiving area 2, therefore, the non-volatile memory area 6 has a memory space of the number of bits (N bits) per pixel.times.the horizontal pixel number (m).times.the row number (n) of the light receiving area 2.times.a frame number (k) as described in fig. 1 paragraph 39))
Therefore, taking the combined teachings of Nitta and Shizukuishi as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (capacity) into the system of Nitta as taught by Shizukuishi.
One will be motivated to incorporate the above feature into the system of Nitta as taught by Shizukuishi for the benefit of having a non-volatile memory area 6 which has a capacity capable of storing all pixel signals of one or more frames (full screen images), and is made of a semiconductor non-volatile memory such as a flash memory, wherein the memory space (memory capacity) of one frame is the number of bits (N bits) per pixel.times.the horizontal pixel number (m).times.the vertical pixel number (n) of the light receiving area 2, therefore, the non-volatile memory area 6 has a memory space of the number of bits (N bits) per pixel.times.the horizontal pixel number (m).times.the row number (n) of the light receiving area 2.times.a frame number (k) in order to improve efficiency when using the storage capacity of the non-volatile memory area 6 to store all pixel signals (see fig. 1 ¶ 39)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of Gahang (US 6,553,151 B1)(hereinafter Gahang).
Re claim 4, Nitta as discussed in claim 1 above discloses all the claimed limitations but fails to explicitly teach wherein in the second mode, the second memory stores dummy data of a fixed value. However, the reference of Gahang explicitly teaches wherein in the second mode, the second memory stores dummy data of a fixed value (see col. 3 lines 66-67, col. 4 lines 1-10 to 16-21 for in the second mode, the second memory stores dummy data of a fixed value (i.e. during the dummy scanning mode, the image sensor 100 scans a white panel or white roller mounted opposite the image sensor, once the dummy scanning is completed, the CPU 110 sequentially reads and store the shading data stored in the least significant address of the shading memory 108 in a temporary register (TMP) of the shading memory 108 at step S204, the CPU 110 then finds a shading factor for shading data previously stored in TMP by dividing a preset maximum brightness value by a value of the shading data previously stored in TMP at step S206, and stores the shading factor in the least significant address of the shading memory 108, where the shading data was originally read from at step S208 as described in figs. 1-2 col. 4 lines 22-35))
Therefore, taking the combined teachings of Nitta and Gahang as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (dummy) into the system of Nitta as taught by Gahang.
One will be motivated to incorporate the above feature into the system of Nitta as taught by Gahang for the benefit of having CPU 110 that generates a third control signal CNT3 for the image sensor control circuit 104 to start dummy scanning, and controls the DMA control circuit, so that output image data from ADC 102 is stored, as shading data, by pixel from the least significant address to the most significant address of shading memory 108 at step 202, wherein during the dummy scanning mode, the image sensor 100 scans a white panel or white roller mounted opposite the image sensor, wherein once the dummy scanning is completed, the CPU 110 sequentially reads and store the shading data stored in the least significant address of the shading memory 108 in a temporary register (TMP) of the shading memory 108 at step S204, wherein the CPU 110 then finds a shading factor for shading data previously stored in TMP by dividing a preset maximum brightness value by a value of the shading data previously stored in TMP at step S206, and stores the shading factor in the least significant address of the shading memory 108, where the shading data was originally read from at step S208 in order to ease the processing time when storing the shading data stored in the least significant address of the shading memory 108 (see figs. 1-2 col. 4 lines 16-35)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of Yoshida (US 2010/0134171 A1)(hereinafter Yoshida).
Re claim 7, Nitta as discussed in claim 1 above discloses all the claimed limitations but fails to explicitly teach wherein the analog-to-digital conversion unit includes a pipelined analog-to-digital conversion circuit. However, the reference of Yoshida explicitly teaches wherein the analog-to-digital conversion unit includes a pipelined analog-to-digital conversion circuit (see ¶ 111 for the analog-to-digital conversion unit includes a pipelined analog-to-digital conversion circuit (i.e. the AD converter 901 is a pipelined AD conversion circuit as shown in fig. 11))
Therefore, taking the combined teachings of Nitta and Yoshida as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (pipelined analog-to-digital conversion circuit) into the system of Nitta as taught by Yoshida.
One will be motivated to incorporate the above feature into the system of Nitta as taught by Yoshida for the benefit of having a type of circuit in the AD converter 901 which is a pipelined AD conversion circuit, wherein a pipelined AD conversion circuit operates using a two-phase clock that has a non-overlap period, and a change in the non-overlap period readily causes changes in the characteristics, and restricts the circuit operation margin, wherein in regard to this, the clock generation circuit 200 supplies, to the AD converter 901, the first clock CK1 and the second clock CK2 that have been adjusted such that changes in a non-overlap period due to temperature or variations during manufacturing are reduced, wherein the AD converter 901 operates using the first clock CK1 and the second clock CK2 that are output from the clock generation circuit 200 in order to improve efficiency when performing an A/D conversion process on the sensor signal (analog signal) output from the sensor signal output circuit 802 at a high speed and with high precision (see fig. 11 ¶s 111-112)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of GARCIA GONZALEZ et al. (US 2024/0055464 A1)(hereinafter GARCIA).
Re claim 12, Nitta as discussed in claim 1 above discloses all the claimed limitations but fails to explicitly teach wherein each of the plurality of pixels is sensitive to radiation. However, the reference of GARCIA explicitly teaches wherein each of the plurality of pixels is sensitive to radiation (see ¶ 44 for each of the plurality of pixels is sensitive to radiation (i.e. each of the electrodes 1100 is electrically connected to a respective pixel of the radiation-sensitive area 1200 to provide an electric signal in response to an electric charge received from the electrode to which the pixel is connected as described in fig. 1 paragraph 43))
Therefore, taking the combined teachings of Nitta and GARCIA as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (radiation) into the system of Nitta as taught by GARCIA.
One will be motivated to incorporate the above feature into the system of Nitta as taught by GARCIA for the benefit of having a plurality of the electrodes 1100 to respectively provide an electric charge, when a photon of an X-ray radiation hits the direct X-ray conversion layer is distributed over the radiation-sensitive area 1200, wherein each of the electrodes 1100 is electrically connected to a respective pixel of the radiation-sensitive area 1200 to provide an electric signal in response to an electric charge received from the electrode to which the pixel is connected in order to improve efficiency when providing an electric signal in response to an electric charge received from the electrode to which the pixel is connected (see fig. 1 ¶ 43)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of Lee (US 2002/0075252 A1)(hereinafter Lee).
Re claim 14, Nitta as discussed in claim 1 above discloses all the claimed limitations but fails to explicitly teach wherein in the second mode, the scanning circuit does not cause the second memory to output a signal. However, the reference of Lee explicitly teaches wherein in the second mode, the scanning circuit does not cause the second memory to output a signal (see ¶ 36 for in the second mode, the scanning circuit does not cause the second memory to output a signal (i.e. at this time, since the second control signal transmitted via the second control signal line 23 is in high state and the first control signal transmitted via the first control signal line 22 is in low state, the push nTFT N3, pull nTFT N4 and still pTFT P3 are turned off, and therefore, the memory cell unit 100 becomes floating from the powers VD1 and GND and is not operated as shown in fig. 3))
Therefore, taking the combined teachings of Nitta and Lee as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (does not cause the second memory to output a signal) into the system of Nitta as taught by Lee.
One will be motivated to incorporate the above feature into the system of Nitta as taught by Lee for the benefit of implementing, in the normal operation mode, when a high state voltage is supplied to the scan signal line and a corresponding operation mode image signal is supplied to the source signal line according to a frame period of a resolution, the high state voltage is supplied to the gate electrode that is the second electrode of the pixel switch N1 to be turned on, and at this time, image signals are transmitted to the third electrode 140 from the first electrode connected to the source signal line, wherein at this time, since the second control signal transmitted via the second control signal line 23 is in high state and the first control signal transmitted via the first control signal line 22 is in low state, the push nTFT N3, pull nTFT N4 and still pTFT P3 are turned off, and therefore, the memory cell unit 100 becomes floating from the powers VD1 and GND and is not operated in order to improve efficiency when transmitting the second control signal and the first control signal so the memory cell unit 100 becomes floating from the powers VD1 and GND and is not operated (see fig. 3 ¶ 36)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta et al. (US 9,769,411 B2)(hereinafter Nitta) as applied to claims 1, 5, 6, 8-11, 13, 16-18 and 20 above, and further in view of Kobayashi (US 2022/0030164 A1)(hereinafter Kobayashi).
Re claim 19, Nitta as discussed in claim 18 above discloses all the claimed limitations but fails to explicitly teach wherein the processing device acquires distance information on a distance from the imaging device to an object. However, the reference of Kobayashi explicitly teaches wherein the processing device acquires distance information on a distance from the imaging device to an object (see ¶ 135 for the processing device acquires distance information on a distance from the imaging device to an object (i.e. signal processing unit 708 acquires distance information from the imaging device 70 to an object as shown in fig. 19))
Therefore, taking the combined teachings of Nitta and Kobayashi as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (distance) into the system of Nitta as taught by Kobayashi.
One will be motivated to incorporate the above feature into the system of Nitta as taught by Kobayashi for the benefit of having a signal processing unit 708 that may be configured to process the pixel signal based on the electric charge generated in the first photoelectric conversion element and the pixel signal based on the electric charge generated in the second photoelectric conversion element, and acquire distance information from the imaging device 70 to the object in order to ease the processing time when processing pixel signal and acquiring distance information from the imaging device 70 to the object (see fig. 19 ¶ 135)
Conclusion
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1/22/2026
/JOSE M. MESA/
Examiner
Art Unit 2484
/THAI Q TRAN/Supervisory Patent Examiner, Art Unit 2484