DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The amendment filed June 8, 2026 has been entered. Claims 1-20 remain pending in this application.
Priority
Applicant’s claim for the benefit of prior-filed applications 15/790,882, now issued as US 10,437,476, 16/520,204, now issued as US 10,969,963, 17/184,487, now issued as US 11,520,484, 18/054,666, now issued as US 11,714,553, and 18/331,842 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. All claims are examined with an effective filing date of October 23, 2017.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on March 17, 2026 and June 12, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10, and 17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Oshima (US 2016/0342463, as provided in applicant’s IDS).
Regarding claim 1, Oshima teaches a device (Fig. 1, storage device 104), comprising:
a memory (Fig. 1, non-volatile semiconductor memory 112); and
a circuit (Fig. 1, back end 110, where [0033] provides hardware implementations for back end 110 teaching a circuit) configured to translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory (“Back end 110 includes multiple functional units, including … a logical-to-physical address translation unit 132” [0025], “For efficiency, it is advantageous for logical-to-physical translation unit 132 to use a logical address as an index to a single lookup table that encompasses all namespaces managed by SSD controller 105. However, the namespace-based addresses illustrated in FIG. 2 are not amenable for use in such a table,” [0040], “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041], see also Figs. 2 and 3, with Fig. 3 showing that the output of the conversion to the internal address is specifically a logical address, and the citations above showing that these are logical addresses in the namespace, see also [0038,0051]).
Regarding claim 2, Oshima teaches the device of claim 1, and further teaches wherein the first storage spaces include a namespace allocated from a storage capacity of the memory (see Fig. 2 showing name spaces allocated, where Figs. 3, 4, and 5 show how the namespace correlates to an internal linear addressing, where the linear internal addressing refers to the SSD’s internal address space, see [0043]).
Regarding claim 3, Oshima teaches the device of claim 2, and further teaches wherein the second storage space includes the storage capacity (see the SSD internal address space in [0043], see also Figs. 4 and 5 showing the entire logical address space of the NAND storage)
Regarding claim 10, Oshima teaches a method, comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of a memory of a device (Figs. 2, 4, 5, allocating namespaces from an internal logical address space of a storage device, see also Fig. 1 for the storage device)); and
translating, by the device, first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory (“Back end 110 includes multiple functional units, including … a logical-to-physical address translation unit 132” [0025], “For efficiency, it is advantageous for logical-to-physical translation unit 132 to use a logical address as an index to a single lookup table that encompasses all namespaces managed by SSD controller 105. However, the namespace-based addresses illustrated in FIG. 2 are not amenable for use in such a table,” [0040], “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041], see also Figs. 2 and 3, with Fig. 3 showing that the output of the conversion to the internal address is specifically a logical address, and the citations above showing that these are logical addresses in the namespace, see also [0038,0051]).
Regarding claim 17, Oshima teaches a non-transitory computer storage medium storing instructions which, when executed by a device having a memory, cause the device to perform a method (“One embodiment disclosed herein provides A non-transitory computer readable medium. The non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform a method”, [0007]) identical to the method of claim 10 and rejected according to the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-9, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima in view of Sundararaman et al. (US 2016/0070652, as provided in applicant’s IDS).
Regarding claim 4, Oshima teaches the device of claim 1, wherein the circuit is configured to divide the first logical addresses in the first storage spaces into first blocks (“The use of namespaces means that logical addresses provided by host system 102 to SSD controller 105 include a namespace identifier, which identifies a namespace (and can be, for example, a short sequence of bits), in addition to a logical block address, which identifies a logical block within that namespace,” [0038], teaching that the namespaces can be identified by block addresses, reading on the division of the first spaces and addresses into blocks, see also “The flow in the diagram begins with the host system 102 and ends with the back end 110 of the SSD controller 105. To access (read or write) particular data within storage device 104, host system 102 provides an LBA-based address 602 that includes a namespace identifier (“NSID”) and that specifies a logical block address (“LBA”) within the namespace associated with the NSID. The LBA specifies a particular block within the associated namespace. Note that because namespaces are independent logical subdivisions of storage for storage device 104, an LBA in one namespace points to a different location in NAND 112 than the same LBA in a different namespace,” [0051]) and map the first blocks into second blocks in the second storage space (“Logical-to-physical translation unit 132 translates logical addresses, e.g., logical block addresses (LBAs), to physical addresses, e.g., physical block addresses, of non-volatile semiconductor memory 112 during reading or writing data,” [0028], “logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table,” [0041] teaching that the internal linear address space addresses are also provided as blocks).
Oshima fails to teach where this division of the logical addresses into blocks is done according to a plurality of block sizes.
Sundararaman’s disclosure relates to a storage device and interface and as such comprises analogous art in the same field of endeavor of storage management.
As part of this disclosure, Sundararaman provides for a translation between IO namespaces to storage resources, where “The virtual blocks may be adapted to provide a desired storage granularity (e.g., block size),” [0070], with the ability to select different block sizes based on different factors, see [0099], and the example of [0153] showing different name spaces and storage resources with different block sizes, see also the Fig. 2B embodiment.
An obvious modification can be identified: providing flexibility to provide a desired block size for different virtual blocks and different underlying blocks, reading upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Sundararaman’s variable block size into Oshima’s system, as a flexible block size allows for the ability to account for different performance factors such as “memory overhead (e.g., larger virtual blocks 145 may result in a fewer number of entries in the forward map 125), garbage collection complexity, sequential storage performance of the storage resource(s) 190, I/O properties of the clients 106 (e.g., preferred client block size), and/or the like,” [0099].
Regarding claim 5, the combination of Oshima and Sundararaman teaches the device of claim 4, and Oshima further teaches wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces (as seen in Fig. 2, Oshima’s namespaces are ordered in a sequential manner, with each address being provided continuously within the respective namespace to provide for increasing offsets; this is also seen in Figs. 4 and 5).
Oshima fails to teach where fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
As seen in Oshima Figs. 4 and 5, Oshima’s internal linear address spaces provides for a sequential, continuous mapping from the namespace addresses to the linear address space.
As further provided in Sundararaman’s disclosure, in the Fig. 2B embodiment, the general address space 122 shows how discontinuous parts of the address space may be mapped to virtual blocks assigned to a given resource/namespace (see virtual blocks 145A being mapped arbitrarily within total address space with one arrow from the left side of the address space 122 and another arrow being mapped from close to the right side of the address space 122).
A further modification can be identified: incorporating Sundararaman’s disclosure of discontinuous mapping between an overall address space and the individual namespaces. Such a modification reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Sundararaman’s disclosure of discontinuous mapping between address spaces into Oshima’s disclosure, as this allows for flexibility to reuse parts of the logical address space as they are available instead of potentially having to shift data around in order to adjust boundaries of namespaces.
Regarding claim 6, the combination of Oshima and Sundararaman teaches the device of claim 5, and the combination further teaches wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks (as part of the incorporation of Sundararaman in the claim 4 rationale, Sundararaman [0153] provides for different block sizes while still providing for 2kb virtual blocks for the different LIDs, providing for a 2kb common size).
Regarding claim 7, the combination of Oshima and Sundararaman teaches the device of claim 6, and the combination further teaches wherein each of the first storage spaces is divided by no more than two block sizes (as shown in the claims 4 and 6 rationale, Sundararaman provides for different block size resources, where Fig 2B shows that each individual namespace 145A and 190A through 145N and 190N map different block sizes in 190A-190N onto the single common block size in 145A-145N, teaching that each of the namespaces utilizes both its own individual block size and the common size, with the following citations coming from Sundararaman);
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size (“In the FIG. 2B embodiment, the storage resource 190A may be configured with a block size of 1 kb, the storage resource 190B may have a block size of 2 kb, and the storage resource 190N may have a block size of 512 bytes. The translation module 124 may configure the LIDs to reference 2 kb blocks,” [0153], so each of the namespaces utilizes a smaller block size than the common block size); and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size (“In the FIG. 2B embodiment, the storage resource 190A may be configured with a block size of 1 kb, the storage resource 190B may have a block size of 2 kb, and the storage resource 190N may have a block size of 512 bytes. The translation module 124 may configure the LIDs to reference 2 kb blocks,” [0153], each namespace utilizes one block size, i.e. no more than one block having a block size different from the common lock size).
Regarding claim 8, the combination of Oshima and Sundararaman teaches the device of claim 7, and Oshima further teaches wherein the circuit is configured at least in part via firmware (“In various embodiments, the functional blocks included in front end 108 and back end 110 represent hardware or combined software and hardware elements for performing associated functionality. Thus, any or all of the functional blocks may be embodied as firmware executing in a processing unit,” [0033]).
Regarding claim 9, the combination of Oshima and Sundararaman teaches the device of claim 7, and the combination further teaches wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space (as discussed in the claim 7 rationale, incorporating the claims 4 and 6 rationale, Sundararaman’s disclosure provides for different block sizes for the different name spaces while providing for a larger common virtual block for the overall logical address space; in order to make this work, “The translation module 124 may configure the LIDs to reference 2 kb blocks, which may comprise mapping two virtual addresses 195A to each virtual block 145A, mapping one virtual address 195B to each virtual block 145B, mapping four virtual addresses 195N to each virtual block 145N, and so on,” [0153], teaching that smaller blocks are consolidated into blocks of the common size).
Claims 11, 12, 13, 14, 15, and 16 are rejected according to the rationale of claims 4, 5, 6, 7, 3 (incorporating the rejection to claim 2), and claim 9 respectively.
Claims 18, 19, and 20 are rejected according to the rationale of claims 11, 13 (incorporating the rejection to claim 12), and claim 9 (incorporating the rejection to claim 7) respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
For clarity, as the order of limitations and claims are not identical between applications, in all double patenting rejections presented below, the claims in the instant claim are presented in the recited order, and the limitations/claims of the patents are moved around as needed. Additionally, where possible for purpose of brevity, only claims 1-9 of the application will be compared in the tables, with comments concerning claims 10-20 provided as appropriate.
Claims 1-3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,437,476 in view of Oshima.
Claims 4-9, 11-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,437,476 in view of Oshima and further in view of Sundararaman.
Claim 1, instant application
Claim 1, US 10,437,476
A device, comprising:
a memory; and
a circuit configured to
translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.
A computer storage device, comprising:
a controller;
non-volatile storage media; and
firmware containing instructions which, when executed by the controller, instruct the controller to at least:
convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory.
Claim 8, instant application
Claim 1, US 10,437,476
The device of claim 7, wherein the circuit is configured at least in part via firmware.
firmware containing instructions which, when executed by the controller, instruct the controller to at least
Regarding claim 1, as seen in the table above, claim 1 of US 10,437,476 fails to teach that the result of the translation are specifically second logical addresses.
Oshima discloses and teaches this in “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Oshima’s disclosure of converting namespaces logical addresses to a unified logical address space first, as this provides for a more efficient logical-to-physical translation, see Oshima [0040].
Regarding claims 2-9, with the exception of claim 8 shown in the table above, all the other claims are taught by their disclosure in Oshima and Sundararaman as seen in the prior art rejections and are incorporated into the double patenting rejection for the same rationale presented in the prior art rejection.
Regarding claims 10-20, the analysis largely follows the same as claims 1-9, with the exception of the different statutory categories. However, the different statutory categories are not patentably distinct, as these are simply obvious variants of the device of claim 1 with its configured functionality.
Claims 1-3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,969,963 in view of Oshima.
Claims 4-9, 11-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of U.S. Patent No. 10,969,963 in view of Oshima and further in view of Sundararaman.
Claim 1, instant application
Claim 1, US 10,969,963
A device, comprising:
a memory; and
a circuit configured to
translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.
A computer storage device, comprising:
non-volatile storage media; and
a controller configured to at least:
Claim 8, instant application
Claim 3, US 10,969,963
The device of claim 7, wherein the circuit is configured at least in part via firmware.
The computer storage device of claim 1, wherein the computer storage device is a solid state drive; and the controller is configured at least in part via firmware.
Regarding claim 1, as seen in the table above, claim 1 of US 10,969,963 fails to teach the translation between logical addresses of different address spaces.
Oshima discloses and teaches this in “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Oshima’s disclosure of converting namespaces logical addresses to a unified logical address space first, as this provides for a more efficient logical-to-physical translation needed for accessing underlying storage media, see Oshima [0040].
Regarding claims 2-9, with the exception of claim 8 as shown in the table above, all the other claims are taught by their disclosure in Oshima and Sundararaman as seen in the prior art rejections and are incorporated into the double patenting rejection for the same rationale presented in the prior art rejection.
Regarding claims 10-20, the analysis largely follows the same as claims 1-9, with the exception of the different statutory categories. However, the different statutory categories are not patentably distinct, as these are simply obvious variants of the device of claim 1 with its configured functionality.
Claims 1-3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,520,484 in view of Oshima.
Claims 4-9, 11-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of U.S. Patent No. 11,520,484 in view of Oshima and further in view of Sundararaman.
Claim 1, instant application
Claim 1, US 11,520,484
A device, comprising:
a memory; and
a circuit configured to
translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory;
A device, comprising:
storage media; and
a controller configured to at least:
Claim 8, instant application
Claim 3, US 11,520,484
The device of claim 7, wherein the circuit is configured at least in part via firmware.
The device of claim 1, wherein the device is a solid state drive; and the controller is configured at least in part via firmware.
Regarding claim 1, as seen in the table above, claim 1 of US 11,520,484 fails to teach the translation between logical addresses of different address spaces.
Oshima discloses and teaches this in “Thus, instead of using namespace-based addresses as indexes to logical-to-physical lookup tables, logical-to-physical translation unit 132 instead first converts the namespace-based address to a linear, internal address that is not based on namespaces (also referred to herein simply as an “internal address,” or a “linear address”) and uses that linear, internal address as an index to a logical-to-physical lookup table. Within the linear address space that is associated with the linear, internal address, the namespaces are arrayed in a back-to-back manner, so that the linear addresses corresponding to one namespace are adjacent to the linear addresses corresponding to the subsequent namespace. This effectively converts the namespace-based address space into an address space that includes a single set of numbers that begin at 0 and increase to a maximum number,” [0041].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Oshima’s disclosure of converting namespaces logical addresses to a unified logical address space first, as this provides for a more efficient logical-to-physical translation needed for accessing underlying storage media, see Oshima [0040].
Regarding claims 2-9, with the exception of claim 8 as seen in the table above, all the other claims are taught by their disclosure in Oshima and Sundararaman as seen in the prior art rejections and are incorporated into the double patenting rejection for the same rationale presented in the prior art rejection.
Regarding claims 10-20, the analysis largely follows the same as claims 1-9, with the exception of the different statutory categories. However, the different statutory categories are not patentably distinct, as these are simply obvious variants of the device of claim 1 with its configured functionality.
Claims 1-3, 10, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 11,714,553.
Claims 4-9, 11-16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2 and 4 of U.S. Patent No. 11,714,553 in view of Oshima and Sundararaman.
Claim 1, instant application
Claim 2, US 11,714,553, incorporating claim 1
A device, comprising:
a memory; and
a circuit configured to
translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory;
A device, comprising:
memory cells configured to provide a storage capacity of the device; and
a logic circuit configured to:
translate, based on a first size of a first block of continuous logical addresses in a first namespace, first logical addresses in the first block in the first namespace into second logical addresses in the storage capacity
Claim 2, instant application
Claim 2, US 11,714,553, incorporating claim 1
The device of claim 1, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory.
… first logical addresses in the first block in the first namespace
Claim 3, instant application
Claim 2, US 11,714,553, incorporating claim 1
The device of claim 2, wherein the second storage space includes the storage capacity.
… into second logical addresses in the storage capacity
Claim 8, instant application
Claim 4, US 11,714,553
The device of claim 7, wherein the circuit is configured at least in part via firmware.
The device of claim 3, wherein the logic circuit includes a controller configured at least in part via firmware.
Regarding claim 1, as seen in the table above, while claim 2 of US 11,714,553 does not recite the limitations of instant claim 1 exactly the same, the subject matter is patentably indistinct, as claim 1 of US 11,714,553 clearly provides for a logical address in name space to logical address in storage capacity translation, and claim 2 provides this on a block by block basis, i.e. while it does not explicitly recite dividing the logical addresses into blocks in the first logical space, this must necessarily occur in order to provide a block by block mapping between logical addresses.
Regarding claims 4-7 and 9, all the other claims are taught by their disclosure in Oshima and Sundararaman as seen in the prior art rejections and are incorporated into the double patenting rejection for the same rationale presented in the prior art rejection.
Regarding claims 10-20, the analysis largely follows the same as claims 1-9, with the exception of the different statutory categories. However, the different statutory categories are not patentably distinct, as these are simply obvious variants of the device of claim 1 with its configured functionality.
Claims 1-20 of copending Application No. 18/331,842 contains every element of claims 1-20 of the instant application, as can be shown in the following table, and as such anticipates claims 1-20 of the instant application. “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. For clarity of record, this chart compares the most recent version of the copending claims filed December 8, 2025.
Claim 1, instant application
Claim 1, 18/331,842
A device, comprising:
a memory; and
a circuit configured to translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.
A device, comprising:
a memory; and
a circuit configured to translate, based on a plurality of block sizes, the first logical addresses specified in the first storage spaces implemented using the portions of the memory into second logical addresses specified in a second storage space corresponding to a capacity of the memory
…
Claim 2, instant application
Claim 2, 18/331,842
The device of claim 1, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory.
The device of claim 1, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory.
Claim 3, instant application
Claim 3, 18/331,842
The device of claim 2, wherein the second storage space includes the storage capacity.
The device of claim 2, wherein the second storage space includes the storage capacity.
Claim 4, instant application
Claim 4, 18/331,842
The device of claim 1, wherein the circuit is configured to divide, according to a plurality of block sizes, the first logical addresses in the first storage spaces into first blocks and map the first blocks into second blocks in the second storage space.
The device of claim 1, wherein the circuit is configured to divide, according to the plurality of block sizes, the first logical addresses in the first storage spaces into the first blocks and map the first blocks into second blocks in the second storage space.
Claim 5, instant application
Claim 5, 18/331,842
The device of claim 4, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
The device of claim 4, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
Claim 6, instant application
Claim 6, 18/331,842
The device of claim 5, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
The device of claim 5, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
Claim 7, instant application
Claim 7, 18/331,842
The device of claim 6, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
The device of claim 6, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
Claim 8, instant application
Claim 8, 18/331,842
The device of claim 7, wherein the circuit is configured at least in part via firmware.
The device of claim 7, wherein the circuit is configured at least in part via firmware.
Claim 9, instant application
Claim 9, 18/331,842
The device of claim 7, wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
The device of claim 7, wherein the circuit is configured to consolidate at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
Claim 10, instant application
Claim 10, 18/331,842
A method, comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of a memory of a device; and
translating first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory.
A method, comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of a memory of a device;
translating, by the device based on a plurality of block sizes, the first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory;
…
Claim 11, instant application
Claim 11, 18/331,842
The method of claim 10, further comprising:
dividing, according to a plurality of block sizes, the first logical addresses in the first storage spaces into first blocks to map the first blocks into second blocks in the second storage space.
The method of claim 10, further comprising:
dividing, according to the plurality of block sizes, the first logical addresses in the first storage spaces into the first blocks to map the first blocks into second blocks in the second storage space.
Claim 12, instant application
Claim 12, 18/331,842
The method of claim 11, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
The method of claim 11, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space.
Claim 13, instant application
Claim 13, 18/331,842
The method of claim 12, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
The method of claim 12, wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
Claim 14, instant application
Claim 14, 18/331,842
The method of claim 13, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
The method of claim 13, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size; and
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size.
Claim 15, instant application
Claim 15, 18/331,842
The method of claim 14, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory; and the second storage space includes the storage capacity.
The method of claim 14, wherein the first storage spaces include a namespace allocated from a storage capacity of the memory; and the second storage space includes the storage capacity.
Claim 16, instant application
Claim 16, 18/331,842
The method of claim 14, further comprising:
consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
The method of claim 14, further comprising:
consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
Claim 17, instant application
Claim 17, 18/331,842
A non-transitory computer storage medium storing instructions which, when executed by a device having a memory, cause the device to perform a method, the method comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of the memory of the device; and
translating first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory
A non-transitory computer storage medium storing instructions which, when executed by a device having a memory, cause the device to perform a method, the method comprising:
allocating a plurality of first storage spaces respectively from a plurality of portions of the memory of the device; translating, by the device based on a plurality of block sizes, first logical addresses specified in the first storage spaces into second logical addresses specified in a second storage space defined in the memory;
…
Claim 18, instant application
Claim 18, 18/331,842
The non-transitory computer storage medium of claim 17, wherein the method further comprises:
dividing, according to a plurality of block sizes, the first logical addresses in the first storage spaces into first blocks to map the first blocks into second blocks in the second storage space.
The non-transitory computer storage medium of claim 17, wherein the method further comprises:
dividing, according to the plurality of block sizes, the first logical addresses in the first storage spaces into first blocks to map the first blocks into second blocks in the second storage space.
Claim 19, instant application
Claim 19, 18/331,842
The non-transitory computer storage medium of claim 18, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space; and
wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
The non-transitory computer storage medium of claim 18, wherein the first blocks include third logical addresses that are specified continuously in one of the first storage spaces; and fourth logical addresses, mapped from the third logical addresses, are not continuous in the second storage space; and
wherein the plurality of block sizes include a common block size shared across the first storage spaces in division of the first logical addresses in the first storage spaces into the first blocks.
Claim 20, instant application
Claim 20, 18/331,842
The non-transitory computer storage medium of claim 19, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size;
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size; and
wherein the method further comprises:
consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
The non-transitory computer storage medium of claim 19, wherein each of the first storage spaces is divided by no more than two block sizes;
wherein each of the first storage spaces is divided by at least one block size that is no larger than the common block size;
wherein each of the first storage spaces is divided to include no more than one block of logical addresses having a block size that is different from the common block size; and
wherein the method further comprises:
consolidating, at least two of the first blocks into being mapped within a third block having the common block size in the second storage space.
Response to Arguments
Applicant's arguments filed June 8, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments focus on the overall disclosed invention, focusing on namespaces on p.1, the dynamic allocation of multiple namespaces on p.2, the block by block mapping on p.2, and utilizing blocks of LBA addresses on p.2. The applicant then asserts that this is captured via the claimed elements of independent claim 1 and that Oshima fails to teach this invention. However, this is unpersuasive, as the elements identified above and other technical elements that are argued are not at all found in the independent language of claim 1.
Claim 1 as presented in the amendment recites “A device, comprising:
a memory; and
a circuit configured to translate first logical addresses specified in first storage spaces defined in portions of the memory into second logical addresses specified in a second storage space defined in the memory.”
There is no recitation in the independent claims of namespaces, any dynamic allocation, any idea that the translation is based on block size. The argument is therefore unpersuasive, as the asserted arguments are not found within the claim limitations of independent claim 1 as argued and therefore are not required within the broadest interpretation of the claim scope.
For clarity of record, examiner notes that claim 2 is rejected as anticipated by Oshima for teaching the argued namespaces, but this is plainly clear as Oshima depicts the use of namespace ID’s for converting logical addresses, teaching claim 2, see the rejection under 35 U.S.C. 102. Further, Claim 2 only recites that namespaces are allocated from the storage capacity, with no further detail about the namespaces being dynamically allocated or the use of different block sizes as argued, so the arguments regarding namespaces would still be unpersuasive with regards to claim 2, even though the arguments are not presented as such.
For clarity of record, later dependent claims do recite the features regarding a plurality of block sizes, but the office action acknowledges that Oshima fails to anticipate this, instead relying on Sundararaman, see the rejection under 35 U.S.C. 103. The arguments against the disclosed inventive features are unpersuasive as even in claims that do recite the disclosed features, the rejection is one of obviousness, not anticipation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou (US 2018/0189174, as presented in applicant’s IDS) discloses providing multiple namespaces and translating between addresses,
Asano et al. (US 2018/0260334) discloses utilizing namespace tables to translate from LBA’s associated with namespaces to physical addresses, as well as the ability to specify subdivisions of namespaces that use partial blocks.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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