DETAILED ACTION
This office action is responsive to application 19/022,140 filed on January 15, 2025, the preliminary amendment filed February 25, 2025, and the election reply filed June 12, 2026. Claims 1-42 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 (figure 2, claims 1, 2, 6-11, 13, 19-24, 28-33, 35, 41 and 42) in the reply filed on June 12, 2026 is acknowledged. The traversal is on the ground(s) that claim 1 is generic because claim 1 defines a common or generic invention encompassing all of the identified species. This is not found persuasive because claim 1 requires both a first reset unit and a second reset unit. Species 2 (figure 4), Species 4 (figure 7), and Species 5 (figure 8) only include a single reset unit (2). Therefore, claim 1 is not generic to at least Species 2, Species 4 and Species 5.
The requirement is still deemed proper and is therefore made FINAL.
Claims 3-5, 12, 14-18, 25-27, 34 and 36-40 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 12, 2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“detection unit” in claims 1-22
“first reset unit” in claims 1-9 and 11-22
“second reset unit” in claims 1-22
“distance information acquisition unit” in claim 22
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim limitations are interpreted under 35 USC 112(f) as follows:
The “detection unit” in claims 1-22 corresponds to element “4” of figure 2, which is an inverter or a comparator (see paragraph 0030 of US 2021/0020793).
The “first reset unit” in claims 1-9 and 11-22 corresponds to a transistor (see paragraph 0021 of US 2021/0020793).
The “second reset unit” in claims 1-22 corresponds to a transistor (see paragraph 0025 of US 2021/0020793).
The “distance information acquisition unit” in claim 22 corresponds to element “1310” of figure 11A, which is a vehicle sensor (see paragraph 0082 of US 2021/0020793).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-9, 11, 13, 19, 23, 28, 29, 31, 35 and 41 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutton et al. (US 2014/0124652).
Consider claim 1, Dutton et al. teaches:
A photoelectric conversion apparatus (see figure 6) comprising:
an avalanche diode (SPAD, 605, paragraphs 0044 and 0002);
a detection unit (push-pull inverter, 695) configured to detect an avalanche current generated by avalanche multiplication in the avalanche diode (“a push-pull inverter 695 is provided to invert the SPAD 605 output”, paragraph 0044);
a switch (620b) disposed between the avalanche diode (605) and the detection unit (695, see figure 6, paragraphs 0027 and 0044); and
a first reset unit (620a) configured to reset a node (i.e. to VDD) between the switch (620b) and the detection unit (695, see figure 6, paragraphs 0027 and 0044);
a second reset unit (610) configured to reset an output node of the avalanche diode (The gate of the second reset circuit (610) receives a reset signal (SR) which necessarily comes from a control circuit, see figures 6, 2 and 4, paragraph 0026.) and configured to reset an output node of the avalanche diode (i.e. to VEB, see figure 6, paragraph 0026).
The Examiner notes that claim 1 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “wherein the first reset unit resets the node during a period in which the switch is in an off state” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 1. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 1 is directed toward an apparatus and not toward a method of operating the apparatus.
Nevertheless, Dutton et al. teaches that the first reset unit (620a) resets the node during a period in which the switch (620b) is in an off state (See figures 2 and 4. The reset circuit (620a) resets the node according to control signal DIS in a period (i.e. in a period immediately after “Dynamic Range/Frame”) in which the switch (620b) is in an off state due to control signal EN, paragraphs 0031-0033, 0037 and 0038.).
With regards to claim 6, the Examiner notes that claim 6 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “turning on and off of the switch is controlled by a clock pulse to be periodically input” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 6. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 6 is directed toward an apparatus and not toward a method of operating the apparatus.
Nevertheless, Dutton et al. teaches that turning on and off of the switch (620b) is controlled by a clock pulse (EN) to be periodically input (see figures 2 and 4).
With regards to claim 7, the Examiner notes that claim 7 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “the first reset unit resets the node in response to input of the clock pulse” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 7. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 7 is directed toward an apparatus and not toward a method of operating the apparatus.
With regards to claim 8, the Examiner notes that claim 8 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “the clock pulse is simultaneously input to the switch and the first reset unit” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 8. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 8 is directed toward an apparatus and not toward a method of operating the apparatus.
With regards to claim 9, the Examiner notes that claim 9 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “the first reset unit is turned on after the switch is turned off, and the switch is turned on after the first reset unit is turned off” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 9. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 9 is directed toward an apparatus and not toward a method of operating the apparatus.
Nevertheless, Dutton et al. teaches that the first reset unit (620a) is turned on (i.e. via DIS) after the switch (620b) is turned off (i.e. via EN, see figures 2 and 4), and the switch (620b) is turned on (i.e. via EN) after the first reset unit (620a) is turned off (i.e. via DIS, see figures 2 and 4).
With regards to claim 11, the Examiner notes that claim 11 is directed toward an apparatus (i.e. a photoelectric conversion apparatus). The recitation “the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection circuit when a threshold voltage of the detection circuit is passed through” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Dutton et al. teaches all of the structural limitations of claim 11. Whether Dutton et al. teaches the claimed manner of operation associated with said structure is inconsequential, as claim 11 is directed toward an apparatus and not toward a method of operating the apparatus.
Consider claim 13, and as applied to claim 1 above, Dutton et al. further teaches that the switch (620b) is disposed between the second reset unit (610) and the detection circuit (695, see figure 6).
Consider claim 19, and as applied to claim 1 above, Dutton et al. further teaches a plurality of photoelectric conversion circuits each including the avalanche diode, the detection circuit, and the switch is two-dimensionally arranged (“a large scale array for 3D single photon avalanche diode (SPAD) based imagers”, paragraph 0021), and wherein the plurality of photoelectric conversion circuits is configured to individually control turning on and off of each of the reset circuit and the switch (i.e. via DIS an EN, respectively, figure 6).
Consider claim 23, Dutton et al. teaches:
A method of driving a photoelectric conversion apparatus, the apparatus (see figure 6) comprising:
an avalanche diode (SPAD, 605, paragraphs 0044 and 0002);
a detection unit (push-pull inverter, 695) configured to detect an avalanche current generated by avalanche multiplication in the avalanche diode (“a push-pull inverter 695 is provided to invert the SPAD 605 output”, paragraph 0044);
a switch (620b) disposed between the avalanche diode (605) and the detection unit (695, see figure 6, paragraphs 0027 and 0044); and
a first reset unit (620a) configured to reset a node (i.e. to VDD) between the switch (620b) and the detection unit (695, see figure 6, paragraphs 0027 and 0044);
a second reset unit (610) configured to reset an output node of the avalanche diode (The gate of the second reset circuit (610) receives a reset signal (SR) which necessarily comes from a control circuit, see figures 6, 2 and 4, paragraph 0026.) and configured to reset an output node of the avalanche diode (i.e. to VEB, see figure 6, paragraph 0026), wherein
the first reset unit (620a) resets the node during a period in which the switch (620b) is in an off state (See figures 2 and 4. The reset circuit (620a) resets the node according to control signal DIS in a period (i.e. in a period immediately after “Dynamic Range/Frame”) in which the switch (620b) is in an off state due to control signal EN, paragraphs 0031-0033, 0037 and 0038.).
Consider claim 28, and as applied to claim 23 above, Dutton et al. further teaches that turning on and off of the switch (620b) is controlled by a clock pulse (EN) to be periodically input (see figures 2 and 4).
Consider claim 29, and as applied to claim 28 above, Dutton et al. further teaches that the first reset unit (620a) resets the node in response to input of the clock pulse (i.e. according to DIS and EN in figures 6, 2 and 4, paragraphs 0031, 0032 and 0037).
Consider claim 31, and as applied to claim 29 above, Dutton et al. further teaches that the first reset unit is turned on after the switch is turned off, and the switch is turned on after the reset unit is turned off (i.e. according to DIS and EN in figures 6, 2 and 4, paragraphs 0031, 0032 and 0037).
Consider claim 35, and as applied to claim 23 above, Dutton et al. further teaches that the switch (620b) is disposed between the second reset unit (610) and the detection circuit (695, see figure 6).
Consider claim 41, and as applied to claim 23 above, Dutton et al. further teaches a plurality of photoelectric conversion circuits each including the avalanche diode, the detection circuit, and the switch is two-dimensionally arranged (“a large scale array for 3D single photon avalanche diode (SPAD) based imagers”, paragraph 0021), and wherein the plurality of photoelectric conversion circuits is configured to individually control turning on and off of each of the reset circuit and the switch (i.e. via DIS an EN, respectively, figure 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 10, 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Dutton et al. (US 2014/0124652) in view of Ikeda (US 2020/0091214).
Consider claim 2, and as applied to claim 1 above Dutton et al. does not explicitly teach a counter configured to count the number of generation times of the avalanche current detected by the detection circuit.
Ikeda similarly teaches a photoelectric conversion apparatus (figure 1) comprising:
an avalanche diode (101, “an avalanche diode is preferably used”, paragraph 0065);
a detection circuit (inverter circuit, 103, paragraph 0056) configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode (i.e. due to its placement downstream of the avalanche diode (101), as shown in figure 1, paragraphs 0074 and 0075);
a switch (transistor, 102) disposed between an output node of the avalanche diode (101) and the detection circuit (103, see figure 1, paragraph 0061); and
a first reset circuit (transistor, 104) configured to reset a node (node, AN) between the switch (102) and the detection circuit (103, see figure 1, paragraph 0075).
However, Ikeda additionally teaches a counter (counter circuit, 202) configured to count the number of generation times of the avalanche current detected by the detection circuit (i.e. by counting an output pulse signal, paragraph 0083).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion apparatus taught by Dutton et al. comprise a counter as taught by Ikeda for the benefit of providing an imaging device capable of executing image processing with high reliability (Ikeda, paragraphs 0010 and 0011).
Consider claim 10, and as applied to claim 8 above, Dutton et al. does not explicitly teach a transistor constituting the switch and a transistor constituting the first reset unit have opposite conductivity types.
Ikeda similarly teaches a photoelectric conversion apparatus (figure 1) comprising:
an avalanche diode (101, “an avalanche diode is preferably used”, paragraph 0065);
a detection circuit (inverter circuit, 103, paragraph 0056) configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode (i.e. due to its placement downstream of the avalanche diode (101), as shown in figure 1, paragraphs 0074 and 0075);
a switch (transistor, 102) disposed between an output node of the avalanche diode (101) and the detection circuit (103, see figure 1, paragraph 0061); and
a first reset circuit (transistor, 104) configured to reset a node (node, AN) between the switch (102) and the detection circuit (103, see figure 1, paragraph 0075).
However, Ikeda additionally teaches that a transistor constituting the switch (102) and a transistor (104) constituting the first reset unit (104) have opposite conductivity types (See the symbols for 102 and 104 in figure 1.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the transistor constituting the switch and a transistor constituting the first reset unit taught by Dutton et al. be of opposite conductivity types as taught by Ikeda for the benefit of providing an imaging device with low power consumption that is less likely to be affected by noise (Ikeda, paragraphs 0010 and 0011).
Consider claim 21, Dutton et al. teaches a photoelectric conversion system comprising: a photoelectric conversion apparatus according to claim 1 (see claim 1 rationale).
Dutton et al. does not explicitly a signal processing circuit configured to process a signal output from the photoelectric conversion apparatus.
Ikeda similarly teaches a photoelectric conversion apparatus (figure 1) comprising:
an avalanche diode (101, “an avalanche diode is preferably used”, paragraph 0065);
a detection circuit (inverter circuit, 103, paragraph 0056) configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode (i.e. due to its placement downstream of the avalanche diode (101), as shown in figure 1, paragraphs 0074 and 0075);
a switch (transistor, 102) disposed between an output node of the avalanche diode (101) and the detection circuit (103, see figure 1, paragraph 0061); and
a first reset circuit (transistor, 104) configured to reset a node (node, AN) between the switch (102) and the detection circuit (103, see figure 1, paragraph 0075).
However, Ikeda additionally teaches a signal processing circuit (circuit, 405, figure 4) configured to process a signal output from the photoelectric conversion apparatus (see paragraphs 0086 and 0114-0116).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion system taught by Dutton et al. comprise a signal processing circuit configured to process a signal output from the photoelectric conversion apparatus as taught by Ikeda for the benefit of providing an imaging device capable of executing image processing with high reliability (Ikeda, paragraphs 0010 and 0011).
Consider claim 24, and as applied to claim 23 above Dutton et al. does not explicitly teach a counter configured to count the number of generation times of the avalanche current detected by the detection circuit.
Ikeda similarly teaches a photoelectric conversion apparatus (figure 1) comprising:
an avalanche diode (101, “an avalanche diode is preferably used”, paragraph 0065);
a detection circuit (inverter circuit, 103, paragraph 0056) configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode (i.e. due to its placement downstream of the avalanche diode (101), as shown in figure 1, paragraphs 0074 and 0075);
a switch (transistor, 102) disposed between an output node of the avalanche diode (101) and the detection circuit (103, see figure 1, paragraph 0061); and
a first reset circuit (transistor, 104) configured to reset a node (node, AN) between the switch (102) and the detection circuit (103, see figure 1, paragraph 0075).
However, Ikeda additionally teaches a counter (counter circuit, 202) configured to count the number of generation times of the avalanche current detected by the detection circuit (i.e. by counting an output pulse signal, paragraph 0083).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion apparatus taught by Dutton et al. comprise a counter as taught by Ikeda for the benefit of providing an imaging device capable of executing image processing with high reliability (Ikeda, paragraphs 0010 and 0011).
Claims 20 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Dutton et al. (US 2014/0124652) in view of Nishihara (US 10,841,518).
Consider claim 20, and as applied to claim 1 above, Dutton et al. does not explicitly teach a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection circuit, and wherein the second substrate includes the avalanche diode.
Nishihara similarly teaches a photoelectric conversion apparatus (figure 14) comprising an photodiode (photodiode, 111E, column 23, lines 8-15) and a detection circuit (sense circuit, 121E, column 23, lines 8-15), wherein the photodiode is an avalanche photodiode (see column 22, lines 8-16), and wherein the detection circuit (121E) comprises an inverter (IV121, figure 15, column 23, lines 52-56).
However, Nishihara additionally teaches a first substrate (SUB2E) and a second substrate (SUB1E) stacked on the first substrate (see figure 14), wherein the first substrate (SUB2E) includes the detection circuit (121E), and wherein the second substrate (SUB1E) includes the avalanche diode (111E). See figure 14, column 23, lines 8-15.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the detection circuit and avalanche diode taught by Dutton et al. be implemented in first and second stacked substrates as taught by Nishihara for the benefit of improving imaging performance at a low cost (Nishihara, column 5, lines 55-59).
Consider claim 42, and as applied to claim 23 above, Dutton et al. does not explicitly teach a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection circuit, and wherein the second substrate includes the avalanche diode.
Nishihara similarly teaches a photoelectric conversion apparatus (figure 14) comprising an photodiode (photodiode, 111E, column 23, lines 8-15) and a detection circuit (sense circuit, 121E, column 23, lines 8-15), wherein the photodiode is an avalanche photodiode (see column 22, lines 8-16), and wherein the detection circuit (121E) comprises an inverter (IV121, figure 15, column 23, lines 52-56).
However, Nishihara additionally teaches a first substrate (SUB2E) and a second substrate (SUB1E) stacked on the first substrate (see figure 14), wherein the first substrate (SUB2E) includes the detection circuit (121E), and wherein the second substrate (SUB1E) includes the avalanche diode (111E). See figure 14, column 23, lines 8-15.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the detection circuit and avalanche diode taught by Dutton et al. be implemented in first and second stacked substrates as taught by Nishihara for the benefit of improving imaging performance at a low cost (Nishihara, column 5, lines 55-59).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Dutton et al. (US 2014/0124652) in view of Tochigi et al. (US 2021/0051279).
Consider claim 22, Dutton et al. teaches a photoelectric conversion apparatus according to claim 1 (see claim 1 rationale).
However, Dutton et al. does not explicitly teach that the photoelectric conversion apparatus is part of a moving body comprising a distance information acquisition circuit configured to acquire distance information from parallax information based on a signal output from the photoelectric conversion apparatus, the distance information indicating a distance from an object, wherein the moving body further comprises a control circuit configured to control the moving body based on the distance information.
Tochigi similarly teaches a photoelectric conversion apparatus (figure 7) comprising an avalanche photodiode (222, paragraph 0082) and a detection unit (271, paragraph 0084).
However Tochigi additionally teaches that the photoelectric conversion apparatus is part of a moving body (figure 27, paragraphs 0154 and 0155) comprising a distance information acquisition circuit (imaging units, 12101 to 12104) configured to acquire distance information from parallax information based on a signal output from the photoelectric conversion apparatus (see paragraph 0170), the distance information indicating a distance from an object (“of persons, vehicles, obstacles, signs, letters on a road surface, or the like on the basis of the received image”, paragraph 0159), wherein the moving body (figure 27) further comprises a control circuit (integrated control unit, 12050) configured to control the moving body based on the distance information (see paragraphs 0159, 0160, 0162 and 0163).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion apparatus taught by Dutton et al. be implemented in a moving body as taught by Tochigi for the benefit of enabling a vehicle to automatically perform collision avoidance or shock mitigation of the vehicle, follow travel based on a vehicular gap, vehicle speed maintaining travel, collision warning of the vehicle, lane out warning of the vehicle, and the like (Tochigi, paragraph 0162).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 6-11, 13, 19-24, 28-33, 35, 41 and 42 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-8 and 10-14 of U.S. Patent No. 12,230,722. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 4, 6-11, 13, 19-24, 28-33, 35, 41 and 42 are anticipated by claims 1, 4-8 and 10-14 of US 12,230,722 as follows:
Consider claim 1, claim 1 of US 12,230,722 teaches (in parentheses):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
an avalanche diode (an avalanche diode);
a detection unit configured to detect an avalanche current generated by avalanche multiplication in the avalanche diode (a detection circuit configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode);
a switch disposed between the avalanche diode and the detection unit (a switch disposed between an output node of the avalanche diode and the counter); and
a first reset unit configured to reset a node between the switch and the detection unit (a reset circuit configured to reset a node between the switch and the detection circuit);
a second reset unit configured to reset an output node of the avalanche diode (a second reset circuit configured to reset the output node of the avalanche diode),
wherein the first reset unit resets the node during a period in which the switch is in an off state (wherein the reset circuit resets the node during a period in which the switch is in an off state).
Consider claim 2, claim 1 of US 12,230,722 teaches (in parentheses):
a counter configured to count the number of generation times of the avalanche current detected by the detection unit (a counter configured to count the number of generation times of the avalanche current detected by the detection circuit).
Consider claim 6, claim 4 of US 12,230,722 teaches (in parentheses):
turning on and off of the switch is controlled by a clock pulse to be periodically input (turning on and off of the switch is controlled by a clock pulse to be periodically input).
Consider claim 7, claim 5 of US 12,230,722 teaches (in parentheses):
the first reset unit resets the node in response to input of the clock pulse (the reset circuit resets the node in response to input of the clock pulse).
Consider claim 8, claim 6 of US 12,230,722 teaches (in parentheses):
the clock pulse is simultaneously input to the switch and the first reset unit (the clock pulse is simultaneously input to the switch and the reset circuit).
Consider claim 9, claim 7 of US 12,230,722 teaches (in parentheses):
the first reset unit is turned on after the switch is turned off, and the switch is turned on after the first reset unit is turned off (the reset circuit is turned on after the switch is turned off, and the switch is turned on after the reset circuit is turned off).
Consider claim 10, claim 6 of US 12,230,722 teaches (in parentheses):
a transistor constituting the switch and a transistor constituting the first reset unit have opposite conductivity types (a transistor constituting the switch and a transistor constituting the reset circuit have opposite conductivity types).
Consider claim 11, claim 8 of US 12,230,722 teaches (in parentheses):
the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection unit when a threshold voltage of the detection unit is passed through (the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection circuit when a threshold voltage of the detection circuit is passed through).
Consider claim 13, claim 10 of US 12,230,722 teaches (in parentheses):
the switch is disposed between the second reset unit and the detection unit (the switch is disposed between the second reset circuit and the detection circuit).
Consider claim 19, claim 11 of US 12,230,722 teaches (in parentheses):
a plurality of photoelectric conversion units each including the avalanche diode, the detection unit, and the switch is two-dimensionally arranged, and wherein the plurality of photoelectric conversion units is configured to individually control turning on and off of each of the first reset unit and the switch (a plurality of photoelectric conversion circuits each including the avalanche diode, the detection circuit, and the switch is two-dimensionally arranged, and wherein the plurality of photoelectric conversion circuits is configured to individually control turning on and off of each of the reset circuit and the switch).
Consider claim 20, claim 12 of US 12,230,722 teaches (in parentheses):
a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection unit, and wherein the second substrate includes the avalanche diode (a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection circuit, and wherein the second substrate includes the avalanche diode).
Consider claim 21, claim 13 of US 12,230,722 teaches (in parentheses):
a signal processing unit configured to process a signal output from the photoelectric conversion apparatus (a signal processing circuit configured to process a signal output from the photoelectric conversion apparatus).
Consider claim 22, claim 14 of US 12,230,722 teaches (in parentheses):
a distance information acquisition unit configured to acquire distance information from parallax information based on a signal output from the photoelectric conversion apparatus, the distance information indicating a distance from an object, wherein the moving body further comprises a control unit configured to control the moving body based on the distance information (a distance information acquisition circuit configured to acquire distance information from parallax information based on a signal output from the photoelectric conversion apparatus, the distance information indicating a distance from an object, wherein the moving body further comprises a control circuit configured to control the moving body based on the distance information).
Consider claim 23, claim 1 of US 12,230,722 teaches (in parentheses):
A method for driving a photoelectric conversion apparatus, the apparatus comprising: (A photoelectric conversion apparatus comprising:)
an avalanche diode; (an avalanche diode)
a detection unit configured to detect an avalanche current generated by avalanche multiplication in the avalanche diode; (a detection circuit configured to output a signal based on an avalanche current generated by avalanche multiplication in the avalanche diode)
a switch disposed between the avalanche diode and the detection unit; (a switch disposed between an output node of the avalanche diode and the counter)
a first reset unit configured to reset a node between the switch and the detection unit; (a reset circuit configured to reset a node between the switch and the detection circuit) and
a second reset unit configured to reset an output node of the avalanche diode (a second reset circuit configured to reset the output node of the avalanche diode), and
wherein the first reset unit resets the node during a period in which the switch is in an off state (wherein the reset circuit resets the node during a period in which the switch is in an off state).
Consider claim 24, claim 1 of US 12,230,722 teaches (in parentheses):
a counter configured to count the number of generation times of the avalanche current detected by the detection unit (a counter configured to count the number of generation times of the avalanche current detected by the detection circuit).
Consider claim 28, claim 4 of US 12,230,722 teaches (in parentheses):
turning on and off of the switch is controlled by a clock pulse to be periodically input (turning on and off of the switch is controlled by a clock pulse to be periodically input).
Consider claim 29, claim 5 of US 12,230,722 teaches (in parentheses):
the first reset unit resets the node in response to input of the clock pulse (the reset circuit resets the node in response to input of the clock pulse).
Consider claim 30, claim 6 of US 12,230,722 teaches (in parentheses):
the clock pulse is simultaneously input to the switch and the first reset unit (the clock pulse is simultaneously input to the switch and the reset circuit).
Consider claim 31, claim 7 of US 12,230,722 teaches (in parentheses):
the first reset unit is turned on after the switch is turned off, and the switch is turned on after the first reset unit is turned off (the reset circuit is turned on after the switch is turned off, and the switch is turned on after the reset circuit is turned off).
Consider claim 32, claim 6 of US 12,230,722 teaches (in parentheses):
a transistor constituting the switch and a transistor constituting the first reset unit have opposite conductivity types (a transistor constituting the switch and a transistor constituting the reset circuit have opposite conductivity types).
Consider claim 33, claim 8 of US 12,230,722 teaches (in parentheses):
the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection unit when a threshold voltage of the detection unit is passed through (the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection circuit when a threshold voltage of the detection circuit is passed through).
Consider claim 35, claim 10 of US 12,230,722 teaches (in parentheses):
the switch is disposed between the second reset unit and the detection unit (the switch is disposed between the second reset circuit and the detection circuit).
Consider claim 41, claim 11 of US 12,230,722 teaches (in parentheses):
a plurality of photoelectric conversion units each including the avalanche diode, the detection unit, and the switch is two-dimensionally arranged, and wherein the plurality of photoelectric conversion units is configured to individually control turning on and off of each of the first reset unit and the switch (a plurality of photoelectric conversion circuits each including the avalanche diode, the detection circuit, and the switch is two-dimensionally arranged, and wherein the plurality of photoelectric conversion circuits is configured to individually control turning on and off of each of the reset circuit and the switch).
Consider claim 42, claim 12 of US 12,230,722 teaches (in parentheses):
a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection unit, and wherein the second substrate includes the avalanche diode (a first substrate and a second substrate stacked on the first substrate, wherein the first substrate includes the detection circuit, and wherein the second substrate includes the avalanche diode).
Allowable Subject Matter
Claims 30, 32 and 33 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon submission of a proper Terminal Disclaimer overcoming the Double Patenting rejection outlined herein.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 30, the prior art of record does not teach nor reasonably suggest that the clock pulse is simultaneously input to the switch and the first reset unit, in combination with the other elements recited in parent claims 23, 28 and 29.
Claim 32 contains allowable subject matter as depending from claim 30.
Consider claim 33, the prior art of record does not teach nor reasonably suggest that the clock pulse has a frequency of 1/Td, where Td represents an interval between a falling edge and a rising edge of a potential input to the detection unit when a threshold voltage of the detection unit is passed through, in combination with the other elements recited in parent claims 23, 28 and 29.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kalgi (US 2019/0281238) teaches a pixel configuration (figure 8) with a SPAD (801), a second reset unit (802), a first reset unit (Reset1) and a switch (101).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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