DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending. Claims 3, 15, 18, and 20 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on June 12, 2026
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 12, 2026 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-12, and 14-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 9 of U.S. Patent No. 11,733,873. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patent would anticipate the claims of the current application. See chart below.
Current Application
US 11,733,873
1. A device, comprising:
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
a controller configured to:
track degrees of wear of the memory units based on a normalized degree of wear; and
adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units.
1. A solid state drive, comprising:
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
a controller;
firmware containing instructions configured to instruct the controller to:
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
3. The device of claim 1, wherein the controller is further configured to generate the address map prior to an access of the memory units using the address map.
Claim 1
generate an address map mapping logical addresses to physical addresses of the memory units of the different types;
4. The device of claim 1, wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
Claim 1
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
5. The device of claim 1, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
Claim 1
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
6. The device of claim 1, wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
Claim 1
track numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
7. The device of claim 1, wherein the non-volatile memory units of different types comprise at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
2. The solid state drive of claim 1, wherein the types of the memory units include at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
8. The device of claim 1, wherein the controller is further configured to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
3. The solid state drive of claim 1, wherein the instructions are further configured to instruct the controller to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify a second memory unit having less wear than the first memory unit;
9. The device of claim 8, wherein the controller is further configured to:
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
Claim 3
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
10. The device of claim 9, wherein the first memory unit and the second memory unit are of different types.
4. The solid state drive of claim 3, wherein the first memory unit and the second memory unit are of different types.
11. The device of claim 9, wherein the first memory unit and the second memory unit have different program erase budgets.
5. The solid state drive of claim 3, wherein the first memory unit and the second memory unit have different program erase budgets.
12. A non-transitory computer storage medium storing instructions thereon which,
upon execution by a controller of a memory device, cause the memory device to:
access memory units of different types that have different program erase budgets corresponding to the different types respectively;
track degrees of wear of the memory units based on a normalized degree of wear;
and adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units.
1. A solid state drive, comprising:
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
14. The non-transitory computer storage medium of claim 12, generate the address map prior to the access of the memory units using the address map.
Claim 1
generate an address map mapping logical addresses to physical addresses of the memory units of the different types;
15. The non-transitory computer storage medium of claim 12, wherein the instructions further cause the memory device to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
3. The solid state drive of claim 1, wherein the instructions are further configured to instruct the controller to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
identify a second memory unit having less wear than the first memory unit;
16. The non-transitory computer storage medium of claim 12, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
Claim 1
track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
17. The non-transitory computer storage medium of claim 12, wherein the memory units of different types comprise at least two of:
single level cell non-volatile flash memory;
multi level cell non-volatile flash memory;
triple level cell non-volatile flash memory; and
quad level cell non-volatile flash memory.
2. The solid state drive of claim 1, wherein the types of the memory units include at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
18. A method comprising:
accessing, by a controller of a memory device, memory units of different types;
tracking, by the controller, degrees of wear of the memory units based on a normalized degree of wear; and
adjusting, by the controller, an address map based at least in part on the normalized degree of wear for at least one of the memory units.
6. A method implemented in a solid state drive, the method comprising:
providing a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
tracking data indicating degrees of wear of the memory units, wherein the degrees of wear are normalized according to the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
adjusting the address map based at least in part on the program erase budgets to level wear across the memory units of the different types;
19. The method of claim 18, wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units.
Claim 6
tracking data indicating degrees of wear of the memory units, wherein the degrees of wear are normalized according to the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets; and
20. The method of claim 18, wherein the memory units comprise at least two memory units of different types,
wherein the different types of memory units have different program erase budgets.
9. The method of claim 8, wherein the first memory unit and the second memory unit are of different types.
10. The method of claim 8, wherein the first memory unit and the second memory unit have different program erase budgets.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 3-12, and 14-20 of copending Application No. 18/452,020 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Patent would anticipate the claims of the current application. See chart below.
Current Application
18/452,020 (10/30/2025)
1. A device, comprising:
a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
a controller configured to:
track degrees of wear of the memory units based on a normalized degree of wear; and
adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units.
1. A device, comprising:
a set of non-volatile memory units of different types, wherein the non-volatile memory units of different types comprise at least three different memory types each having different program erase budgets corresponding to the different types respectively;
a controller configured to:
access the memory units using an address map that maps logical addresses to physical addresses of the memory units;
track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types having different program erase budgets based on the at least three different memory types; and
adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units; and
a host interface different from the controller, the host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
2. The device of claim 1, further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
Claim 1
the host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
3. The device of claim 1, wherein the controller is further configured to generate the address map prior to an access of the memory units using the address map.
3. The device of claim 1, wherein the controller is further configured to generate the address map prior to the access of the memory units using the address map.
4. The device of claim 1, wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
4. The device of claim 1, wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
5. The device of claim 1, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
5. The device of claim 1, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
6. The device of claim 1, wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
6. The device of claim 1, wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
7. The device of claim 1, wherein the non-volatile memory units of different types comprise at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
7. The device of claim 1, wherein the non-volatile memory units of different types comprise at least two of:
single level cell flash memory;
multi level cell flash memory;
triple level cell flash memory; and
quad level cell flash memory.
8. The device of claim 1, wherein the controller is further configured to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
8. The device of claim 1, wherein the controller is further configured to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
9. The device of claim 8, wherein the controller is further configured to:
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
9. The device of claim 8, wherein the controller is further configured to:
change the address map to map the logical address to the second memory unit; and
write the data in the second memory unit.
10. The device of claim 9, wherein the first memory unit and the second memory unit are of different types.
10. The device of claim 9, wherein the first memory unit and the second memory unit are of different types.
11. The device of claim 9, wherein the first memory unit and the second memory unit have different program erase budgets.
11. The device of claim 9, wherein the first memory unit and the second memory unit have different program erase budgets.
12. A non-transitory computer storage medium storing instructions thereon which,
upon execution by a controller of a memory device, cause the memory device to:
access memory units of different types that have different program erase budgets corresponding to the different types respectively;
track degrees of wear of the memory units based on a normalized degree of wear;
and adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units.
12. A non-transitory computer storage medium storing instructions thereon which, upon execution by a controller of a memory device, cause the memory device to:
access memory units using an address map that maps logical addresses to physical addresses of the memory units, wherein the memory units comprise a set of memory units of different types, wherein the memory units of different types comprise at least three different memory types each having different program erase budgets corresponding to the different types respectively;
track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types having different program erase budgets based on the at least three different memory types;
adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units; and
communicate with a host device through a communication channel connecting a host interface and the host device, wherein the host interface is different from the controller.
13. The non-transitory computer storage medium of claim 12, wherein the instructions further cause the memory device to communicate with a host device through a communication channel connecting the host interface and the host device.
Claim 12
communicate with a host device through a communication channel connecting a host interface and the host device, wherein the host interface is different from the controller.
14. The non-transitory computer storage medium of claim 12, generate the address map prior to the access of the memory units using the address map.
14. The non-transitory computer storage medium of claim 12, generate the address map prior to the access of the memory units using the address map.
15. The non-transitory computer storage medium of claim 12, wherein the instructions further cause the memory device to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
15. The non-transitory computer storage medium of claim 12, wherein the instructions further cause the memory device to:
receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
16. The non-transitory computer storage medium of claim 12, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
16. The non-transitory computer storage medium of claim 12, wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
17. The non-transitory computer storage medium of claim 12, wherein the memory units of different types comprise at least two of:
single level cell non-volatile flash memory;
multi level cell non-volatile flash memory;
triple level cell non-volatile flash memory; and
quad level cell non-volatile flash memory.
17. The non-transitory computer storage medium of claim 12, wherein the memory units of different types comprise at least two of:
single level cell non-volatile flash memory;
multi level cell non-volatile flash memory;
triple level cell non-volatile flash memory; and
quad level cell non-volatile flash memory.
18. A method comprising:
accessing, by a controller of a memory device, memory units of different types;
tracking, by the controller, degrees of wear of the memory units based on a normalized degree of wear; and
adjusting, by the controller, an address map based at least in part on the normalized degree of wear for at least one of the memory units.
18. (Currently Amended) A method comprising:
accessing, by a controller of a memory device, memory units using an address map that maps logical addresses to physical addresses of the memory units, wherein the memory units comprise a set of memory units, wherein the set of memory units comprises at least three different memory types each having different program erase budgets corresponding to the different types respectively;
tracking, by the controller, degrees of wear of the memory units based on a normalized degree of wear for each of the memory units having different program erase budgets based on the at least three different memory types; and
adjusting, by the controller, the address map based at least in part on the normalized degree of wear for at least one of the memory units; and
communicating, by the controller, with a host device through a communication channel connecting a host interface and the host device, wherein the host interface is part of the memory device and the host interface different from the controller.
19. The method of claim 18, wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units.
19. The method of claim 18, wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units.
20. The method of claim 18, wherein the memory units comprise at least two memory units of different types,
wherein the different types of memory units have different program erase budgets.
20. The method of claim 18, wherein the memory units comprise at least two memory units of different types,
wherein the different types of memory units have different program erase budgets.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Objections
Claim 15 is objected to because of the following informalities: The claim currently includes three limitations of which the first two limitations appear to be a repeat of each other. Examiner believes this could be a typographical error and the duplicate should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-12, and 14-20 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Sutardja (US 2008/0140918) (hereinafter Sutardja) (published June 12, 2008).
Regarding Claims 1, 12, and 18, taking claim 1 as exemplary, Sutardja discloses a device, comprising: a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
a controller configured to:
“A solid-state disk 450 may include a controller 460, a first solid-state nonvolatile memory 462, and a second solid-state nonvolatile memory 464” (Sutardja [0141])
track degrees of wear of the memory units based on a normalized degree of wear; and
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts. For example, the number of write cycles performed on a block in the first solid-state nonvolatile memory 204 may be divided by the total number of write cycles that a block in the first solid-state nonvolatile memory 204 can endure” (Sutardja [0122])
adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units.
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts” (Sutardja [0122])
“At various times, such as periodically, the wear leveling module may analyze the wear levels of the blocks, and remap relatively frequently rewritten logical addresses to blocks with low wear levels. In addition, the wear leveling module may remap relatively infrequently rewritten logical addresses to blocks with high wear levels, which is known as static data shifting” (Sutardja [0167])
Claims 12 and 18 further recite access(ing) of the memory units.
“The controller 202 receives access requests from a host 220. The controller 202 directs the access requests to the first solid-state nonvolatile memory 204 or the second solid-state nonvolatile memory 206, as will be described below” (Sutardja [0105])
Regarding Claims 3 and 14, Sutardja further discloses wherein the controller is further configured to generate the address map prior to an access of the memory units using the address map.
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164] the address map is already generated before the request and is used to direct the access to the correct address)
Regarding Claim 4, Sutardja further discloses wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types.
“The number of erases performed on a block may therefore not be an appropriate comparison between a block from the first memory and a block of the second memory. To achieve appropriate comparisons, the erase counts can be normalized. One way of normalizing is to divide the erase count by the total number of erase counts a block in that memory is expected to be able to withstand. For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161])
Regarding Claims 5 and 16, Sutardja further discloses wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types.
“Another way of normalizing, which avoids fractional numbers, is to multiply the erase counts of blocks in the first memory (having the lower write cycle lifetime) by the ratio of write cycle lifetimes. In the current example, the ratio is 10 (100,000/10,000). A block in the first memory that has been erased 1,000 times would then have a normalized wear level of 10,000, while a block in the second memory that has been erased 1,000 times would then have a normalized wear level of 1,000” (Sutardja [0163] the erase budget/write cycle lifetimes of the smaller one is normalized to the higher erase budget write cycle lifetimes, also the largest program erase budget 100,000 is used in the calculation of the normalized value)
Regarding Claim 6, Sutardja further discloses wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units,
“The wear leveling module 260 may use a normalized version of the write and/or erase cycle counts” (Sutardja [0122])
wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units.
“Another way of normalizing, which avoids fractional numbers, is to multiply the erase counts of blocks in the first memory (having the lower write cycle lifetime) by the ratio of write cycle lifetimes. In the current example, the ratio is 10 (100,000/10,000). A block in the first memory that has been erased 1,000 times would then have a normalized wear level of 10,000, while a block in the second memory that has been erased 1,000 times would then have a normalized wear level of 1,000” (Sutardja [0163] it is inherent that the normalized erase cycles are proportional to the number of actual program erase cycle and inversely proportional to program erase budgets of the memory units)
Regarding Claims 7 and 17, Sutardja further discloses wherein the non-volatile memory units of different types comprise at least two of: single level cell flash memory; multi level cell flash memory; triple level cell flash memory; and quad level cell flash memory.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
Regarding Claims 8 and 15, Sutardja further discloses wherein the controller is further configured to: receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164])
identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.
“When the wear leveling module has good data for estimating access frequencies, the wear leveling module may move data from a used block to free that block for an incoming write. In this way, an incoming write to a block that is relatively frequently accessed can be written to a block with a low wear level. Also, an incoming write to a block that is relatively infrequently accessed can be written to a block with a high wear level” (Sutardja [0166])
Regarding Claim 9, Sutardja further discloses wherein the controller is further configured to: change the address map to map the logical address to the second memory unit; and write the data in the second memory unit.
“Control writes data to the first and/or second NVS memories in step 510 according to the mapping generated in steps 506 and 508” (Sutardja [0147])
“When a write request for a logical address arrives at the wear leveling module, the wear leveling module may determine if the logical address is already mapped to a physical address. If so, the wear leveling module may direct the write to that physical address” (Sutardja [0164])
“When the wear leveling module has good data for estimating access frequencies, the wear leveling module may move data from a used block to free that block for an incoming write. In this way, an incoming write to a block that is relatively frequently accessed can be written to a block with a low wear level. Also, an incoming write to a block that is relatively infrequently accessed can be written to a block with a high wear level” (Sutardja [0166] mapping is changed to another physical address that has a lower wear level)
Regarding Claim 10, Sutardja further discloses wherein the first memory unit and the second memory unit are of different types.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
Regarding Claims 11, Sutardja further discloses wherein the first memory unit and the second memory unit have different program erase budgets.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
Regarding Claim 19, Sutardja further discloses wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units.
“Another way of normalizing, which avoids fractional numbers, is to multiply the erase counts of blocks in the first memory (having the lower write cycle lifetime) by the ratio of write cycle lifetimes. In the current example, the ratio is 10 (100,000/10,000). A block in the first memory that has been erased 1,000 times would then have a normalized wear level of 10,000, while a block in the second memory that has been erased 1,000 times would then have a normalized wear level of 1,000” (Sutardja [0163] the erase budget/write cycle lifetimes of the smaller one is normalized to the higher erase budget write cycle lifetimes, also the largest program erase budget 100,000 is used in the calculation of the normalized value)
Regarding Claims 20, Sutardja further discloses wherein the memory units comprises at least two memory units of different types, wherein the different types of memory unit have different program erase budgets.
“The first solid-state nonvolatile memory 204 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory. The second solid-state nonvolatile memory 206 may include single-level cell (SLC) flash memory or multi-level cell (MLC) flash memory” (Sutardja [0108])
“For example only, the first memory have a write cycle lifetime of 10,000, while the second memory has a write cycle lifetime of 100,000” (Sutardja [0161] SLC would have more write cycle lifetime than MLC)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja (published June 12, 2008) in view of Fai et al. (US 2012/0216079) (hereinafter Fai) (published August 23, 2012).
Regarding Claims 2 and 13, Sutardja disclosed the device of claim 1 and medium of claim 12, and further discloses a communication channel connecting the host interface and the host device.
“In various implementations, the host 220 may specify to the controller 202 the logical addresses that correspond to data that will change relatively frequently and the logical addresses that correspond to data that will change relatively infrequently” (Sutardja [0106] see figs. 2-6 the path connecting the host to the controller is the communication channel)
But does not explicitly state further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
Fai discloses further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device.
“The NVM package 104 can interact with the host 102 over the connection 110 using a host interface 114 and a memory controller 116. Like the host controller 112, the memory controller 116 can include one or more processors and/or microprocessors 118 that are configured to perform operations based on the execution of software and/or firmware instructions” (Fai [0022] See fig. 1)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the host interface of Fai with the system in Sutardja. The motivation for doing so would be improve compatibility by using industry standards like USB as disclosed by Fai. “The host 102 can communicate with the NVM package 104 over the connection 110. The connection 110 between the host 102 and the NVM package 104 the can be fixed (e.g., fixed communications channel) and/or detachable (e.g., a universal serial bus (USB) port)” (Fai [0021])
Response to Arguments
Double Patenting
Applicant's arguments filed June 12, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
a) (page 1 top) Claim 1 recites "adjust an address map based at least in part on the normalized degree of wear for at least one of the memory units." The emphasized portion of this element is not present in the '873 patent claims as shown on page 4 of the Office Action. For at least these reasons, the currently pending claims are patentably distinct from the granted claims of the '873 patent.
With respect to (a), although the ’873 patent does not recite the emphasized language verbatim, it does disclose the underlying feature. In particular, the ’873 patent states, “track degrees of wear of the memory units, wherein the degrees of wear are normalized to account for differences in the program erase budgets corresponding to the different types, wherein the degrees of wear are normalized using a largest one of the program erase budgets”. Thus, the ’873 patent expressly discloses determining a normalized degree of wear for the memory units. Moreover, the normalized wear information is used in connection with managing the memory units and their address mappings. Accordingly, the claimed step of “adjust[ing] an address map based at least in part on the normalized degree of wear” is not a limitation that is absent from the disclosure merely because the ’873 patent uses different wording. Rather, the ’873 patent discloses the relevant functionality by tracking and normalizing the degree of wear of the memory units and using that wear information in managing the mapping of addresses to the memory units. Therefore, the fact that the exact phrase “adjust an address map based at least in part on the normalized degree of wear” does not appear verbatim in the ’873 patent claims does not establish that the feature is absent from the ’873 disclosure. The relevant inquiry is whether the claimed subject matter is disclosed, expressly or inherently, by the ’873 patent. Here, the ’873 patent expressly discloses the normalized wear information that forms the basis for the claimed address-map adjustment. Accordingly, this limitation does not provide a patentable distinction over the ’873 patent merely by virtue of the particular claim language used.
Claim Objections
Applicant's arguments filed June 12, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
b) (page 1 middle) Applicant has amended the claims to address the typographical errors noted in the Office Action.
With respect to (b), the amendment to claim 15 does not fully address the objection, an updated objection is issued above.
Rejection under 35 U.S.C. § 112
Applicant’s arguments, see page 1 of remarks, filed June 12, 2026, with respect to claim3 have been fully considered and are persuasive. The 35 U.S.C. § 112 rejection of claim 3 has been withdrawn.
Rejection under 35 U.S.C. § 102/103
Applicant's arguments filed June 12, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
c) Accordingly, Sutardja describes a remapping process that involves "swapping data in two blocks." However, swapping data in two blocks does not disclose a controller configured to "adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units," as recited in Claim 1. (Emphasis added.) In other words, swapping data between blocks as in Sutardja does not disclose adjustments to an address map as recited in the claims.
With respect to (c), Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Contrary to Applicant's characterization, the cited paragraph of Sutardja expressly describes remapping logical addresses based on the wear levels of the blocks. Paragraph [0167] states that the wear leveling module may “analyze the wear levels of the blocks, and remap relatively frequently rewritten logical addresses to blocks with low wear levels,” and may likewise “remap relatively infrequently rewritten logical addresses to blocks with high wear levels.” Thus, Sutardja does not merely disclose swapping data between blocks in isolation; it expressly discloses remapping logical addresses based on wear levels. Such remapping necessarily constitutes an adjustment to the address mapping between logical addresses and physical blocks.
Applicant's argument improperly attempts to distinguish Sutardja based on the particular mechanism by which the remapping may be implemented. The fact that Sutardja further explains that “remapping may involve swapping data in two blocks” does not transform the disclosed remapping of logical addresses into something other than an adjustment of the address map. The claimed limitation is directed to adjusting the address map based at least in part on wear, and Sutardja expressly describes remapping logical addresses according to the wear levels of the blocks. Applicant therefore cannot avoid the disclosure merely by focusing on the optional implementation detail of swapping data between blocks.
Accordingly, Applicant's argument does not identify a substantive distinction between the claimed address-map adjustment and the remapping expressly disclosed by Sutardja. Rather, Applicant attempts to steer the disclosure toward a different concept, the physical swapping of data, and then argues that data swapping is not an address-map adjustment. But the cited passage itself makes clear that the relevant operation is the remapping of logical addresses based on wear levels; the subsequent description of swapping data is merely an explanation of how such remapping may be performed. Thus, Sutardja discloses the recited address-map adjustment, and Applicant has not shown how the claim amendment distinguishes over that disclosure.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.L./Examiner, Art Unit 2137
/PRASITH THAMMAVONG/Primary Examiner, Art Unit 2137
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