DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: on page 1, line 7, the patent number of the parent case is missing.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,298,924. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has merely reworded the patented claims and removed some limitations. It is obvious to reword patented claims and remove limitations from patented claims. Similarities between the instant claims and the patented claims are shown in the table below comparing one claim from each group of claims:
Instant claim 1
Patented claim 3 (including independent claim 1 and intermediate claim 2)
1. An apparatus comprising one or more processor units configured to identify a set of M memory addresses from a set of N input memory addresses containing at least one non-unique memory addresses, wherein N > M, and wherein the M memory addresses are to be used for accessing one or blocks of memory in parallel, the apparatus configured to:
1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
perform a plurality of address comparisons of the set of N input memory addresses to generate a dataset of N classification values, wherein a subset of the N classification values identify a corresponding subset of unique addresses from the set of N input addresses;
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a classification dataset that identifies a subset of unique addresses from the set of input addresses;
sort at least a portion of the dataset of N classification values into a plurality of intermediary datasets, wherein each intermediary dataset comprises a first group of values identifying addresses belonging to the subset of unique addresses and a second group of values identifying addresses not belonging to the subset of unique addresses; in dependence on the first group of each of the intermediary datasets, selectively obtain a set of M memory addresses wherein the obtained set of M memory addresses comprises fewer non-unique memory addresses than the set of N input memory addresses;
a plurality of combination logic units, each configured to: receive a subset of data from the classification dataset and order the subset of data into two groups, wherein a first group identifies addresses belonging to the subset of unique addresses, and a second group identifies addresses not belonging to the subset of unique addresses;
and output the obtained set of M memory addresses for accessing, in parallel, memory addresses identified by the set of M memory addresses within one or blocks of memory.
and output generating logic configured to select between data belonging to different subsets of data to generate an output identifying at least one address in the subset of unique addresses.
2. An apparatus as claimed in claim 1, wherein the classification dataset is a binary classification dataset, and wherein the subset of data from the classification data is a predetermined selection of bits.
3. An apparatus as claimed in claim 2, wherein ordering the subset of data into two groups comprises sorting the predetermined selection of bits into an intermediary binary string.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,816,044. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has merely reworded the patented claims and removed some limitations. It is obvious to reword patented claims and remove limitations from patented claims. Similarities between the instant claims and the patented claims are shown in the table below comparing one claim from each group of claims:
Instant claim 1
Patented claim 17 (including independent claim 1 and intermediate claims 5 and 6)
1. An apparatus comprising one or more processor units configured to identify a set of M memory addresses from a set of N input memory addresses containing at least one non-unique memory addresses, wherein N > M, and wherein the M memory addresses are to be used for accessing one or blocks of memory in parallel, the apparatus configured to:
1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
perform a plurality of address comparisons of the set of N input memory addresses to generate a dataset of N classification values, wherein a subset of the N classification values identify a corresponding subset of unique addresses from the set of N input addresses;
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; and a monitoring unit configured to generate an output flag whose status indicates whether all addresses in the subset identified by the binary classification dataset have been output by output generating logic, the output generating logic being configured to generate an output containing an address in the identified subset of addresses.
sort at least a portion of the dataset of N classification values into a plurality of intermediary datasets, wherein each intermediary dataset comprises a first group of values identifying addresses belonging to the subset of unique addresses and a second group of values identifying addresses not belonging to the subset of unique addresses; in dependence on the first group of each of the intermediary datasets, selectively obtain a set of M memory addresses wherein the obtained set of M memory addresses comprises fewer non-unique memory addresses than the set of N input memory addresses; and output the obtained set of M memory addresses for accessing, in parallel, memory addresses identified by the set of M memory addresses within one or blocks of memory.
5. The apparatus of claim 1, further comprising a combination logic unit configured to receive bits of the binary classification dataset; and sort the bits into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.
6. The apparatus of claim 5, further comprising an additional combination logic unit, with each of the combination logic units configured to receive a subset of the bits of the binary classification dataset.
17. The apparatus of claim 6, wherein each combination logic unit is configured to sort its received predetermined selection of bits into an intermediary binary string containing fewer bits than the number of the predetermined selection of bits received by that combination logic unit.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,249,925. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has merely reworded the patented claims and removed some limitations. It is obvious to reword patented claims and remove limitations from patented claims. Similarities between the instant claims and the patented claims are shown in the table below comparing one claim from each group of claims:
Instant claim 1
Patented claim 5 (including independent claim 1)
1. An apparatus comprising one or more processor units configured to identify a set of M memory addresses from a set of N input memory addresses containing at least one non-unique memory addresses, wherein N > M, and wherein the M memory addresses are to be used for accessing one or blocks of memory in parallel, the apparatus configured to:
1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
perform a plurality of address comparisons of the set of N input memory addresses to generate a dataset of N classification values, wherein a subset of the N classification values identify a corresponding subset of unique addresses from the set of N input addresses;
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; wherein the comparator block is further configured to generate from the comparison of input addresses a match mask indicating, for each input address, which of the other input addresses match that input address;
sort at least a portion of the dataset of N classification values into a plurality of intermediary datasets, wherein each intermediary dataset comprises a first group of values identifying addresses belonging to the subset of unique addresses and a second group of values identifying addresses not belonging to the subset of unique addresses; in dependence on the first group of each of the intermediary datasets, selectively obtain a set of M memory addresses wherein the obtained set of M memory addresses comprises fewer non-unique memory addresses than the set of N input memory addresses;
5. The apparatus as claimed in claim 1, further comprising a combination logic unit configured to receive bits of the binary classification dataset; and sort the bits into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.
and output the obtained set of M memory addresses for accessing, in parallel, memory addresses identified by the set of M memory addresses within one or blocks of memory.
(from claim 1) and output generating logic configured to generate an output containing at least one address in the identified subset.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 10,628,341. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are not material to patentability. Applicant has merely reworded the patented claims and removed some limitations. It is obvious to reword patented claims and remove limitations from patented claims. Similarities between the instant claims and the patented claims are shown in the table below comparing one claim from each group of claims:
Instant claim 1
Patented claim 1
1. An apparatus comprising one or more processor units configured to identify a set of M memory addresses from a set of N input memory addresses containing at least one non-unique memory addresses, wherein N > M, and wherein the M memory addresses are to be used for accessing one or blocks of memory in parallel, the apparatus configured to:
1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address, the apparatus comprising:
perform a plurality of address comparisons of the set of N input memory addresses to generate a dataset of N classification values, wherein a subset of the N classification values identify a corresponding subset of unique addresses from the set of N input addresses;
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; a plurality of combination logic units, each combination logic unit being configured to: receive a predetermined selection of bits of the binary classification dataset;
sort at least a portion of the dataset of N classification values into a plurality of intermediary datasets, wherein each intermediary dataset comprises a first group of values identifying addresses belonging to the subset of unique addresses and a second group of values identifying addresses not belonging to the subset of unique addresses; in dependence on the first group of each of the intermediary datasets, selectively obtain a set of M memory addresses wherein the obtained set of M memory addresses comprises fewer non-unique memory addresses than the set of N input memory addresses;
and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset;
and output the obtained set of M memory addresses for accessing, in parallel, memory addresses identified by the set of M memory addresses within one or blocks of memory.
and output generating logic configured to select between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.
Conclusion
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132