DETAILED ACTION
This Office Action is in response to the application filed on 15 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in France on 29 January 2024. It is noted, however, that applicant has not filed a certified copy of the FR2400813 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, 7-11, 15-16, and 18-19 are rejected under 35 U.S.C. 103 as being obvious over Ortet (US 11,784,567 B2; hereinafter “Ortet”).
The applied reference has a common applicant, assignee, and joint inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claim 1, Ortet discloses a switched-mode power supply (Fig. 1) comprising: a first switch (20) coupling a first node for receiving a first power supply voltage (VDD) to a second node (12) for supplying a second output voltage (VOUT); a comparator (42) adapted for comparing the second output voltage (VOUT) with a third comparison voltage (VREF); wherein the comparator is adapted to, when the switched- mode power supply is operating in a pulse skipping mode, indicate that the second output voltage is different than the third comparison voltage during a part of a conduction phase of the first switch (shown in Fig 5 and further explained in Col 5 Lines 58-62: A second operating mode is called “Pulse Skipping” (PSK) mode. In this operating mode, transistor 24 is for example maintained in the off state and transistor 20 is in an on state when the output voltage VOUT is lower than a reference voltage, for example the setpoint voltage VREF).
Ortet discloses a switched-mode power supply, wherein the comparator is adapted to indicate that the second output voltage is lower than the third comparison voltage during a part of a conduction phase of the first switch, and thus does not disclose a switched-mode power supply, wherein the comparator is adapted to indicate that the second output voltage is higher than the third comparison voltage during a part of a conduction phase of the first switch. However, it would have been a matter of design choice and obvious to try and well-known in the art, before the effective filling date, to have modified the apparatus of Ortet, wherein the comparator is adapted to indicate that the second output voltage is higher, instead of lower, than the third comparison voltage to increase safety and better regulate the circuit’s output.
In re claim 2, Ortet discloses the switched-mode power supply (see rejection of claim 1 and see Fig. 5), wherein the part of the conduction phase (PWM) extends from a first time (first CLK pulse during a PWM pulse, shown in Fig. 5) subsequent to a second initial time of the conduction phase (second CLK pulse during the PWM pulse, shown in Fig. 5) and until a third final time of the conduction phase (third CLK pulse during the PWM pulse, shown in Fig. 5).
In re claim 4, Ortet discloses the switched-mode power supply (see rejection of claim 1), wherein the first switch is a PMOS-type transistor (Col 4 Lines 62-64: converter 10 comprises a first MOS (“metal oxide semiconductor”) transistor 20, preferably a PMOS (P-channel MOS transistor)).
In re claim 5, Ortet discloses the switched-mode power supply (see rejection of claim 1), wherein the comparator (42) comprises a circuit for adapting its output signal (Col 6 Lines 61-63: The comparator 42 comprises an output at which a signal is provided representing the difference between the voltage VOUT and the setpoint voltage VREF.).
In re claim 7, Ortet discloses the switched-mode power supply (see rejection of claim 1), further comprising a control circuit (32) for controlling the first switch adapted to receiving an output from the comparator (shown in Fig. 1).
In re claim 8, Ortet discloses the switched-mode power supply (see rejection of claim 1), wherein the control circuit (32) is a state machine (Col 6 Lines 1-3: The control circuit 28 comprises a circuit 32, for example a state machine, generating the control signals for the transistors 20 and 24.)
In re claim 9, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), further comprising a second switch (24) coupling a third node for receiving a fourth reference voltage (elements 18 and 42) to the second output node (12).
In re claim 10, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), wherein the second switch is an NMOS-type transistor (Col 5 Lines 4-6: converter 10 further comprises a second MOS transistor 24, preferably an NMOS transistor (N-channel MOS transistor)).
In re claim 11, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), further comprising a coil (26) coupling the first switch (20) to the second output node (12).
Claim 15 recites substantially similar limitations as claim 1, therefore will be rejected under the same rationale as claim 1.
Claim 16 recites substantially similar limitations as claim 2, therefore will be rejected under the same rationale as claim 2.
Claim 18 recites substantially similar limitations as claim 4, therefore will be rejected under the same rationale as claim 4.
Claim 19 recites substantially similar limitations as claim 5, therefore will be rejected under the same rationale as claim 5.
Claims 3 and 17 are rejected under 35 U.S.C. 103 as being obvious over Ortet (US 11,784,567 B2; hereinafter “Ortet”) in view of Matsumura et al. (US 12,671,331 B2; hereinafter “Matsumura”).
In re claim 3, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), wherein there is a conduction phase.
Ortet does not disclose wherein the part of the conduction phase has a duration greater than or equal to 20% of the duration of the conduction phase.
Whereas, Matsumura discloses the switched-mode power supply (Fig. 1 and 6-7), wherein the part of the conduction phase has a duration greater than or equal to 20% of the duration of the conduction phase (Col 10 Line 46-49: Therefore, during the extended on-time operation mode, the duty cycle of the ON signal keeps increasing when VIN keeps dropping towards VOUT and may approach 100%).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified apparatus of Ortet such that part of the conduction phase has a duration greater than or equal to 20% of the duration of the conduction phase as shown by Matsumura. The selection of increasing the conduction phase duration would be a routine matter to the person of ordinary skill to increase output, as taught by Matsumura, cited above.
Claim 17 recites substantially similar limitations as claim 3, therefore will be rejected under the same rationale as claim 3.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being obvious over Ortet (US 11,784,567 B2; hereinafter “Ortet”) in view of Scaldaferri et al. (US 2010/0237845 A1; hereinafter “Scaldaferri”).
In re claim 6, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), the circuit for adapting its output signal.
Ortet does not disclose wherein the circuit for adapting its output signal is an OR-type logic gate.
Whereas, Scaldaferri discloses a similar switched-mode power supply (Fig. 5), wherein the circuit for adapting its output signal is an OR-type logic gate (58).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Ortet such that the circuit for adapting its output signal is an OR-type logic gate as shown by Scaldaferri. The selection of an OR-type logic gate would be a routine matter to the person of ordinary skill to improve regulation and control, as taught by Scaldaferri, cited above.
Claim 20 recites substantially similar limitations as claim 6, therefore will be rejected under the same rationale as claim 6.
Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Ortet (US 11,784,567 B2; hereinafter “Ortet”) in view of Nicolosi et al. (US 2015/0301092; hereinafter “Nicolosi”).
In re claim 12, Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1), detecting whether a current flowing through the coil is zero. (Col 5 Lines 65-67: Such an operating mode is implemented, for example, when the current drawn by the load is low. This operating mode is an asynchronous operating mode.)
Ortet does not disclose a zero-current detection circuit.
Whereas, Nicolosi discloses a switched-mode power supply (Figs. 4 and 6-7), further comprising a zero-current detection circuit (9) adapted to detecting whether a current flowing through the coil is zero (Abstract: circuit indicating zero crossings of the inductor current.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Ortet with a zero-current detection circuit as shown by Nicolosi. The selection of a zero-current detection circuit would be a routine matter to the person of ordinary skill to improve safety and performance, as taught by Nicolosi, cited above.
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 13, Ortet (US 11,784,567 B2; hereinafter “Ortet”) is considered the closest prior art on record. Ortet discloses the switched-mode power supply (see rejection of claim 1 and Fig. 1). Despite the similarity, Ortet does not disclose wherein the switched-mode power supply is adapted to transition from a continuous conduction mode to a pulse skipping mode when the second output voltage is higher than the third comparison voltage and the current flowing through the coil is zero.
The second closest prior art on record is Nicolosi et al. (US 2015/0301092; hereinafter “Nicolosi”). Nicolosi discloses wherein the switched-mode power supply (Figs. 4 and 6-7) is adapted to transition from a continuous conduction mode to a pulse skipping mode when the output voltage is higher than a voltage (Pg. 8, [0121]: the comparator circuit 115 generates a rising edge of the signal v.sub.skip whenever the output voltage v.sub.out overcomes the first output threshold V.sub.out_hi) and the current flowing through the coil is zero (Pg. 3, [0046]: when the current I.sub.LOAD approaches to zero, the second and the fourth phase are skipped). Despite the similarity of the references with the Applicant’s claimed invention, Nicolosi does not reasonably teach the recited feature of the apparatus comprising: “the switched-mode power supply is adapted to transition from a continuous conduction mode to a pulse skipping mode when the second output voltage is higher than the third comparison voltage and the current flowing through the coil is zero,” in combination with the remaining limitations recited in preceding claim as a whole. Further, the additional prior art on record does not suggest an obvious modification to the apparatus of Ortet in view of Nicolosi that would produce the claimed invention in its entirety.
Claim 14 depends on claim 13 and therefore contains allowable subject matter for the same rationale stated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Yun et al. US 2023/0327548 A1 “DC-TO-DC CONVERTER WITH PULSE SKIPPING FUNCTION AND ON-TIME CONTROL FUNCTION, AND ELECTRONIC DEVICES INCLUDING THE SAME”
Wei et al. US 2023/0170805 A1 “DC-DC CONVERTER AND CONTROL METHOD THEREOF”
Zhang US 12,476,544 B2 “SWITCHING CONVERTER”
Schmidt et al. US 2011/0193539 A1 “Switching Regulator With Offset Correction”
Chen et al. US 2018/0269787 A1 “SYSTEM AND METHOD FOR CONTROLLING SWITCHING POWER SUPPLY”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICOLAS ALDEN CHAPA MILLS/ Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
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