Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/28/2026 has been entered.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as unpatentable over CHOI (US 20100182223 A1) in view of YANG (US 20130015448 A1).
Regarding claim 1, CHOI (e.g., Figs. 1-3) discloses a display having an array of pixels (Fig. 1; an array of pixels 300), the display comprising:
thin-film transistor structures (Fig. 3; TFT structures) for the array of pixels, wherein the thin-film transistor structures include a silicon transistor (Fig. 3; silicon TFT M2; [0030] and [0037]) having a first channel (channel region 30) and a first gate (gate 15) and an oxide transistor (Fig. 3; oxide TFT M1; [0030] and [0037]) having a second channel (channel region 18) and a second gate (gate 14);
a first dielectric layer (Fig. 3; dielectric layer 318) overlapping the first channel (channel region 30) or the second channel (channel region 18);
a second dielectric layer (Fig. 3; dielectric layer 316) that is interposed between the first dielectric layer (dielectric layer 318) and the first channel (channel region 30) or the second channel (channel region 18);
a third dielectric layer (Fig. 3; dielectric layer 22) that is interposed between the second dielectric layer (dielectric layer 316) and the first channel (channel region 30) or the second channel (channel region 18); and
a fourth dielectric layer (Fig. 3; dielectric layer 16) that is interposed between the third dielectric layer (dielectric layer 22) and the first channel (channel region 30), the second channel (channel region 18), the first gate (gate 15), and the second gate (gate 14), and
a conductive layer (conductive layer including source electrodes and drain electrodes 20a-20d) interposed between the second and third dielectric layers (dielectric layers 316 and 22).
CHOI discloses a conductive layer (source-drain electrode layer including source electrodes and drain electrodes 20a-20d) interposed between the second and third dielectric layers (dielectric layers 316 and 22), but does not disclose the conductive source-drain electrode layer is a metal layer. However, the claimed feature is well known in the field. As a reference, YANG (e.g., Figs. 4-7) discloses a display device similar to that disclosed by CHOI, wherein the thin-film transistor structures include a silicon transistor (Figs. 4 and 6; silicon TFT 301 or 501) and an oxide transistor (Figs. 4 and 6; oxide TFT 302 or 502) and a source-drain electrode layer including source electrodes and drain electrodes 241-244 are made of metal material ([0027]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from YANG to the transistor circuit of the display device of CHOI. The combination/motivation would be to enhance the conductivity of the thin-film transistors of the display device.
Regarding claim 2, CHOI in view of YANG discloses the display of claim 1, CHOI (e.g., Fig. 3) discloses wherein the second dielectric layer (dielectric layer 316) is interposed between the first dielectric layer (dielectric layer 318) and both the first channel (channel region 30) and the second channel (channel region 18).
Regarding claim 3, CHOI in view of YANG discloses the display of claim 1, CHOI (e.g., Fig. 3) discloses wherein the third dielectric layer (dielectric layer 22) is interposed between the second dielectric layer (dielectric layer 316) and both the first channel (channel region 30) and the second channel (channel region 18).
Regarding claim 4, CHOI in view of YANG discloses the display of claim 1, CHOI (e.g., Fig. 3) discloses wherein first channel is a polysilicon channel (silicon TFT M2 including a polysilicon channel; [0037]-[0042]) and wherein the second channel comprises a semiconducting oxide layer (oxide TFT M1 including an oxide channel; [0037]-[0042]).
Regarding claim 6, CHOI in view of YANG discloses the display of claim 1, YANG (e.g., Figs. 4-7) discloses an additional metal layer that forms the first gate or the second gate ([0025]; metal gate 18).
Regarding claim 7, CHOI in view of YANG discloses the display of claim 1, YANG (e.g., Figs. 4-7) discloses wherein the metal layer forms a contact for the oxide transistor (source-drain metal electrode layer 243/244 connected to the oxide TFT 302 or 502).
Regarding claim 8, CHOI in view of YANG discloses the display of claim 1, YANG (e.g., Figs. 4-7) discloses wherein the metal layer forms a contact for the silicon transistor (source-drain metal electrode layer 241/242 connected to the oxide TFT 301 or 501).
Regarding claim 9, CHOI in view of YANG discloses the display of claim 1, YANG (e.g., Figs. 4-7) discloses wherein the first and second dielectric layers are first and second planar dielectric layers (the first and second dielectric layers 318 and 316 are planar layers).
5. Claim 5 is rejected under 35 U.S.C. 103 as unpatentable over CHOI (US 20100182223 A1) in view of YANG (US 20130015448 A1) and further in view of AH (KR 20110071698 A) or SEO (US 20050218794 A1).
Regarding claim 5, CHOI in view of YANG discloses the display of claim 1, but does not disclose an electrode that is electrically connected to the second channel, wherein the first dielectric layer is interposed between the electrode and the second dielectric layer. However, AH (e.g., Fig. 8) discloses an OLED display device similar to that disclosed by CHOI and YANG, further comprising: an electrode (electrode 221) that is electrically connected to the second channel (Fig. 8; channel region 212b of oxide TFT TR2), wherein the first dielectric layer (insulating layer 218 is a multiple layer structure comprising a first insulating layer 218; Page 9, Paragraph 5) is interposed between the electrode (electrode 221) and the second dielectric layer (insulating layer 218 is a multiple layer structure comprising a second insulating layer 218; Page 9, Paragraph 5). As another reference, SEO (e.g., Fig. 2) discloses an OLED display device, wherein the first dielectric layer (first insulating layer 19-2) is interposed between the electrode (electrode 21) and the second dielectric layer (second insulating layer 19-1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by AH and SEO to an OLED display device of CHOI in view of YANG. The combination/motivation would be to enhance the insulation performance and provide an insulating structure to improve the characteristic of a thin-film transistor of a display device.
Allowable Subject Matter
6. Claims 10-20 are allowed. The following is an examiner’s statement of reasons for allowance: The present invention is directed to an OLED display. The closet prior arts, CHOI (US 20100182223 A1), YANG (US 20130015448 A1), AH (KR 20110071698 A), SEO (US 20050218794 A1), and KIM (US 20140197382 A1), individually or in combination, discloses an OLED display similar to the claimed invention, comprising: thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate; a first dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor; a second dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor; a third dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer; and a fourth dielectric layer between the third dielectric layer and both the first gate and the second gate, but fails to teach a first metal layer that forms the first gate or the second gate; a second metal layer that at least partially overlaps the second and third dielectric layers; and a third metal layer that at least partially overlaps the second and third dielectric layers, wherein the second metal layer is interposed between the first metal layer and the third metal layer. In addition, the closet prior arts discloses thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, wherein the oxide transistor comprises a semiconducting oxide layer and a second gate; a first electrode that is electrically connected to the semiconducting oxide layer; a capacitor coupled to the thin-film transistor structures, wherein the capacitor comprises a second electrode; a first layer of metal that is interposed between first and second dielectric layers of five dielectric layers and the polysilicon channel; and a second layer of metal that forms the second electrode and that forms the first or second gate, but fail to teach the five dielectric layers that are interposed between the first electrode and the polysilicon channel, wherein third, fourth, and fifth dielectric layers of the five dielectric layers are interposed between the first layer of metal and the second layer of metal.
Response to Arguments
7. Regarding claim 1, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments, the references of CHOI (US 20100182223 A1) and YANG (US 20130015448 A1) have been used for new ground rejection.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
