Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 04/10/2026 has been entered. Claims 1-6, 8-10, 12-15 and 17-20 have been amended. Rejection of claim 5 under 35 U.S.C. 112(a) (pre-AIA 35 U.S.C. 112, first paragraph) is withdrawn.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-7, 17-18, and 20 are rejected under 35 U.S.C. 103 as unpatentable over AH (KR 20110071698 A) in view of SEO (US 20050218794 A1).
Regarding claim 1, AH (e.g., Figs. 5 and 8) discloses a display having an array of pixels (Fig. 5; an array of pixels), the display comprising:
thin-film transistor structures (Fig. 8; TFT structures) for the array of pixels, wherein the thin-film transistor structures include a silicon transistor (Fig. 8; silicon TFT TR3; Page 11, Paragraph 4) having a first channel (channel region 312) and an oxide transistor (Fig. 8; oxide TFT TR2; Page 8, Paragraph 5) having a second channel (channel region 212b);
a first dielectric layer (Fig. 8; insulating layer 218 is a multiple layer structure comprising a first insulating layer 218; Page 9, Paragraph 5) overlapping the first channel (channel region 312) or the second channel (channel region 212b);
a second dielectric layer (Fig. 8; insulating layer 218 is a multiple layer structure comprising a second insulating layer 218; Page 9, Paragraph 5) that is interposed between the first dielectric layer (insulating layer 219) and the first channel (channel region 312) or the second channel (channel region 212b);
a third dielectric layer (Fig. 8; insulating layer 215; Page 8, Paragraph 7) that is interposed between the second dielectric layer (insulating layer 218) and the first channel (channel region 312) or the second channel (channel region 212b); and
a fourth dielectric layer (Fig. 8; insulating layer 213; Page 8, Paragraph 6) that is interposed between the third dielectric layer (insulating layer 215) and both the first channel (channel region 312) and the second channel (channel region 212b).
AH (e.g., Fig. 8) discloses the dielectric layer 218 is a multiple layer structure comprising a first dielectric layer 218 and a second dielectric layer 218. Similar to AH, SEO (e.g., Fig. 2) discloses an OLED display device, wherein the dielectric layer 19 is a multiple layer structure comprising a first dielectric layer 19-2 and a second dielectric layer 19-1. SEO (e.g., Fig. 2) also discloses a third dielectric layer 16 and a fourth dielectric layer 14. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by SEO with AH to an OLED display device. The combination/motivation would be to enhance the insulation performance and provide an insulating structure to improve the characteristic of a thin-film transistor of a display device.
Regarding claim 2, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses wherein the second dielectric layer (second insulating layer 218 or 19-1) is interposed between the first dielectric layer (first insulating layer 218 or 19-2) and both the first channel (channel region 312) and the second channel (channel region 212b).
Regarding claim 3, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses wherein the third dielectric layer (insulating layer 215) is interposed between the second dielectric layer (second insulating layer 218) and both the first channel (channel region 312) and the second channel (channel region 212b).
Regarding claim 4, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses wherein first channel is a polysilicon channel (Fig. 8; silicon TFT TR3 including a polysilicon channel 312; Page 11, Paragraph 4) and wherein the second channel comprises a semiconducting oxide layer (Fig. 8; oxide TFT TR2 including an oxide channel 212b; Page 8, Paragraph 5).
Regarding claim 5, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses further comprising: an electrode (electrode 221) that is electrically connected to the second channel (Fig. 8; channel region 212b of oxide TFT TR2), wherein the first dielectric layer (first insulating layer 218 or 19-2) is interposed between the electrode (electrode 221) and the second dielectric layer (second insulating layer 218 or 19-1).
Regarding claim 6, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses further comprising: a first metal layer (metal connecting layer 221 disposed in a via hole in first and second insulating layers 218 and connected between anode electrode 221 and TFT TR2; Fig. 8 and Page 10, Paragraph 3), wherein the first metal layer is interposed between the first dielectric layer (first insulating layer 218) and the first channel (channel region 312 of TFT TR3) or the second channel (channel region 212b of TFT TR2). Similar to AH, SEO also discloses wherein the first metal layer (Fig. 2 and [0017]; metal connecting layer 21-1 disposed in a via hole in first and second insulating layers 19-2 and 19-1 and connected between anode electrode 21-1 and TFT) is interposed between the first dielectric layer (first insulating layer 19-2) and the first channel (channel region 12 of TFT).
Regarding claim 7, AH in view of SEO discloses the display of claim 1, AH (e.g., Fig. 8) discloses wherein the first metal layer forms a contact for the oxide transistor (the metal connector 221 connected to the oxide TFT TR2).
Regarding claim 9, AH in view of SEO discloses the display of claim 1, SEO (e.g., Fig. 2) discloses wherein the first and second dielectric layers are first and second planar dielectric layers (the first and second dielectric layers 19-1 and 19-2 are planar layers).
Regarding claim 17, AH (e.g., Figs. 5 and 8) discloses a display having an array of pixels (Fig. 5; an array of pixels), the display comprising:
thin-film transistor structures (Fig. 8; TFT structures) for the array of pixels, wherein the thin-film transistor structures include a silicon transistor (Fig. 8; silicon TFT TR3; Page 11, Paragraph 4) and an oxide transistor (Fig. 8; oxide TFT TR2; Page 8, Paragraph 5), wherein the silicon transistor comprises a polysilicon channel and a first gate (Fig. 8; silicon TFT TR3 comprising a polysilicon channel 312 and a first gate 314; Page 11, Paragraph 4), wherein the oxide transistor comprises a semiconducting oxide layer and a second gate (Fig. 8; oxide TFT TR2 comprises a semiconducting oxide layer 212b and a second gate 214b; Page 8, Paragraph 5);
an electrode (electrode 221) that is electrically connected to the semiconducting oxide layer (oxide layer 212b of TFT TR2); and
five dielectric layers (insulating layer 218 is a multiple layer structure comprising a first insulating layer 218 and a second insulating layer 218, insulating layer 215, insulating layer 213, insulating layer 211; Page 8, Paragraphs 4 and 6-7, and Page 9, Paragraph 5) that are interposed between the electrode (electrode 221) and the polysilicon channel (polysilicon channel 312 of TFT TR3);
a first layer of source-drain electrodes (source electrode 216b-drain electrode 217b) that is interposed between first and second dielectric layers of the five dielectric layers (insulating layer 218 is a multiple layer structure comprising a first insulating layer 218 and a second insulating layer 218) and the polysilicon channel (polysilicon channel 312 of TFT TR3); and
a second layer of gate electrode that forms the first or second gate (gate electrode 314 of TFT TR3), wherein third, fourth, and fifth dielectric layers (insulating layer 215, insulating layer 213, insulating layer 211) of the five dielectric layers are interposed between the first layer of source-drain electrodes (source electrode 216b-drain electrode 217b) and the second layer of gate electrode (gate electrode 314 of TFT TR3).
AH (e.g., Fig. 8) discloses the dielectric layer 218 is a multiple layer structure comprising a first dielectric layer 218 and a second dielectric layer 218. Similar to AH, SEO (e.g., Fig. 2) discloses an OLED display device, wherein the dielectric layer 19 is a multiple layer structure comprising a first dielectric layer 19-2 and a second dielectric layer 19-1. SEO (e.g., Fig. 2) also discloses a third dielectric layer 16 and a fourth dielectric layer 14. In addition, AH discloses a first layer of source-drain electrodes (source electrode 216b-drain electrode 217b) and a second layer of gate electrode that forms the second gate (gate electrode 314), but does not disclose the first layer of source-drain electrodes and the second layer of gate electrode are metal layers. However, it is well known that metal materials are used to form gate electrode, source electrode, and drain electrode of a transistor. As a reference, SEO discloses a first layer of source-drain electrodes (source/drain electrodes 58-1/58-2) is formed of metal material ([0075]), and a second layer of gate electrode (gate electrode 55a) is formed of metal material ([0072]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by SEO with AH to an OLED display device. The combination/motivation would be to enhance the insulation performance and electrical conductivity to improve the characteristic of a thin-film transistor of a display device.
Regarding claim 18, AH in view of SEO discloses the display of claim 17, AH (e.g., Fig. 8) discloses wherein the first layer of conductive material that forms a source-drain contact for the silicon transistor or the oxide transistor (source electrode 216b-drain electrode 217b of TFT TR2). SEO further discloses SEO discloses the first layer of source-drain electrodes (source/drain electrodes 58-1/58-2) is formed of metal material ([0075]), Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by SEO with AH to an OLED display device for the same reason above.
Regarding claim 20, AH in view of SEO discloses the display of claim 17, SEO (e.g., Fig. 2) discloses wherein the second dielectric layer (insulating layer 19-2) is an organic layer ([0013]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by SEO with AH to an OLED display device for the same reason above.
5. Claims 10 and 13-15 are rejected under 35 U.S.C. 103 as unpatentable over CHOI (US 20100182223 A1) in view of SEO (US 20050218794 A1).
Regarding claim 10, CHOI (e.g., Figs. 1-3) discloses a display having an array of pixels (Fig. 1; an array of pixels 300), the display comprising:
thin-film transistor structures (Fig. 3; TFT structures) for the array of pixels, wherein the thin-film transistor structures include a silicon transistor (silicon transistor M2; [0030]) and an oxide transistor (oxide transistor M1; [0030]), wherein the silicon transistor comprises a polysilicon channel and a first gate (Fig. 3 and [0030], [0038]-[0039]; silicon transistor M2 comprising a polysilicon channel 30c and a gate 15), and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate (Fig. 3 and [0030], [0041]-[0042]; oxide transistor M1 comprising a semiconducting oxide layer 18 and a gate 14);
a first dielectric layer (Fig. 3; insulating layer 318) that at least partially overlaps the silicon transistor (silicon transistor M2) or the oxide transistor (oxide transistor M1);
a second dielectric layer (Fig. 3; insulating layer 316) that at least partially overlaps the silicon transistor (silicon transistor M2) or the oxide transistor (oxide transistor M1);
a third dielectric layer (Fig. 3; insulating layer 22) that at least partially overlaps the silicon transistor (silicon transistor M2) or the oxide transistor (oxide transistor M1), wherein the second dielectric layer (Fig. 3; insulating layer 316) is between the first dielectric layer (insulating layer 318) and the third dielectric layer (insulating layer 22); and
a fourth dielectric layer (Fig. 3; insulating layer 16) between the third dielectric layer (insulating layer 22) and both the first gate (gate 15) and the second gate (gate 14).
Although CHOI does not expressly disclose, it is obvious to one skilled in the art that the first layer 318, the second layer 316, the third layer 22 are insulating layer. The examiner further cites SEO as a reference. SEO (e.g., Fig. 2) discloses a display device, comprising a first dielectric layer (insulating layer 22; [0056]), a second dielectric layer (insulating layer 19; [0013]), and a third dielectric layer (insulating layer 16; [0049]), corresponding to the first layer 318, the second layer 316, the third layer 22, respectively. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by SEO with CHOI to an OLED display device. The combination/motivation would be to enhance the insulation performance and provide an insulating structure to improve the characteristic of a thin-film transistor of a display device.
Regarding claim 13, CHOI in view of SEO discloses the display of claim 11, CHOI (e.g., Figs. 1-3) discloses wherein the fourth dielectric layer is an interlayer dielectric (Fig. 3; interlayer insulating layer 16; [0041]).
Regarding claim 14, CHOI in view of SEO discloses the display of claim 11, CHOI (e.g., Figs. 1-3) discloses wherein the second dielectric layer (Fig. 3; insulating layer 316) at least partially overlaps both the silicon transistor (silicon transistor M2) and the oxide transistor (oxide transistor M1).
Regarding claim 15, CHOI in view of SEO discloses the display of claim 11, CHOI (e.g., Figs. 1-3) discloses wherein the third dielectric layer (Fig. 3; insulating layer 22) at least partially overlaps both the silicon transistor (silicon transistor M2) and the oxide transistor (oxide transistor M1).
6. Claims 8 and 19 are rejected under 35 U.S.C. 103 as unpatentable over AH (KR 20110071698 A) in view of SEO (US 20050218794 A1) and further in view of KIM (US 20140197382 A1).
Regarding claim 8, AH in view of SEO discloses the display of claim 1, but does not disclose wherein the first metal layer forms a contact for the silicon transistor. However, KIM (e.g., Figs. 6 and 9) discloses a display device similar to that disclosed by AH, comprising a silicon transistor (silicon transistor TRs; [0092] and [0096]) and an oxide transistor (oxide transistor TRd; [0093] and [0100]), wherein the first metal layer forms a contact for the silicon transistor (conductor 160 disposed in a via hole in insulating layers 150, corresponding to metal connecting layer 221 as taught by AH, is electrically connected to silicon TFT TRs). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by KIM with AH in view of SEO to an OLED display device. The combination/motivation would be using different type transistors to improve the performance and characteristic of the pixel circuits of the display device.
Regarding claim 19, AH in view of SEO discloses the display of claim 17, but does not disclose the light shield as claimed. further comprising: However, Kim (Fig. 9) discloses a display device, comprising a silicon transistor (silicon transistor TRs; [0092] and [0096]) and an oxide transistor (oxide transistor TRd; [0093] and [0100]); a substrate (substrate 100); and a light shield ([005; light shield) that is interposed between the substrate (substrate 100) and at least one of the silicon transistor and the oxide transistor (oxide transistor; [0059]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM to the display device of AH in view of SEO to block the light traveling to the oxide semiconductor active layer of the oxide transistor.
7. Claim 16 is rejected under 35 U.S.C. 103 as unpatentable over CHOI (US 20100182223 A1) in view of SEO (US 20050218794 A1) and further in view of HEO (US20130056735 A1).
Regarding claim 16, CHOI in view of SEO discloses the display of claim 11, SEO discloses (e.g., Fig. 2) discloses wherein the second dielectric layer is second organic dielectric layer ([0013]), but does not disclose wherein the third dielectric layer is third organic dielectric layer. However, HEO discloses a display device, wherein the third dielectric layer is third organic dielectric layer ([0079]; organic interlayer insulating layer 206). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by HEO to an OLED display device of CHOI in view of SEO. The combination/motivation would be to enhance the insulation performance and provide an insulating structure to improve the characteristic of a thin-film transistor of a display device.
Allowable Subject Matter
8. Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The present invention is directed to an OLED display. The closet prior arts, AH (KR 20110071698 A), CHOI (US 20100182223 A1), SEO (US 20050218794 A1), and KIM (US 20140197382 A1), individually or in combination, discloses an OLED display similar to the claimed invention, comprising: thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate; a first dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor; a second dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor; a third dielectric layer that at least partially overlaps the silicon transistor or the oxide transistor, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer; and a fourth dielectric layer between the third dielectric layer and both the first gate and the second gate, but fails to teach a first metal layer that forms the first gate or the second gate; a second metal layer that at least partially overlaps the second and third dielectric layers; and a third metal layer that at least partially overlaps the second and third dielectric layers, wherein the second metal layer is interposed between the first metal layer and the third metal layer.
Response to Arguments
9. Regarding claims 1, 10, and 17, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments, the references of AH (KR 20110071698 A), CHOI (US 20100182223 A1), and SEO (US 20050218794 A1) have been used for new ground rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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