Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention. (FP 7.30.01)
3. Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. (FP 7.31.01).
Claim 5 depends on claim 1. Claim 1 recites the limitations “a first dielectric layer; a second dielectric layer that is interposed between the first dielectric layer and the silicon transistor or the oxide transistor; and a third dielectric layer that is interposed between the second dielectric layer and the silicon transistor or the oxide transistor”, and claim 5 further recites the limitations “an electrode that is electrically connected to the semiconducting oxide layer, wherein the first dielectric layer is interposed between the electrode and the second dielectric layer”. According to claims 1 and 5 and the specification, there are three dielectric layers (the first dielectric layer, the second dielectric layer, and the third dielectric layer) interposed between the electrode (anode electrode) and the silicon transistor and the oxide transistor. However, the claimed features are not supported by the original disclosure and therefore constitutes new matter (See also 37 C.F.R. 1.121(f), MPEP 608.04, 706.03(o)). Nowhere in the specification and drawings disclose more than two dielectric layers interposed between the electrode (anode electrode) and the silicon transistor and the oxide transistor.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 4-5, 9-10, and 13-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 20140299842 A1).
Regarding claim 1, Kim (e.g., Figs. 1-2 and 4) discloses a display having an array of pixels (Fig. 1; an array of pixels), the display comprising: thin-film transistor structures (Figs. 2 and 4; thin-film transistor structures) for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor (Fig. 4 and [0126]-[0127]; e.g., a silicon TFT T1 and an oxide TFT T6); a first dielectric layer (layer PL3); a second dielectric layer (layer PL2) that is interposed between the first dielectric layer (layer PL3) and the silicon transistor (silicon TFT T1) or the oxide transistor; and a third dielectric layer (layer PL1) that is interposed between the second dielectric layer (layer PL2) and the silicon transistor (silicon TFT T1) or the oxide transistor.
Regarding claim 4, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 1, wherein the silicon transistor comprises a polysilicon channel and a first gate and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate (Fig. 4 and [0126]-[0127]; e.g., a silicon TFT T1 including a polysilicon channel and a gate G1 and an oxide TFT T6 including a semiconducting oxide layer and a gate G6).
Regarding claim 5, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 4, further comprising: an electrode (anode EL1) that is electrically connected to the semiconducting oxide layer (semiconducting oxide layer of oxide TFT T6), wherein the first dielectric layer (layer PL3) is interposed between the electrode (anode EL1) and the second dielectric layer (layer PL2).
Regarding claim 9, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 1, wherein the second and third dielectric layers are second and third planar dielectric layers (layer PL2 and layer PL1 are planar layers).
Regarding claim 10, Kim (e.g., Figs. 1-2 and 4) discloses a display having an array of pixels (Fig. 1; an array of pixels), the display comprising: thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures Figs. 2 and 4; thin-film transistor structures) include a silicon transistor and an oxide transistor (Fig. 4 and [0126]-[0127]; e.g., a silicon TFT T1 and an oxide TFT T6), wherein the silicon transistor comprises a polysilicon channel and a first gate, and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate (Fig. 4 and [0126]-[0127]; e.g., a silicon TFT T1 including a polysilicon channel and a gate G1 and an oxide TFT T6 including a semiconducting oxide layer and a gate G6); a first dielectric layer (layer PL3) that at least partially overlaps the silicon transistor or the oxide transistor (silicon TFT T1 and oxide TFT T6); a second dielectric layer (layer PL2) that at least partially overlaps the silicon transistor or the oxide transistor (silicon TFT T1 and oxide TFT T6); and a third dielectric layer (layer PL1) that at least partially overlaps the silicon transistor or the oxide transistor (silicon TFT T1 and oxide TFT T6).
Regarding claim 13, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 10, wherein the first dielectric layer (layer PL3) at least partially overlaps both the silicon transistor and the oxide transistor (silicon TFT T1 and oxide TFT T6).
Regarding claim 14, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 13, wherein the second dielectric layer (layer PL2) at least partially overlaps both the silicon transistor and the oxide transistor (silicon TFT T1 and oxide TFT T6).
Regarding claim 15, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 14, wherein the third dielectric layer (layer PL1) at least partially overlaps both the silicon transistor and the oxide transistor (silicon TFT T1 and oxide TFT T6).
Regarding claim 16, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 10, wherein the second and third dielectric layers (layers PL1 and PL2) are second and third organic dielectric layers ([0116] and [0118]).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2-3 are rejected under 35 U.S.C. 103 as unpatentable over Kim (US 20140299842 A1) in view of Umezaki (US 20140070880 A1).
Regarding claim 2, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 1, but does not disclose wherein the second dielectric layer is interposed between the first dielectric layer and both the silicon transistor and the oxide transistor. However, Umezaki Umezaki (e.g., Figs. 13-14) discloses a display device comprising: a first dielectric layer (layer 211; [0139]); a second dielectric layer (layer 210 or layers 210 and 217; [0139] and [0150]), and a third dielectric layer (layer 209; [0139]), wherein the second dielectric layer (e.g., Figs. 13A-13B; layer 210 or layers 210 and 217) is interposed between the first dielectric layer (layer 211) and the oxide transistor (oxide transistor 201; [0137]). Since Kim discloses the display device, wherein the oxide TFTs are disposed on top of the silicon TFTs, the combination of Kim and Umezaki teaches wherein the second dielectric layer is interposed between the first dielectric layer and both the silicon transistor and the oxide transistor. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by Umezaki to the display device of Kim. The combination/motivation would be to provide an insulating structure to enhance the insulation performance and improve the characteristic of a thin-film transistor of a display device.
Regarding claim 3, Kim in view of Umezaki discloses the display of claim 1, Umezaki (e.g., Figs. 13-14) discloses wherein the third dielectric layer (e.g., Figs. 13A-13B; layer 209) is interposed between the second dielectric layer (e.g., Figs. 13A-13B; layer 210 or layers 210 and 217) and both the silicon transistor and the oxide transistor (e.g., Figs. 13A-13B; oxide transistor 201). Since Kim discloses the display device, wherein the oxide TFTs are disposed on top of the silicon TFTs, the combination of Kim and Umezaki teaches Since Kim discloses the display device, wherein the oxide TFTs are disposed on top of the silicon TFTs, the combination of Kim and Umezaki teaches wherein the third dielectric layer is interposed between the second dielectric layer and both the silicon transistor and the oxide transistor. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the multiple insulation structures as taught by Umezaki to the display device of Kim. The combination/motivation would be to enhance the insulation performance and provide an insulating structure to improve the characteristic of a thin-film transistor of a display device.
8. Claims 11-12 are rejected under 35 U.S.C. 103 as unpatentable over Kim (US 20140299842 A1) in view of Sagawa (US 20080246403 A1).
Regarding claim 11, Kim (e.g., Figs. 1-2 and 4) discloses the display of claim 10, further comprising: a first conductive layer that forms the first gate or the second gate (transistor T1 comprising a gate electrode); a second conductive layer that at least partially overlaps the second and third dielectric layers; and a third conductive layer that at least partially overlaps the second and third dielectric layers (capacitor C1 or C2 comprising a second conductive electrode CE1 or CE3 and a third conductive electrode CE2 or CE4, which overlap with layer PL2 and PL1), wherein the second metal layer is interposed between the first conductive layer and the third conductive layer (second conductive electrode CE1 or CE3 is interposed between gate electrode G1 and third conductive electrode CE2 or CE4). Kim does not disclose the first conductive layer (or gate electrode layer), the second conductive layer (capacitor electrode layer CE1 or CE3), and the third conductive layer (capacitor electrode layer CE2 or CE4) are metal layers. However, Sagawa (Figs. 1-3 and 11-12) discloses a display device similar to that disclosed by Kim, wherein a gate electrode layer of a transistor and a first and a second electrode layers of a capacitor are formed of metal layers (Figs. 11-12 and [0119]-[0120]; metal gate electrode and metal capacitor electrodes). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Sagawa to form the transistors and capacitors of the pixel circuit of the display device of Park using metallic conductive materials.
Regarding claim 12, Kim in view of Sagawa discloses the display of claim 11, wherein the second and third metal layers (electrode layers of capacitor C1 or C2) at least partially overlap the first dielectric layer (layer PL3).
9. Claims 1, 6-9, and 17-20 are rejected under 35 U.S.C. 103 as unpatentable over Park (US 20080116457 A1) in view of Kim (US 20140197382 A1) and/or Kang (US 20110012104 A1).
Regarding claim 1, Park (e.g., Figs. 5-7) discloses a display having an array of pixels (Fig. 6; an array of pixels), the display comprising: thin-film transistor structures (Fig. 6; thin-film transistor structures) for the array of pixels, wherein the thin-film transistor structures include a first transistor and a second transistor (Fig. 6; switching transistor 101 (Tsw) and driving transistor 102 (Tdr)); a first dielectric layer (layer 92); a second dielectric layer (layer 72) that is interposed between the first dielectric layer (layer 92) and the first transistor or the oxide transistor (Fig. 6; switching transistor 101 (Tsw) and driving transistor 102 (Tdr)); and a third dielectric layer (layer 62) that is interposed between the second dielectric layer (layer 72) and the silicon transistor or the oxide transistor (switching transistor 101 (Tsw) and driving transistor 102 (Tdr)).
Park (e.g., Figs. 5-7) discloses the first transistor 101 is a silicon transistor ([0031]), but does not disclose the second transistor is an oxide transistor. However, Kim (e.g., Figs. 1-3, 6, 9, and 12) discloses a display device essentially same as that disclosed by Park, wherein the thin-film transistor structures include a first transistor and a second transistor (switching transistor TRs and driving transistor TRd); wherein the first transistor and the second transistor can be silicon transistors and/or oxide transistors (e.g., Figs. 3, 6, 9, and 12). As an example, Kim (Fig. 9) discloses the first transistor TRs is a silicon transistor ([0092] and [0096]) and the second transistor TRd is an oxide transistor ([0093] and [0100]). As another reference, Kang (e.g., Figs. 1-3, 6, 9, and 12) discloses a display device essentially same as that disclosed by Park and Kim, comprising a first transistor (switching transistor M2) and a second transistor (driving transistor M1); wherein the second transistor M1 is an oxide transistor ([0039] and [0046]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Kim and Kang to the display device of Park. The combination/motivation would be to an alternative design choice by using different type transistors to improve the performance and characteristic of the pixel circuits of the display device.
Regarding claim 6, Park in view of Kim or Kang discloses the display of claim 1, further comprising: a first metal layer, wherein the first metal layer is interposed between the third dielectric layer and the silicon transistor or the oxide transistor (Kim’s Fig. 6 and [0051], a part of a metal layer 80 is interposed between dielectric layer 62 and the driving transistor 102 and connected to the drain 41D of the driving transistor 102; Kang’s Fig. 3 teaches similar features of connection to driving transistor M1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Kim and Kang to the display device of Park for the same reason above.
Regarding claim 7, Park in view of Kim or Kang discloses the display of claim 1, wherein the first metal layer forms a contact for the oxide transistor (Kim’s Fig. 6 and [0051], a part of a metal layer 80 is interposed between dielectric layer 62 and the driving transistor 102 and connected to the drain 41D of the driving transistor 102; Kang’s Fig. 3 teaches similar features of connection to driving transistor M1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Kim and Kang to the display device of Park for the same reason above.
Regarding claim 8, Park in view of Kim or Kang discloses the display of claim 1, Park (e.g., Figs. 5-7) discloses the display further comprising: a second metal layer (metal layer 70), wherein the second metal layer is interposed between the second dielectric layer (layer 72) and the silicon transistor (switching transistor 101) or the oxide transistor and wherein the second metal layer forms a contact for the silicon transistor (metal layer 70 forms a contact with the drain 40D of the silicon transistor 101).
Regarding claim 9, Park in view of Kim or Kang discloses the display of claim 1, Park (e.g., Figs. 5-7) discloses wherein the second and third dielectric layers are second and third planar dielectric layers (layer 72 and layer 62 are planar layers).
Regarding claim 17, Park (e.g., Figs. 5-7) discloses a display having an array of pixels (Fig. 6; an array of pixels), the display comprising: thin-film transistor structures (Fig. 6; thin-film transistor structures) for the array of pixels, wherein the thin-film transistor structures include a first transistor and a second transistor (Fig. 6; switching transistor 101 (Tsw) and driving transistor 102 (Tdr)); an electrode that is electrically connected to a semiconducting layer of the second transistor (Fig. 6; electrode 90 electrically connected to semiconductor layer 27 of driving transistor 102 (Tdr)); and at least one dielectric layer that is interposed between the electrode and the semiconducting layer (Fig. 6; layer 72 and/or layer 62 interposed between the electrode 90 and the semiconductor layer 27 of driving transistor 102 (Tdr)); and a layer of metal that is interposed between the at least one dielectric layer and the semiconducting layer (Fig. 6; metal layer 70 interposed between the layer 72 and/or layer 62 and the semiconductor layer 27 of driving transistor 102 (Tdr)).
Park (e.g., Figs. 5-7) discloses the first transistor 101 is a silicon transistor ([0031]), wherein the silicon transistor comprises a polysilicon channel and a first gate ([0031]), but does not disclose the second transistor is an oxide transistor, wherein the oxide transistor comprises a semiconducting oxide layer and a second gate. However, Kim (e.g., Figs. 1-3, 6, 9, and 12) discloses a display device essentially same as that disclosed by Park, wherein the thin-film transistor structures include a first transistor and a second transistor (switching transistor TRs and driving transistor TRd); wherein the first transistor and the second transistor can be silicon transistors and/or oxide transistors (e.g., Figs. 3, 6, 9, and 12). As an example, Kim (Fig. 9) discloses the first transistor TRs is a silicon transistor ([0092] and [0096]), wherein the silicon transistor comprises a polysilicon channel and a first gate ([0092] and [0096]), and the second transistor TRd is an oxide transistor ([0093] and [0100]), wherein the oxide transistor comprises a semiconducting oxide layer and a second gate ([0093] and [0100]). As another reference, Kang (e.g., Figs. 1-3, 6, 9, and 12) discloses a display device essentially same as that disclosed by Park and Kim, comprising a first transistor (switching transistor M2) and a second transistor (driving transistor M1); wherein the second transistor M1 is an oxide transistor, wherein the oxide transistor comprises a semiconducting oxide layer and a second gate ([0039] and [0046]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Kim and Kang to the display device of Park. The combination/motivation would be to an alternative design choice by using different type transistors to improve the performance and characteristic of the pixel circuits of the display device.
Regarding claim 18, Park in view of Kim or Kang discloses the display of claim 17, Park (e.g., Figs. 5-7) discloses wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer (layer 72 and layer 62).
Regarding claim 19, Park in view of Kim or Kang discloses the display of claim 18, Park (e.g., Figs. 5-7) discloses wherein the layer of metal (metal layer 70) is interposed between the first dielectric layer (layer 72) and the second dielectric layer (layer 62).
Regarding claim 20, Park in view of Kim or Kang discloses the display of claim 19, Park (e.g., Figs. 5-7) discloses wherein the at least one dielectric layer further comprises a third dielectric layer (layer 42).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623