DETAILED ACTION
This Office action is in response to the application filed on 15 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
Receipt is acknowledged of drawings filed on 15 January 2025. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim. (US 11,789,479 B2; hereinafter “Kim”).
In re claim 1, Kim discloses a LDO regulator (Fig. 8) comprising: an error amplifier (330) that generates a control voltage by considering an error between a reference voltage (VREF) and an output voltage (VFB) generated from a pass transistor (PT), and then transmits the generated control voltage (VG) to the pass transistor (PT) and performs an operation in response to a bias voltage (VB1); a load adaptive bias generator (element 350 and Fig. 10) connected to an output terminal (NG) of the error amplifier that receives the control voltage (VG) transmitted from the error amplifier to the pass transistor (PT), generates a corresponding bias voltage (VB1), and transmits the generated bias voltage to the error amplifier; and a voltage droop predictor (element 400 and Figs. 11-14) whose output node (NO) is connected to a point where the output voltage (VO) generated from the pass transistor is transmitted to a load (395), and that, when at least one of a voltage droop signal in which the output voltage droops below a certain range (Col 9 Lines 13-16: The droop adjusting circuit 400 may reduce a voltage level of the gate voltage VG in response to decrease of the output voltage VO) or a wake-up signal (EN1) transmitted from outside is detected (Col 9 Lines 16-17: The droop adjusting circuit 400 may be selectively activated in response to an enable signal EN1), transmits an input voltage to the load connected to the output node (shown in Fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim. (US 11,789,479 B2; hereinafter “Kim”) in view of Mack (US 8120390 B1; hereinafter “Mack”).
In re claim 2, Kim discloses the LDO regulator (see rejection of claim 1).
Kim does not disclose an error amplifier comprising, a core OTA that performs an on/off operation in response to the bias voltage transmitted from the load adaptive bias generator.
Whereas, Mack discloses a similar LDO regulator (Fig. 1A), wherein an error amplifier (120) comprising, a core OTA (Col 3 Lines 13-14: an associated transconductance for the operational amplifier 120) that performs an on/off operation in response to the bias voltage transmitted from the load adaptive bias generator (Col 3 Lines: 7-10: bias generator 122 provides at least one bias voltage to the operational amplifier 120 to establish an operational bias point within the operational amplifier 120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the effective filing date of the claimed invention to have modified the apparatus of Kim such that “an error amplifier comprising, a core OTA that performs an on/off operation in response to the bias voltage transmitted from the load adaptive bias generator” as shown by Mack. The selection of “an error amplifier comprising, a core OTA that performs an on/off operation in response to the bias voltage transmitted from the load adaptive bias generator” would be a routine matter to the person of ordinary skill to increase control, as taught by Mack, cited above.
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, Kim (US 11,789,479 B2; hereinafter “Kim”) is considered the closest prior art on record. Kim discloses an LDO regulator.
Despite the similarity of the reference with Applicant’s claimed invention, Kim does not reasonably teach the recited feature of the LDO regulator comprising: “a class AB including a first transistor connected to the output terminal of the error amplifier and turned on when the control voltage is transmitted through the output terminal, and pulling up and transmitting the control voltage, and a second transistor connected to the output terminal of the error amplifier and turned on when the control voltage is transmitted through the output terminal, and pulling down and transmitting the control voltage; wherein class AB is connected to the load adaptive bias generator and transmits the pulled-up or pulled-down control voltage to the load adaptive bias generator,” in combination with the remaining limitations recited in claim 1 as a whole. Further, the additional prior art on record does not suggest an obvious modification to Kim that would produce the claimed invention in its entirety.
With respect to claim 4, Kim (US 11,789,479 B2; hereinafter “Kim”) is considered the closest prior art on record. Kim discloses an LDO regulator.
Despite the similarity of the reference with Applicant’s claimed invention, Kim does not reasonably teach the recited feature of the LDO regulator comprising: “a class AB including a first transistor connected to the output terminal of the error amplifier and turned on when the control voltage is transmitted through the output terminal, and pulling up and transmitting the control voltage, and a second transistor connected to the output terminal of the error amplifier and turned on when the control voltage is transmitted through the output terminal, and pulling down and transmitting the control voltage; wherein class AB is connected to the load adaptive bias generator and transmits the pulled-up or pulled-down control voltage to the load adaptive bias generator,” in combination with the remaining limitations recited in claim 1 as a whole. Further, the additional prior art on record does not suggest an obvious modification to Kim that would produce the claimed invention in its entirety.
With respect to claim 5, Kim (US 11,789,479 B2; hereinafter “Kim”) is considered the closest prior art on record. Kim discloses an LDO regulator. Kim discloses an LDO regulator (see of claim 1), wherein the voltage droop predictor (element 400 and Figs. 8 and 11-14) comprises, a fifth transistor (411) connected to an input voltage; and a droop detector whose output node is connected to a point (NO) where an output voltage (VO) generated from the pass transistor is transmitted to a load, and that, when at least one of a voltage droop signal in which the output voltage droops below a certain range and a wake- up signal transmitted from outside is detected.
Despite the similarity of the reference with Applicant’s claimed invention, Kim does not reasonably teach the recited feature of “turning on the fifth transistor so that the input voltage is transmitted to the load connected to the output node,” in combination with the remaining limitations recited in claim 1 as a whole. Further, the additional prior art on record does not suggest an obvious modification to Kim that would produce the claimed invention in its entirety.
Claim 6 depends directly on claim 5 and therefore contains allowable subject matter for the same reasons stated above.
Claims 7-11 allowed.
With respect to claim 7, Kim (US 11,789,479 B2; hereinafter “Kim”) is considered the closest prior art on record
Kim discloses a method for driving an LDO regulator (Fig. 8, 9) comprising: pulling up, when a load current changes from a large value to a small value, a control voltage (VG) outputted through an error amplifier (330) and transmitting it to a pass transistor (PT), and transmitting a bias voltage (VB1) lowered in response to the load current (Col 9 Lines 2-7: load sensor 360 may generate the first current by coping the supply current provided to the output node NO through the power transistor PT in response to the gate voltage VG, may generate the first bias voltage VB1 based on the first current and may provide the first bias voltage VB1 to the gate of the first PMOS transistor 351) to the error amplifier to reduce standby current consumption in the error amplifier; pulling down, when the load current changes from a small value to a large value, a control voltage outputted through an error amplifier and transmitting it to a pass transistor.
Despite the similarity of the reference with Applicant’s claimed invention, Kim does not reasonably teach the recited feature of “transmitting a bias voltage increased in response to the load current to the error amplifier to increase operating speed of the error amplifier; transmitting, when at least one of a voltage droop signal in which an output voltage generated from the pass transistor droops below a certain range or a wake-up signal transmitted from outside is detected, an input voltage to a load to prevent voltage droop,” in combination with the remaining limitations recited in claim 7 as a whole. Further, the additional prior art on record does not suggest an obvious modification to Kim that would produce the claimed invention in its entirety.
With respect to claim 8, Kim (US 11,789,479 B2; hereinafter “Kim”) is considered the closest prior art on record
Kim discloses a power management apparatus (Fig. 1, 8-11) in a device that switches from an idle state to an active state according to a predefined wake-up signal comprising: a front-end that, when a wake-up signal is detected (Col 8 Lines 44-48: the error amplifier 330 may include a resistive common-mode feedback circuit which is activated in response to an enable signal EN2 and increases an impedance of the error amplifier 330.); a back-end that switches to an active state according to a wake-up signal (EN1) transmitted and an LDO regulator that transmits an input voltage to the back-end to prevent voltage droop when the wake-up signal transmitted (EN1).
Despite the similarity of the reference with Applicant’s claimed invention, Kim does not reasonably teach the recited feature of “transmits the detected wake-up signal to a back-end and a wake-up signal transmitted from the front-end during an idle state,” in combination with the remaining limitations recited in claim 8 as a whole. Further, the additional prior art on record does not suggest an obvious modification to Kim that would produce the claimed invention in its entirety.
Claims 9-11 depend, either directly or indirectly, with claim 8 and are therefore allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Mack et al. US 11662755 B2 Low-noise High Efficiency Bias Generation Circuits And Method
Liu et al. US 20210333812 A1 PARALLEL LOW DROPOUT REGULATOR
Bisson et al. US 9134743 B2 Low-Dropout Voltage Regulator
Strik et al. US 8289009 B1 Low Dropout (LDO) Regulator With Ultra-low Quiescent Current
Chang et al. US 20230393598 A1 LOW-DROPOUT REGULATOR CIRCUIT
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICOLAS ALDEN CHAPA MILLS/ Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
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