DETAILED ACTION
This action is in response to the 08/06/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 08/06/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) in page 12 with respect to claim 1 and claim 9:
“First, according to Figure 3a and paragraph [0026] of Chang, the second waveform of figure 3a shows the switching frequency over time. Namely, the Y axis of figure 3a of Chang represents the overall switching frequency of the resonant converter during operation, but not a startup frequency. Chang does not indicate a specific comparative relationship between a controlled starting point (i.e., the startup frequency) and voltage (or current). Moreover, since Chang entirely fails to mention the technical feature of controlling the startup frequency, it naturally cannot disclose the technical feature of controlling the switching control signal to decrease from the startup frequency. Consequently, the control logic of Chang is fundamentally different from the control logic of Claims 1 and 9.”
In response, Chang’s paragraph 026 clearly discloses a starting up frequency, paragraph 026 recites “FIG. 3a illustrates a waveform showing a conventional method of starting up a resonant LLC converter... As shown, frequency fsw initially starts at a high frequency fmax when output voltage Vo is at zero and/or at a minimum voltage at time t0. Between time t0 and time t1 the frequency fsw of HSdrive and LSdrive decrease over time until fsw reaches operating frequency foper. By starting the switching frequency at a high frequency, the output voltage is able to ramp up to a high voltage while the LLC converter operates in the inductive mode.” Emphasis added. Therefore, the argument is not persuasive.
Further, Applicant(s) argue(s) in page 13 with respect to claim 1 and claim 9:
“Moreover, according to figure 3a of Chang, the first waveform of figure 3a merely discloses switching signals HSdrive and LSdrive. The switching signals HSdrive and LSdrive are complementary signals during the period from t0 to t1. The switching signals HSdrive and LSdrive merely exhibit a simple increasing in period over time. The switching signals HSdrive and LSdrive do not disclose the feature of "a phase shift synchronously decreasing over time or with frequency". Namely, the control logic of Chang is fundamentally different from the control logic of amended Claims 1 and 9 of the present invention.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a phase shift synchronously decreasing over time or with frequency) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claim does not require a reducing a phase shift between the plurality of control signals. Instead, the claims recite “control a time shift of the plurality of switching control signals to be reduced”. Chang does disclose shifting a timing (e.g. changing of timing) of the plurality of control signals Q1, Q2 corresponding to reducing the timing frequency on each rising edge of the control signals Q1-Q2. Therefore, the argument is not persuasive and the rejection is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2016/0181927; (hereinafter Chang), cited by Applicant(s).
Regarding claim 1, Chang [e.g. Fig. 2 – 3b] discloses a resonant converter [e.g. Fig. 2; 200] converting a power to a load [e.g. 112], and the resonant converter comprising: a transformer [e.g. Fig. 2; 208] comprising a primary winding [e.g. Fig. 2; 210] and two secondary windings [e.g. Fig. 2; 212]; a resonant circuit comprising two first switches [e.g. Fig. 2; Q1, Q2] connected in series, wherein two ends of the two first switches are connected with two ends of the primary winding, respectively [e.g. as shown]; a rectifier circuit comprising two second switches [e.g. Fig. 2; Q3, Q4] and an output terminal [e.g. lower node connecting low side terminal of capacitor Co and low terminal of Load 112], wherein the two second switches are connected in series with a connection node [e.g. connection of source terminals of Q3 and Q4], two ends of the two second switches are connected with two ends of the two secondary windings, respectively [e.g. drain terminals of each Q3, Q4 respectively coupled to the windings], and the output terminal is connected with the connection node [e.g. as shown]; a detection circuit [e.g. line detecting Vo input to controller 206 and part of 206 sensing it] connected with the output terminal and configured to detect at least one of a voltage and a current of the output terminal [e.g. paragraph 020 recites “controller 206 senses the output voltage Vo of the power converter”]; and a controller [e.g. 206, 202, 204] connected with the detection circuit, the two first switches [e.g. at gate terminals] and the two second switches [e.g. at gate terminals], wherein the controller is configured to provide a plurality of switching control signals to the two first switches [e.g. HS drive, LS drive] and the two second switches [e.g. SR1, SR2] according to at least one of the voltage and the current; wherein the controller is configured to set a startup frequency of the plurality of switching control signals to have inverse relationship with at least one of the voltage and the current of the output terminal [e.g. See the inverse relationship between output voltage and switching frequency in Fig. 3a. Note: Q3-Q4 are synchronous rectifiers (paragraph 020), synchronous rectifiers operates in synchronization with the switching frequency], the controller is configured to control the plurality of switching control signals to be reduced from the startup frequency [e.g. paragraph 026 recites “frequency fsw initially starts at a high frequency fmax when output voltage Vo is at zero and/or at a minimum voltage at time t0. Between time t0 and time t1 the frequency fsw of HSdrive and LSdrive decrease over time until fsw reaches operating frequency foper. By starting the switching frequency at a high frequency, the output voltage is able to ramp up to a high voltage while the LLC converter operates in the inductive mode”] and control a time shift of the plurality of switching control signals to be reduced [e.g. as shown in Fig. 3a], and the voltage of the output terminal reaches a preset voltage [e.g. see Vo stabilized at time t1].
Regarding claim 9, Chang [e.g. Fig. 2 – 3b] discloses a control method of a resonant converter, the resonant converter comprising a detection circuit [e.g. line detecting Vo input to controller 206 and part of 206 sensing it], a controller [e.g. 206, 202, 204], a transformer [e.g. Fig. 2; 208], a resonant circuit [e.g. Cr, Lr] and a rectifier circuit [e.g. Fig. 2; Q3, Q4], the transformer comprising a primary winding [e.g. Fig. 2; 210] and two secondary windings [e.g. Fig. 2; 212], the resonant circuit comprising two first switches [e.g. Fig. 2; Q1, Q2] connected in series, the rectifier circuit comprising two second switches [e.g. Fig. 2; Q3, Q4] connected in series and an output terminal [e.g. Vo], and the control method comprising: the detection circuit detecting at least one of a voltage and a current of the output terminal [e.g. paragraph 020 recites “controller 206 senses the output voltage Vo of the power converter”]; the controller providing a plurality of switching control signal to the two first switches [e.g. HS drive, LS drive] and the two second switches [e.g. SR1, SR2] according to at least one of the voltage and the current of the output terminal [e.g. paragraph 020 recites “controller 206 directly senses output voltage Vo and generate primary-side switching signals LSdrive and HSdrive via an isolated driver 202 and synchronous rectifier switching signals SR1 and SR2 via synchronous rectifier driver 204”]; the controller setting a startup frequency of the plurality of switching control signals to have inverse relationship with at least one of the voltage and the current of the output terminal [e.g. See the inverse relationship between output voltage and switching frequency in Fig. 3a. Note: Q3-Q4 are synchronous rectifiers (paragraph 020), synchronous rectifiers operates in synchronization with the switching frequency]; and the controller controlling the plurality of switching control signals to be reduced from the startup frequency [e.g. paragraph 026 recites “frequency fsw initially starts at a high frequency fmax when output voltage Vo is at zero and/or at a minimum voltage at time t0. Between time t0 and time t1 the frequency fsw of HSdrive and LSdrive decrease over time until fsw reaches operating frequency foper. By starting the switching frequency at a high frequency, the output voltage is able to ramp up to a high voltage while the LLC converter operates in the inductive mode”] and controlling a time shift of the plurality of switching control signals to be reduced [e.g. as shown in Fig. 3a], and the voltage of the output terminal reaching a preset voltage [e.g. see Vo stabilized at time t1].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of US Pub. No. 2015/0318778; (hereinafter Gong).
Regarding claim 3, Chang [e.g. Fig. 2 – 3b] discloses wherein the resonant circuit comprises the two first switches, and a first inductor [e.g. Lr], the two first switches are connected in series with a first node [e.g. left terminal of Cr], wherein the first node is connected with a first end of the primary winding [e.g. via Cr, Lr].
Chang fails to disclose two capacitors, the two capacitors are connected in series with a second node, second node is connected with a second end of the primary winding through the first inductor.
Gong [e.g. Fig. 2] teaches two capacitors [e.g. C1, C2], the two capacitors are connected in series with a second node [e.g. node between capacitors], the second node is connected with a second end of the primary winding [e.g. primary winding] through the first inductor [e.g. lower terminal of Lmt].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chang by two capacitors, the two capacitors are connected in series with a second node, second node is connected with a second end of the primary winding through the first inductor as taught by Gong in order of being able to help reduce the input current ripple, paragraph 047.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of EP 3,706,302; (hereinafter Ye), cited by Applicant(s).
Regarding claim 4, Chang [e.g. Fig. 2 – 3b] discloses wherein the two secondary windings comprises a first secondary winding [e.g. upper 212] and a second secondary winding [e.g. lower 212], the first secondary winding and the second secondary winding are connected with each other in series with a third node [e.g. at left terminal of Lo], the rectifier circuit comprises the two second switches, a second inductor [e.g. Lo] and a first output capacitor [e.g. Co], the two second switches are connected between one end of the first secondary winding and one end of the second secondary winding [e.g. as shown], the two second switches are connected with a fourth node [e.g. nodes directly connected to source terminals of Q3, Q4 and lower terminal of load 112], the second inductor and the first output capacitor are connected in series and connected between the third node and the fourth node [e.g. as shown], wherein the second inductor and the first output capacitor are connected with the output terminal [e.g. Vo].
Chang fails to disclose a capacitor, wherein the capacitor is connected between the third node and the fourth node.
Ye [e.g. Fig. 5] teaches a capacitor [e.g. Cr], wherein the capacitor is connected between the third node and the fourth node [e.g. between the center tap and the lower node having Vo- connecting both switches 44].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chang by a capacitor, wherein the capacitor is connected between the third node and the fourth node as taught by Ye in order of being able to reduce loss due to large RMS current.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Ye and further in view of US Pub. No. 2024/0280645; (hereinafter Khamesra).
Regarding claim 5, Chang fails to disclose wherein the rectifier circuit comprises a protection circuit, the protection circuit is connected between the first output capacitor and the load, the protection circuit comprises an output switch and a second output capacitor, the output switch and the second output capacitor are connected in series and connected between the output terminal and the fourth node.
Khamesra [e.g. Fig. 1] teaches wherein the rectifier circuit comprises a protection circuit [e.g. 148, 126], the protection circuit is connected between the first output capacitor [e.g. 124] and the load [e.g. 128], the protection circuit comprises an output switch [e.g. 148] and a second output capacitor [e.g. 126], the output switch and the second output capacitor are connected in series and connected between the output terminal [e.g. VBUSC] and the fourth node [e.g. upper terminal of 124].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Chang by wherein the rectifier circuit comprises a protection circuit, the protection circuit is connected between the first output capacitor and the load, the protection circuit comprises an output switch and a second output capacitor, the output switch and the second output capacitor are connected in series and connected between the output terminal and the fourth node as taught by Khamesra in order of being able to protect against over voltage and/or under voltage conditions, paragraph 023.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 2, 7 – 8 and 10 – 11 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein when the detection circuit detects the voltage of the output terminal is in a first voltage range, the controller sets the startup frequency of the plurality of switching control signals to a first frequency; when the detection circuit detects the voltage of the output terminal is in a second voltage range, the controller sets the startup frequency of the plurality of switching control signals to a second frequency, wherein a minimum value of the first voltage range is greater than or equal to a maximum value of the second voltage range, and the first frequency is less than the second frequency”.
The primary reason for the indication of the allowability of claim 7 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein when the detection circuit detects that the load state of the load is in a first state range, the controller sets the startup frequency of the plurality of switching control signals to a third frequency, when the detection circuit detects that the load state of the load is in a second state range, the controller sets the startup frequency of the plurality of switching control signals to a fourth frequency, wherein a minimum value of the first state range is greater than or equal to a maximum value of the second state range, and the third frequency is less than the fourth frequency”.
The primary reason for the indication of the allowability of claim 8 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein when the detection circuit detects that the current of the output terminal is ranged between a first current range, the controller sets the startup frequency of the plurality of switching control signals to a first frequency, when the detection circuit detects that the current of the output terminal is ranged between a second current range, the controller sets the startup frequency of the plurality of switching control signals to a second frequency, wherein a minimum value of the first current range is greater than or equal to a maximum value of the second current range, and the first frequency is less than the second frequency”.
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control method comprises: when the detection circuit detecting the voltage of the output terminal is in a first voltage range, the controller setting the startup frequency of the plurality of switching control signals to a first frequency; when the detection circuit detecting the voltage of the output terminal is in a second voltage range, the controller setting the startup frequency of the plurality of switching control signals to a second frequency, wherein a minimum value of the first voltage range is greater than or equal to a maximum value of the second voltage range, and the first frequency is less than the second frequency.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control method comprises: wherein when the detection circuit detecting that the current of the output terminal is ranged between a first current range, the controller setting the startup frequency of the plurality of switching control signals to a first frequency, when the detection circuit detecting that the current of the output terminal is ranged between a second current range, the controller setting the startup frequency of the plurality of switching control signals to a second frequency, wherein a minimum value of the first current range is greater than or equal to a maximum value of the second current range, and the first frequency is less than the second frequency.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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