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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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The information disclosure statements (IDS) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1, 2, 4, 5, 8 – 11, 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (9,129,923; hereinafter Han; cited in Applicant’s 30 October 2025 IDS) in view of Shim et al. (2015/0161943; hereinafter Shim).
Regarding claim 1, Han discloses a display device (Figure 1; col. 3, ll. 54 – 56) comprising:
a first driving transistor (Figure 2: Comprising DT in one of SP1, SP2) including a first active layer (Figures 4, 7: Comprising 144S, 144D1), a first drain electrode (col. 5, ll. 25 – 33: Comprising one of 148, 150), and a first gate electrode (Comprising 146);
a first pixel electrode (Comprising 122) connected directly to a portion of the first active layer or electrically connected to a portion of the first active layer (Comprising 144S, 144D) through an additional first source electrode (Comprising other one of 148, 150);
a second driving transistor (Comprising DT in other one of SP1, SP2) including a second active layer (Comprising 144S, 144D), a second drain electrode (Comprising one of 148, 150), and a second gate electrode (Comprising 146);
a second pixel electrode (Comprising 122) connected directly to a portion of the second active layer () or electrically connected to a portion of the second active layer (Comprising 144S, 144D) through an additional second source electrode (Comprising other one of 148, 150);
a first lower metal (Figures 4, 7: Comprising one of shown two instances of 166) connected to the first pixel electrode or connected to the first source electrode (col. 7, ll. 47 – 50: Terminal of storage capacitor connected to driving transistor source, pixel electrode);
a second lower metal (Comprising other one of shown two instances of 166) connected to the second pixel electrode or connected to the second source electrode (col. 7, ll. 47 – 50: Terminal of storage capacitor connected to driving transistor source, pixel electrode);
an overlapping pattern (Figure 2: Comprising at least one of RP1, RP2), and including
a first part (Figure 3: Comprising one of shown two instances of 176) overlapping with at least a portion of the first lower metal (Figure 4: Comprising one of shown two instances of 166),
a second part (Figure 3: Comprising other one of two shown instances of 176) overlapping with at least a portion of the second lower metal (Figure 4: Comprising other one of shown two instances of 166), and
a third part (Figure 3: Comprising 174) between the first part and the second part (Comprising two shown instances of 176).
Han does not explicitly disclose the device wherein the first lower metal is directly connected to the first pixel electrode or directly connected to the first source electrode, and overlapping with the first active layer; the second lower metal is directly connected to the second pixel electrode or directly connected to the second source electrode, and overlapping with the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; the overlapping pattern disposed on the first buffer layer, and including a second buffer layer disposed on the overlapping pattern and disposed below the first active layer and the second active layer.
In the same field of endeavor, Shim discloses a display device [0003] wherein the first lower metal (Figure 17: Comprising one of IEP1, IEP2) is directly connected to the first pixel electrode or directly connected to the first source electrode (Figure 18: Comprising one of 1821, 1822), and overlapping with the first active layer (Figure 23: Comprising 1940; [0278]: Source node of DT; Figure 13: Corresponding to one of DT1, DT2); the second lower metal (Figure 17: Comprising other one of IEP1, IEP2) is directly connected to the second pixel electrode or directly connected to the second source electrode (Figure 18: Comprising other one of 1821, 1822), and overlapping with the second active layer (Figure 23: 1940; [0278]: Source node of DT; Figure 13: Corresponding to other one of DT1, DT2); a first buffer layer (Figure 23: Comprising one of 2010, 2030) disposed on the first lower metal and the second lower metal (Comprising IEP1, IEP2; [0238]: Extending from corresponding ones of 1710, 1720); the overlapping pattern (Comprising 1711) disposed on the first buffer layer (Comprising one of 2010, 2030), and including a second buffer layer (Comprising other one of 2010, 2030) disposed on the overlapping pattern (Comprising 1711) and disposed below the first active layer and the second active layer (Comprising 1940). This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the first lower metal is directly connected to the first pixel electrode or directly connected to the first source electrode, and overlapping with the first active layer; the second lower metal is directly connected to the second pixel electrode or directly connected to the second source electrode, and overlapping with the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; the overlapping pattern disposed on the first buffer layer, and including a second buffer layer disposed on the overlapping pattern and disposed below the first active layer and the second active layer, in view of the teaching of Shim, to compensate for a brightness reduction.
Regarding claim 2, Han in view of Shim discloses the display device of claim 1.
Han does not explicitly disclose the device wherein a distance between the first source electrode and the second source electrode is smaller than a distance between a first emission area formed by the first pixel electrode and a second emission area formed by the second pixel electrode.
In the same field of endeavor, Shim discloses a display device [0003] wherein a distance between the first source electrode and the second source electrode is smaller than a distance between a first emission area formed by the first pixel electrode and a second emission area formed by the second pixel electrode (Driving transistor sources {1821, 1822 of Figure 18; [0253], [0257]} are separated by an emission area {1720; [0238]} in one configuration {Figure 8(B)}; in an alternative {Figure 8(C)} wherein circuit areas {CA1, CA2} and their respective driving transistors separate the two emission areas {EA1, EA2; 1710, 1720 in Figure 18}, the driving transistor sources are closer than the corresponding emission areas). This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein a distance between the first source electrode and the second source electrode is smaller than a distance between a first emission area formed by the first pixel electrode and a second emission area formed by the second pixel electrode, in view of the teaching of Shim, to compensate for a brightness reduction.
Regarding claim 4, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising: a passivation layer (Figures 4, 7: Comprising 118) disposed on the first source electrode (Comprising one of 148, 150), the first gate electrode (Comprising 146), the second source electrode (Comprising one of 148, 150), and the second gate electrode (Comprising 146); and an overcoat layer disposed on the passivation layer (Comprising 128), wherein the first pixel electrode (Comprising 122) is disposed on the overcoat layer (Comprising 128), and is connected to the first source electrode (Comprising one of 148, 150) through a hole (Comprising 164) in the overcoat layer (Comprising 128) and the passivation layer (Comprising 118), and wherein the second pixel electrode (Comprising 122) is disposed on the overcoat layer (Comprising 128), and is connected to the second source electrode (Comprising one of 148, 150) through a hole (Comprising 164) in the overcoat layer (Comprising 128) and the passivation layer (Comprising 118).
Regarding claim 5, Han in view of Shim discloses the display device of claim 1. Han discloses the device wherein the first gate electrode (Figures 4, 7: Comprising 146) is disposed on the first active layer (Comprising 144S, 144D), and the second gate electrode (Comprising 146) is disposed on the second active layer (Comprising 144S, 144D).
Han does not explicitly disclose the device wherein the first source electrode and the second source electrode include a same electrode material included in the first gate electrode and the second gate electrode.
In the same field of endeavor, Shim discloses a display device [0003] wherein the first source electrode and the second source electrode include a same electrode material included in the first gate electrode and the second gate electrode [0199]. This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the first source electrode and the second source electrode include a same electrode material included in the first gate electrode and the second gate electrode, in view of the teaching of Shim, to compensate for a brightness reduction.
Regarding claim 8, Han in view of Shim discloses the display device of claim 1. Han discloses the device wherein, when a first current is supplied from the first driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in one of SP1, SP2) to the first pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting cell anode) and a second current is supplied from the second driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in differing one of SP1, SP2) to the second pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting cell anode), the first part (Figure 3: Comprising one of shown two instances of 176) and the first lower metal are spaced apart (Figure 4: One of shown instances of 176 – of which one of two ends of RP2 is comprised – separated from corresponding instance of 166) or the second part (Figure 3: Comprising other one of shown two instances of 176) and the second lower metal are spaced apart (Figure 4: Differing one of shown instances of 176 – of which differing one of two ends of RP2 is comprised – separated from corresponding other instance of 166), and at least one of the first lower metal and the second lower metal (Comprising respective instances of 166) is electrically separated from the overlapping pattern (Comprising at least one of RP1, RP2).
Regarding claim 9, Han in view of Shim discloses the display device of claim 8. Han discloses the device further comprising a connection pattern (Figure 6: Corresponding to at least one of W2, W3) connecting the first part (Comprising one of two ends of RP2 – one of two instances of 176; Figure 7) and the first lower metal (Comprising one of two instances of 166) or connecting the second part (Comprising other one of two ends of RP2 – other one of two instances of 176; Figure 7) and the second lower metal (Comprising other one of two instances of 166).
Han does not explicitly disclose the device wherein the connection pattern includes a same material as the first source electrode and the second source electrode.
In the same field of endeavor, Shim discloses a display device [0003] wherein the connection pattern includes a same material as the first source electrode and the second source electrode (Welding particle is a portion of floating pattern [0294] comprising the same material as source and drain electrodes [0197]). This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the connection pattern includes a same material as the first source electrode and the second source electrode, in view of the teaching of Shim, to compensate for a brightness reduction.
Regarding claim 10, Han in view of Shim discloses the display device of claim 1. Han discloses the device wherein, when a first current is supplied from the first driving transistor (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first pixel electrode (Corresponding to N2 of SP2) and the second pixel electrode (Corresponding to N2 of SP1), the first part (Figure 6: Comprising one of two instances of 176 of RP2; Figure 7) and the first lower metal (Comprising one of two instances of 166) are connected (Figure 6: By one of W2, W3), and the second part (Comprising other one of two instances of 176 of RP2; Figure 7) and the second lower metal (Comprising other one of two instances of 166) are connected (Figure 6: By other one of W2, W3).
Regarding claim 11, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising a driving voltage line configured to transmit a driving voltage (Figure 2: Carrying VDD) to the first drain electrode and the second drain electrode (One end of current path across DT, in each of SP1, SP2), wherein, when a first current is supplied (col. 4, ll. 53 – 57) from the first driving transistor to the first pixel electrode (From DT to OLED in corresponding one of SP1, SP2) and a second current is supplied (col. 4, ll. 53 – 57) from the second driving transistor to the second pixel electrode (From DT to OLED in corresponding other one of SP1, SP2), at least one of ends of the overlapping pattern (Comprising at least one of RP1, RP2) is connected to the driving voltage line (Carrying VDD).
Regarding claim 13, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising a driving voltage line configured to transmit a driving voltage (Figure 2: Carrying VDD) to the first drain electrode and the second drain electrode (One end of current path across DT, in each of SP1, SP2), wherein, when a first current is supplied from the first driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in one of SP1, SP2) to the first pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting cell anode) and a second current is supplied from the second driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in differing one of SP1, SP2) to the second pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting cell anode), the driving voltage line (Carrying VDD) and the first drain electrode are electrically connected (One end of current path across DT, in one of SP1, SP2), and the driving voltage line (Carrying VDD) and the second drain electrode are electrically connected (One end of current path across DT, in differing one of SP1, SP2), and wherein, when a first current is supplied from the first driving transistor (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first pixel electrode (Of OLED in SP2) and the second pixel electrode (Of OLED in SP1), the driving voltage line (Carrying VDD) and the first drain electrode are electrically connected (One end of current path across DT, in SP2; col. 11, ll. 46 – 51: DT of *normal* sub-pixel).
Han does not explicitly disclose the device wherein the driving voltage line and the second drain electrode are electrically disconnected.
In the same field of endeavor, Shim discloses a display device [0003] wherein the driving voltage line (Figure 25: Carrying EVDD) and the second drain electrode (Of DT2) are electrically disconnected [0310]. This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the driving voltage line and the second drain electrode are electrically disconnected, in view of the teaching of Shim, to compensate for a brightness reduction.
Regarding claim 14, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising: a data line (Figure 2: Comprising DLj) configured to transmit a data voltage (col. 4, ll. 42 – 45); a first scan transistor (Comprising ST in one of SP1, SP2) configured to control a connection between the data line (Comprising DLj) and the first gate electrode (Of DT, in one of SP1, SP2); and a second scan transistor (Comprising ST in differing one of SP1, SP2) configured to control a connection between the data line (Comprising DLj) and the second gate electrode (Of DT, in differing one of SP1, SP2), wherein, when a first current is supplied from the first driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in one of SP1, SP2) to the first pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting anode) and a second current (col. 4, ll. 50 – 57: Drive transistor supplying current in other one of SP1, SP2) is supplied from the second driving transistor to the second pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting anode), the data line (Comprising DLj) and the first scan transistor (Comprising ST in one of SP1, SP2) are connected (col. 4, ll. 59 – 61), and the data line (Comprising DLj) and the second scan transistor (Comprising ST in other one of SP1, SP2) are connected (col. 4, ll. 59 – 61), and wherein, when a first current is supplied from the first driving transistor (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first pixel electrode (Of OLED in SP2) and the second pixel electrode (Of OLED in SP1), the data line (Comprising DLj) and the first scan transistor (Comprising ST in one of SP1, SP2) are connected (col. 4, ll. 59 – 61), and the data line (Figures 9, 10: Comprising DLj) and the second scan transistor (Comprising ST of SP1) are disconnected (See “…Cutting…”).
ii. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Shim, as applied to claim 1 above, and further in view of Lee et al. (2021/0134891; hereinafter Bang).
Regarding claim 3, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising a gate insulating layer (Figures 4, 7: Comprising 112; col. 5, ll. 7 – 9) disposed on the first active layer (Comprising 144S, 144D) and the second active layer (Comprising 144S, 144D), wherein the first source electrode (Comprising other one of 148, 150) is disposed on the gate insulating layer (Comprising 112), and wherein the second source electrode (Comprising other one of 148, 150) is disposed on the gate insulating layer (Comprising 112).
Han in view of Shim does not explicitly disclose the device wherein the first source electrode is connected to the first lower metal through a hole in the gate insulating layer, the second buffer layer and the first buffer layer, and wherein the second source electrode is connected to the second lower metal through a hole in the gate insulating layer, the second buffer layer and the first buffer layer.
In the same field of endeavor, Bang discloses a display [0002] wherein the source electrode (Figure 10: Comprising one of 250, 260) is connected to the lower metal (Comprising 700; [0101]) through a hole in the gate insulating layer (Comprising 220), the second buffer layer (Comprising 112) and the first buffer layer (Comprising 111). Applied to Han’s pixel circuit (Figure 2), driving transistors (Comprising DT) in each of first (Comprising SP1) and second (Comprising SP2) sub-pixels are configured with the aforementioned connectivity disclosed by Bang. This is among measures implemented to prevent color mixing [0007].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the first source electrode is connected to the first lower metal through a hole in the gate insulating layer, the second buffer layer and the first buffer layer, and wherein the second source electrode is connected to the second lower metal through a hole in the gate insulating layer, the second buffer layer and the first buffer layer, in view of the teaching of Bang, to prevent color mixing.
iii. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Shim, as applied to claim 1 above, and further in view of Park et al. (2022/0123092; hereinafter Park; cited in Applicant’s 30 October 2025 IDS).
Regarding claim 12, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising a driving voltage line configured to transmit a driving voltage (Figure 2: Carrying VDD) to the first drain electrode and the second drain electrode (One end of current path across DT, in each of SP1, SP2), wherein, when a first current is supplied from the first driving transistor (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first pixel electrode (Of OLED in SP2) and the second pixel electrode (Of OLED in SP1).
Han in view of Shim does not explicitly disclose the panel wherein ends of the overlapping pattern are electrically disconnected from the driving voltage line.
In the same field of endeavor, Park discloses a display [0002] wherein ends (Figure 6: Comprising RPa, RPb) of the overlapping pattern (Comprising RP) are electrically disconnected [0138] from the driving voltage line (Comprising at least one of DVL_CPa, DVL_CPb). This is among measures implemented to prevent unfavorable device thickening [0084].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein ends of the overlapping pattern are electrically disconnected from the driving voltage line, in view of the teaching of Park, to prevent thickening the device.
iv. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Shim, as applied to claim 1 above, and further in view of Lee et al. (2021/0098551; hereinafter Lee).
Regarding claim 15, Han in view of Shim discloses the display device of claim 1. Han discloses the device further comprising: a reference voltage line (Figure 2: Carrying Vref) configured to transmit a reference voltage (col. 6, ll. 10 – 13); a first sensing transistor (Comprising SET in one of SP1, SP2) configured to control a connection between the reference voltage line (Carrying Vref) and the first source electrode (Comprising one end of current path across DT in one of SP1, SP2); and a second sensing transistor (Comprising SET in other one of SP1, SP2) configured to control a connection between the reference voltage line (Carrying Vref) and the second source electrode (Comprising one end of current path across DT in other one of SP1, SP2), wherein, when a first current is supplied from the first driving transistor (col. 4, ll. 50 – 57: Drive transistor supplying current in one of SP1, SP2) to the first pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting anode) and a second current (col. 4, ll. 50 – 57: Drive transistor supplying current in other one of SP1, SP2) is supplied from the second driving transistor to the second pixel electrode (col. 5, ll. 25 – 33: Drive transistor connection to light emitting anode), the reference voltage line (Carrying Vref) and the first sensing transistor (Comprising SET in one of SP1, SP2) are connected (col. 6, ll. 10 – 13), and the reference voltage line (Carrying Vref) and the second sensing transistor (Comprising SET in differing one of SP1, SP2) are connected (col. 6, ll. 10 – 13), and wherein, when a first current is supplied from the first driving transistor (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first pixel electrode (Of OLED in SP2) and the second pixel electrode (Of OLED in SP1), the reference voltage line (Carrying Vref) and the first sensing transistor (Comprising SET in one of SP1, SP2) are connected (col. 6, ll. 10 – 13).
Han in view of Shim do not explicitly disclose the device wherein the reference voltage line and the second sensing transistor are disconnected.
In the same field of endeavor, Lee discloses a display [0002] wherein the reference voltage line (Figure 8: Comprising VREF) and the second sensing transistor (Comprising ST, of PXL1-1) are disconnected [0099]. This is among measures implemented to preserve sufficient aperture ratio and transmittance with a repair structure [0013].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the reference voltage line and the second sensing transistor are disconnected, in view of the teaching of Lee, to implement a repair structure with favorable transmittance.
v. Claims 16, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Choi et al. (2021/0098749; hereinafter Choi).
Regarding claim 16, Han discloses a display panel (col. 4, ll. 25 – 27) comprising:
a first subpixel including a first subpixel circuit (Figure 2: Comprising one of SP1, SP2) and a first light emitting device (Comprising OLED in one of SP1, SP2);
a second subpixel including a second subpixel circuit (Comprising other one of SP1, SP2) and a second light emitting device (Comprising OLED in other one of SP1, SP2);
a first lower metal (Figures 4, 7: Comprising one of shown two instances of 166) connected to the first subpixel circuit (Comprising one of SP1, SP2);
a second lower metal (Comprising other one of shown two instances of 166) connected to the second subpixel circuit (Comprising other one of SP1, SP2);
an overlapping pattern (Figure 2: Comprising at least one of RP1, RP2) including
a first part (Figure 3: Comprising one of shown two instances of 176) overlapping with a part of the first lower metal (Figures 4, 7: Comprising one of shown two instances of 166),
a second part (Figure 3: Comprising other one of shown two instances of 176) overlapping with a part of the second lower metal (Figures 4, 7: Comprising other one of shown two instances of 166), and
a third part (Figure 3: Comprising 174) between the first part and the second part (Comprising two shown instances of 176).
Han does not explicitly disclose the panel further comprising a first buffer layer disposed between the first lower metal, the second lower metal, and the overlapping pattern.
In the same field of endeavor, Choi discloses a display [0002] comprising a first buffer layer (Figure 5: Comprising 112) disposed between the first lower metal (Comprising one of BML1, BML3), the second lower metal (Comprising differing one of BML1, BML3), and the overlapping pattern (Comprising at least one of {a} DL, RL and respectively associated {b} CM1, CM2; Figure 9; [0180], [0184]). This is among measures implemented to simplify the manufacturing process [0110].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified as further comprising a first buffer layer disposed between the first lower metal, the second lower metal, and the overlapping pattern, in view of the teaching of Choi, to simplify the manufacturing process.
Regarding claim 19, Han in view of Choi discloses the display panel of claim 16. Han discloses the device wherein, when a first current is supplied from the first subpixel circuit (col. 4, ll. 50 – 57: Drive transistor supplying current to OLED) to the first light emitting device (Figure 2: Comprising OLED in one of SP1, SP2) and a second current is supplied from the second subpixel circuit (col. 4, ll. 50 – 57: Drive transistor supplying current to OLED) to the second light emitting device (Comprising OLED in other one of SP1, SP2), the first part (Figure 3: Comprising one of shown two instances of 176) and the first lower metal are spaced apart (Figure 4: One of shown instances of 176 – of which one of two ends of RP2 is comprised – separated from corresponding instance of 166), or the second part (Figure 3: Comprising other one of shown two instances of 176) and the second lower metal are spaced apart (Figure 4: Differing one of shown instances of 176 – of which differing one of two ends of RP2 is comprised – separated from corresponding other instance of 166), and wherein, when a first current is supplied from the first subpixel circuit (Figures 2, 5: DT of SP2) to the first light emitting device (OLED of SP1) and the second light emitting device (OLED of SP2), the first part (Figures 6, 7: Comprising one of shown two instances of 176) and the first lower metal (Comprising corresponding instance of 166) are connected (At one of W2, W3), and the second part (Comprising other one of shown two instances of 176) and the second lower metal (Comprising corresponding other instance of 166) are connected (At other one of W2, W3).
vi. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Choi, as applied to claim 16 above, and further in view of Shim.
Regarding claim 18, Han in view of Choi discloses the display panel of claim 16.
Han in view of Choi does not explicitly disclose the device wherein a distance between the first subpixel circuit and the second subpixel circuit is smaller than a distance between a first emission area of the first light emitting device and a second emission area of the second light emitting device.
In the same field of endeavor, Shim discloses a display device [0003] wherein a distance between the first subpixel circuit and the second subpixel circuit is smaller than a distance between a first emission area of the first light emitting device and a second emission area of the second light emitting device (Figure 8{C}: Immediately adjacent driving circuits DRC1, DRC2 are formed between and thus more closely spaced than emission areas EA1, EA2). This is among measures implemented to compensate for a brightness reduction following the repair of a defect [0015].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein a distance between the first subpixel circuit and the second subpixel circuit is smaller than a distance between a first emission area of the first light emitting device and a second emission area of the second light emitting device, in view of the teaching of Shim, to compensate for a brightness reduction.
vii. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Han in view of Choi, as applied to claim 16 above, and further in view of Park.
Regarding claim 20, Han in view of Choi discloses the display panel of claim 16. Han discloses the device further comprising a common power line (Figure 2: Carrying VDD), wherein, when a first current is supplied (col. 4, ll. 53 – 57) from the first subpixel circuit to the first light emitting device (From DT to OLED in corresponding one of SP1, SP2) and a second current is supplied (col. 4, ll. 53 – 57) from the second subpixel circuit to the second light emitting device (From DT to OLED in corresponding other one of SP1, SP2), wherein, a first current is supplied from the first subpixel circuit (Figure 12: Comprising DT; corresponding to DT of SP2 in Figure 2) to the first light emitting device (Comprising OLED in SP2) and the second light emitting device (Comprising OLED in SP1).
Han in view of Choi does not explicitly disclose the panel wherein the common power line is adjacent to the overlapping pattern, the overlapping pattern is electrically connected to the common power line, the overlapping pattern is electrically disconnected from the common power line.
In the same field of endeavor, Park discloses a display [0002] wherein the common power line (Figure 6: Comprising at least one of DVL_CPa, DVL_CPb) is adjacent to the overlapping pattern (Comprising RP), the overlapping pattern is electrically connected to the common power line [0139], the overlapping pattern is electrically disconnected from the common power line [0138]. This is among measures implemented to prevent unfavorable device thickening [0084].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the device of Han to be modified wherein the common power line is adjacent to the overlapping pattern, the overlapping pattern is electrically connected to the common power line, the overlapping pattern is electrically disconnected from the common power line, in view of the teaching of Park, to prevent thickening the device.
Allowable Subject Matter
Claims 6, 7, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, Han in view of Shim discloses the display device of claim 1.
The cited prior art fail to singularly or collectively disclose the device further comprising: a first upper capacitor including a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode including a same material as the first active layer; a first lower capacitor including a third capacitor electrode including a same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal; a second upper capacitor including a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode including a same material as the second active layer; and a second lower capacitor including a seventh capacitor electrode including the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal, wherein the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor, and wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.
Thus, claim 6 is objected to.
Regarding claim 7, Han in view of Shim discloses the display device of claim 1.
The cited prior art fail to singularly or collectively disclose the device further comprising: a first upper capacitor including a first capacitor electrode including a same material as the first active layer, and a second capacitor electrode including the same material as the overlapping pattern; a first lower capacitor including the second capacitor electrode and a third capacitor electrode corresponding to the first lower metal; a second upper capacitor including a fourth capacitor electrode including a same material as the second active layer, and a fifth capacitor electrode including the same material as the overlapping pattern; and a second lower capacitor including the fifth capacitor electrode and a sixth capacitor electrode corresponding to the first lower metal, wherein the first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor, and wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.
Thus, claim 7 is objected to.
Regarding claim 17, Han in view of Choi discloses the display panel of claim 16.
The cited prior art fail to singularly or collectively disclose the device further comprising: a substrate (Figures 4, 7: Comprising 101); a first active layer (Comprising 144S, 144D) disposed within the first subpixel circuit (Figure 2: Within DT in one of SP1, SP2); and a second active layer (Figure 4, 7: Comprising 144S, 144D) disposed within the second subpixel circuit (Figure 2: Within DT in one of SP1, SP2), wherein the first lower metal is disposed below the first active layer and overlaps with the first active layer, wherein the second lower metal is disposed below the second active layer and overlaps with the second active layer, and wherein the overlapping pattern is disposed in a metal layer between the first lower metal and the second lower metal and the substrate.
Thus, claim 17 is objected to.
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/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Second active layer of DT (col. 5, ll. 25 – 33) view taken along annotated line I–I’ in Figures 3, 4 corresponding to DT of defective SP1 (col. 7, ll. 53 – 62), DT of normal SP2 (with no similar annotation) is below (Figure 3); note typographical error of “…144S…” shown as “…1445…”