Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claims 1-20 have been submitted for examination.
Claims 1-20 have been rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Kanno United States Patent 11,392,323 hereinafter 323.
In regard to claims 1 8 15
323 discloses
An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: receive a plurality of commands (ERASE PROGRAM READ) at a controller of a memory system ;determine, based at least in part on receiving the plurality of commands, a plurality of weighted counts associated with each command of the plurality of commands; and execute a first command of the plurality of commands based at least in part on a respective weighted count of the first command. (Figure 4)
323 discloses “ The controller selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority. The controller starts execution of a command stored in the selected queue.”
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In regard to claims 2 9 16
2. The apparatus of claim 1, wherein: each weighted count of the plurality of weighted counts is associated with a respective priority of a plurality of priorities; and the respective weighted count of the first command corresponds to a highest priority of the plurality of priorities. 323 discloses “ executing a scheduling operation of selecting a queue of the highest priority from a plurality of queues, using two types of parameters (first weight and second weight) corresponding to each of a plurality of queues.”
In regard to claims 3 10 17
3. The apparatus of claim 2, wherein the processing circuitry is further configured to cause the apparatus to: select, based on determining the plurality of weighted counts, a respective weighted count of the first command that corresponds to the highest priority.
323 discloses “ executing a scheduling operation of selecting a queue of the highest priority from a plurality of queues, using two types of parameters (first weight and second weight) corresponding to each of a plurality of queues.”
In regard to claims 4 11 18
4. The apparatus of claim 2, wherein the processing circuitry is further configured to cause the apparatus to: execute a second command of the plurality of commands based at least in part on a respective weighted count of the second command being the same as the respective weighted count of the first command; and execute a third command of the plurality of commands after executing the second command based at least in part on a respective weighted count of the third command being associated with a second priority of the plurality of priorities that is less than the highest priority.
323 discloses “In a case where all the first weights of eight queues are set to the same value, the scheduler 21 can cause eight queues to function as Round Robin Queuing. In this case, first, the queue # 0 having the smallest queue ID is selected as the queue of the highest priority, and one command stored in the queue # 0 is executed. W0 is reduced. The queue # 1 having the smallest queue ID, of the remaining queues # 1 to #7, is selected as the queue of the highest priority. When one command stored in the queue # 1 is executed, W1 is also reduced. Then, the queue # 2 having the smallest queue ID, of the remaining queues # 2 to #7, is selected as the queue of the highest priority.”
In regard to claims 5 12 19
5. The apparatus of claim 1, wherein executing the first command of the plurality of commands is based at least in part on an order associated with the plurality of weighted counts.
323 discloses “In a case where first weights different from each other are set in eight queues, the scheduler 21 can distribute the time to access the NAND flash memory 5 to eight command groups stored in the respective eight queues, based on the first weights, and can operate the eight queues”
In regard to claims 6 13 20
6. The apparatus of claim 1, wherein the processing circuitry is further configured to cause the apparatus to: increment a value of a counter associated with the respective weighted count of the first command in response to receiving each command within the plurality of commands that is associated with the respective weighted count of the first command, wherein determining the plurality of weighted counts associated with each command of the plurality of commands is based at least in part on incrementing the value of the counter. 323 discloses “the queue # 0 having the smallest queue ID is selected as the queue of the highest priority, and one command stored in the queue # 0 is executed. W0 is reduced. The queue # 1 having the smallest queue ID, of the remaining queues # 1 to #7, is selected as the queue of the highest priority. When one command stored in the queue # 1 is executed, W1 is also reduced. Then, the queue # 2 having the smallest queue ID, of the remaining queues # 2 to #7, is selected as the queue of the highest priority”
In regard to claims 7 14
7. The apparatus of claim 2, wherein each priority of the plurality of priorities is associated with a read length.
323 discloses “ The CPU 12 specifies for the DMAC 15 a transfer source address indicative of a location in the memory of the host 2, the size of the data to be transferred, and a transfer destination address indicative of a location in the internal buffer 161.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure See PTO 892.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMINE RIAD whose telephone number is (571)272-8185.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bonzo Bryce can be reached 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amine Riad/
Primary Examiner