DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Response to Amendment
This final Office action is in response to the amendment filed 10 July 2026. Claims 1-20 are pending. All objections and rejections not repeated below are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Per claim 1, on line 11, when applied the broadest reasonable interpretation (BRI), the plain meaning of the limitation “by preventing write access to the first cache” implies preventing write access to an entire cache and it is not supported by any written description. The specification notably lays out the difference between a cache and cache lines in paragraph [0011], which discloses that a cache refers to multiple cache units, while a cache unit refers to a plurality of cache lines. Consequently, “cache” and “cache line” should not be used interchangeably for claim interpretation. The specification then teaches in paragraphs [0045], [0048], [0050]-[0052] and [0054]-[0056] that coherency is maintained on the basis of cache lines, by checking address registers associated with respective cache lines. The specification further teaches in paragraph [0055] that locking is done on the basis of cache lines by checking the memory address stored in a cache line address register corresponding to a particular cache line. The specification does not appear to disclose any embodiment where the locking is done on the basis of an entire cache or even on the basis of cache units. Locking of a cache is not consistent in scope and meaning as the locking of a cache line. The latter prevents access to a cache line while allowing the rest of the cache to be accessible, while the former prohibits access to the entire cache. As a result, the claim limitation’s BRI is substantially different if not significantly broader in scope and meaning than what is disclosed by the written description.
Per claim 9, on lines 6 and 9, the limitations “preventing write access to the first cache” and “while write access is prevented to the first cache” are not supported by any written description for the same reasons set forth above for claim 1.
Per claim 16, on lines 9 and 12, the limitations “prevent write access to the first cache” and “while write access is prevented to the first cache” are not supported by any written description for the same reasons set forth above for claim 1.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 9-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 6, on lines 2 and 3, “the data” is indefinite as data is stored in the first cache and the second cache. It is unclear whether the transfer request is for the data in the first cache or the second cache, or both. It is further unclear whether coherent access is provided to the data in the first cache or the second cache, or both.
Per claim 9, line 12, “the data” is indefinite as data is stored in the first cache and the second cache. It is unclear whether the access operation is for the data in the first cache or the second cache.
Per claim 12, lines 2 and 4, “the data” on each line is indefinite for similar reasons set forth above for claim 6.
Per claim 16, on line 16, “the data” is indefinite for the same reason set forth above for claim 9.
Per claim 19, lines 3 and 4, “the data” on each line is indefinite for similar reasons set forth above for claim 6.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 3 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Per claim 3, the limitation “prevent the first cache from being written to or read from prior to copying the data from the first cache to the second cache” does not include a further limitation to claim 1’s limitation “preventing write access to the first cache prior to copying the data from the first cache to the second cache”. Note that “or read from” is an optional limitation and may be exclusive from claim interpretation.
Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7, 9, 11-14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Pohlack et al. [Pub.No.: US 20160070659 A1] (hereinafter “Pohlack”), and further in view of Shibahara et al. [Pub.No.: US 20160349322 A1] (hereinafter “Shibahara”) and Beard [Pub.No.: US 2018/0150243 A1] (hereinafter “Beard”).
Independent Claims:
Per claim 1, Pohlack teaches:
A system (see Fig. 1, computing device 100), comprising:
one or more memory arrays (see Fig. 1 and paragraph [0022], one or more of various types of memory devices in memory 106);
a first controller (see Fig. 1, cache controller 128) coupled to a first processing resource (see Fig. 1, cores 108/110) and to a first cache (see Fig. 1, one or more of L1/L2 caches 108/110/124) that is configured to store data corresponding to a memory address of the one or more memory arrays (see paragraph [0024], lines 1-16, cache blocks are loaded from memory 106 into one of the caches); and
a second controller (see Fig. 1, cache controller 130) coupled to a second processing resource (see Fig. 1, cores 112/114) and to a second cache (see Fig. 1, one of more of L1/L2 caches 120/122/126) that is configured to store the data corresponding to the memory address (see paragraph [0024], lines 1-16, cache blocks are loaded from memory 106 into one of the caches),
wherein the system is configured to provide coherent access to the data corresponding to the memory address, and stored in the first cache and stored in the second cache (see paragraph [0024], lines 1-16, processor cores 108-114 may operate on the same data loaded from the same locations in memory 106, and cache coherence among copies of data in different caches is maintained using protocols such as MESI).
Pohlack does not teach coherent access is provided by preventing write access to the first cache prior to copying the data from the first cache to the second cache. Shibahara teaches an analogous system comprising multiple L1 caches wherein when requested data is not stored in a L1 cache, the cache controller copies the data from the first cache to the second cache (see Shibahara, paragraph [0060], acquire the data from another L1 cache when it is not stored in L1 cache 115). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to combine Pohlack and Shibahara when a request for data misses a cache in Pohlack, the data may be copied from another one of Pohlack’s cache storing the data instead of being loaded from Pohlack’s memory 106, so that access latency may be reduced. As such, the combined teachings of Pohlack and Shibahara teach the limitation of “copying the data from the first cache to the second cache”, but still fail to teach providing coherent access by preventing write access to the first cache prior to the copying step.
Beard teaches an analogous system wherein coherent access is provided by preventing write access to a source memory prior to copying the data from the source memory to a destination memory (see Beard, paragraph [0033], lines 1-7, paragraph [0047], lines 11-21 and paragraph [0051], lines 1-4, the source memory region S is locked to prevent write accesses, then data is copied from the source memory region to the destination memory region). Although Beard does not teach the copying is between the first cache and a second cache, it is solving the problem of maintaining coherency by preventing write access to the source data storage before the copying is performed to ensure the correct/coherent data is stored in the destination data storage (see Beard, paragraph [0036] for solving coherence issues by locking source write accesses). Because the combined teaching of Pohlack and Shibahara is directed to copying data between the first cache and the second cache which are accessible by multiple processing cores 108-114, it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to further incorporate Beard by preventing write access to Pohlack’s first cache in order to ensure data coherency between the first cache and the second cache in the combined teaching of Pohlack and Shibahara. As a result, the combined teaching of Pohlack, Shibahara and Beard collectively teach the limitation of “provide coherent access to the data …… by preventing write access to the first cache prior to copying the data from the first cache to the second cache”.
Per claim 16, Pohlack teaches:
A system (see Fig. 1, computing device 100) comprising:
one or more memory arrays (see Fig. 1 and paragraph [0022], one or more of various types of memory devices in memory 106);
a first controller (see Fig. 1, cache controller 128) coupled to a first cache (see Fig. 1, one or more of L1/L2 caches 108/110/124); and
a second controller (see Fig. 1, cache controller 130) coupled to a second cache (see Fig. 1, one or more L1/L2 caches 120/122/126), the first controller configured to cause the system to:
communicate an access command associated with accessing data from a memory address of the one or more memory arrays of the system (see paragraph [0024], lines 1-16, processor cores 108-114 each can issue access command to access data from the same location in memory 106), the first cache configured to store the data (see paragraph [0024], lines 1-16, cache blocks are loaded from memory 106 into one of the caches);
wherein coherent access to the data corresponding to the memory address is provided (see paragraph [0024], lines 1-16, processor cores 108-114 may operate on the same data loaded from the same locations in memory 106, and cache coherence among copies of data in different caches is maintained using protocols such as MESI) r
Pohlack does not specifically teach the crossed-out limitations as set forth above. Shibahara teaches an analogous system comprising multiple L1 caches wherein when requested data is not stored in a L1 cache, the cache controller copies the data from the first cache to the second cache (see Shibahara, paragraph [0060], acquire the data from another L1 cache when it is not stored in L1 cache 115). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to combine Pohlack and Shibahara when a request for data misses a cache in Pohlack, the data may be copied from another one of Pohlack’s cache storing the data instead of being loaded from Pohlack’s memory 106, so that access latency may be reduced. As such, the combined teachings of Pohlack and Shibahara teach the limitation of “copy the data from the first cache to the second cache”, but still fail to teach “preventing write access to the first cache responsive to the access command, the copying is performed while write access is prevented to the first cache, and the coherent access is provided responsive to preventing the write access to the first cache and copying the data from the first cache to the second cache”.
Beard teaches “preventing write access to a source memory responsive to an access command, copying data from the source memory to a destination memory while write access is prevented to the source memory, and the coherent access is provided responsive to preventing the write access to the source memory and copying the data from the source memory to the destination memory (see Beard, paragraph [0033], lines 1-7, paragraph [0047], lines 11-21 and paragraph [0051], lines 1-4, the source memory region S is locked to prevent write accesses, then data is copied from the source memory region to the destination memory region). Although Beard does not teach the copying is between the first cache and a second cache, it is solving the problem of maintaining coherency by preventing write access to the source data storage before the copying is performed to ensure the correct/coherent data is stored in the destination data storage (see Beard, paragraph [0036] for solving coherence issues by locking source write accesses). Because the combined teaching of Pohlack and Shibahara is directed to copying data between the first cache and the second cache which are accessible by multiple processing cores 108-114, it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to further incorporate Beard by preventing write access to Pohlack’s first cache in order to ensure data coherency between the first cache and the second cache in the combined teaching of Pohlack and Shibahara. As a result, the combined teaching of Pohlack, Shibahara and Beard collectively teach the limitation of “preventing write access to the first cache responsive to the access command, the copying is performed while write access is prevented to the first cache, and the coherent access is provided responsive to preventing the write access to the first cache and copying the data from the first cache to the second cache”. Note that the combined teaching of Pohlack and Shibahara already teach that the copying is responsive to an access command. As a result the preventing of write access is also responsive to the access command as it is performed for the copying.
The combined teachings of Pohlack, Shibahara and Beard further teach: perform an access operation for the data, responsive to the access command, after copying the data from the first cache to the second cache (see Pohlack, paragraph [0024], lines 1-16, processor cores 108-114 each can issue access command to access data from the same location in memory 106, and one processor core will access the copied data after the copying).
Per claim 9, the method is performed by the system of claim 16 as set forth above, as such it is rejected on the same grounds mutatis mutandis.
Dependent Claims:
Per claim 3, the combined teachings of Pohlack, Shibahara and Beard further teach prevent the first cache from being written to or read from prior to copying the data from the first cache to the second cache (see Beard, paragraph [0033], lines 1-7, paragraph [0047], lines 11-21 and paragraph [0051], lines 1-4, the source memory region S is locked to prevent write accesses, then data is copied from the source memory region to the destination memory region and the rejection of claim 1 set forth above for similar limitations).
Per claim 13, the claim is the method claim corresponding to the system claim 3, as such it is rejected on the same grounds mutatis mutandis.
Per claim 17, the combined teachings of Pohlack, Shibahara and Bridge further teach the first controller is further configured to cause the system to flush the data stored in the first cache to an array of the one or more memory arrays, the flushing responsive to determining that a cache line of the first cache is populated, that the data has not been written to the one or more memory arrays, or both (see Bridge, paragraph [0033], flush modified cache line from cache to DRAM. Here “modified” is interpreted to mean “populated”. Note that paragraph [0056] of the instant application’s specification states that “a cache line can be populated if the cache line actively stores data”; note Pohlack’s cache controller 128/first controller is the one controlling the flushing of its own cache).
Per claim 5, the combined teachings of Pohlack, Shibahara and Beard further teach the system is configured to enable access to the first cache after copying the data from the first cache to the second cache (see Beard, paragraph [0051], after completion of copying, release the locked memory region).
Per claim 11, the claim is the method claim corresponding to the system claim 5, as such it is rejected on the same grounds mutatis mutandis.
Per claim 18, the combined teachings of Pohlack, Shibahara and Beard further teach the first controller is further configured to cause the system to enable access to the first cache after copying the data from the first cache to the second cache (see Beard, paragraph [0051], after completion of copying, release the locked memory region).
Per claim 6, the combined teachings of Pohlack, Shibahara and Beard further teach the first controller is further configured to request a transfer of the data to provide coherency between the first cache and the second cache, wherein the system is configured to provide coherent access to the data responsive to the request (see the rejection of claim 1 set forth above and see Shibahara, paragraph [0060], the acquisition of the data from another L1 cache when it is not stored in L1 cache 115 can be viewed as requesting a transfer of the data to provide coherency between the first and second caches).
Per claim 12, the claim is the method claim corresponding to the system claim 6, as such it is rejected on the same grounds mutatis mutandis.
Per claim 19, the claim recites substantially the same limitations as claim 6, as such it is rejected on the same grounds.
Per claim 7, the combined teachings of Pohlack, Shibahara and Bridge further teach a coupling of a host system of the system (see Pohlack, Fig. 1, processor 104) to a memory system of the system (see Pohlack, Fig. 1, memory 106) is configured to communicate, from the host system to the memory system via the first processing resource (see Pohlack, Fig. 1, core 112/114), the second processing resource, or both, an access request utilizing an interface that is used to synchronize the memory system and the host system (see Pohlack paragraph [0024], lines 1-16, cache blocks are loaded from memory 106 into one of the caches, and processor cores 108-114 may operate on the same data loaded from the same locations in memory 106. Here, the loading of data from memory 106 into a cache of a processor is viewed as synchronizing the memory system and the host system, as the processor will store the same data value after the loading. The interfacing/connection between memory 106 and processor 104 is viewed as the claimed interface).
Per claim 14, the claim is the method claim corresponding to the system claim 7, as such it is rejected on the same grounds mutatis mutandis.
Claims 2, 8, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pohlack, and further in view of Shibahara and Beard, and further in view of Boyer et al. [Pub.No.: US 20170344479 A1] (hereinafter “Boyer”).
Per claim 2, the combined teachings of Pohlack, Shibahara and Beard further teach the second controller (see Pohlack, Fig. 1, cache controller 130), the second cache (see Pohlack, Fig. 1, one or more L1/L2 caches 120/122/126), and the second processing resource (see Pohlack, Fig. 1, cores 112/114) are included in a host system (see Pohlack, Fig. 1, processor 104) coupled to a memory system (see Pohlack, Fig. 1, memory 106). Pohlack, Shibahara and Beard do not teach or render obvious “the one or more memory arrays, the first controller, the first cache, and the first processing resource are included in a memory system”.
Boyer teaches an analogous system wherein processor-in-memory techniques are utilized to improve energy efficiency and performance (see Boyer, paragraph [0003], lines 1-5). In Boyer, a processor-in-memory (PIM) 102 is coupled to a host processor 110 and includes at least one cache (see Boyer, paragraph [0006], lines 25-27) of a corresponding processor 104 (see Boyer, Figs. 1-3). The processor-in-memory 102 further includes one or more memory arrays (see Boyer, Fig. 2, stacked memory channels) and at least one controller for providing coherency (see Boyer, Fig. 3, controllers 320 and 322, and paragraphs [0006] and [0018]). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to incorporate Boyer’s PIM into Pohlack’s computing device 100 to improve energy efficiency and performance. By incorporation, Pohlack’s memory 106 and processor 102 would be modified in similar fashion as Boyer’s PIM, and the combined teaching would result in “the one or more memory arrays (Pohlack’s memory 106), the first controller (Pohlack’s cache controller 128), the first cache (one or more of Pohlack’s L1/L2 caches 116-124), and the first processing resource (Pohlack’s cores 108/110) being included in a memory system (the resulting PIM by combined Pohlack and Boyer)” and coupled to Polack’s host system (Polack’s processor 104).
Per claim 15, the limitations of the instant claim are recited in claim 2 as set forth above, as such it is rejected on the similar grounds mutatis mutandis.
Per claim 8, the analysis and reasoning set forth above in the rejection of claim 2 for the combining of Boyer with the teachings of Pohlack, Shibahara and Beard is similarly applied to the instant claim. In short, Pohlack’s memory 106 and processor 104 would be modified in similar fashion as Boyer’s PIM to improve energy efficiency and performance. As a result, Pohlack, Shibahara and Beard in view of Boyer further teach the first processing resource comprises one or more processors (see Pohlack, Fig. 1, processor 102 comprising cores 108/110) configured to access the one or more memory arrays (Pohlack’s memory 106, now included in a PIM by the way of incorporation with Boyer) by communicating with the second controller (see Pohlack, Fig. 1, cache controller 130. Also note that in Fig. 1, cache controller 128 and cache controller 130 are communicatively coupled to each other); and the second processing resource comprises one or more controllers (see Pohlack, Fig. 1, processor 104 and cache controller 130; see Boyer, Fig. 3, controllers 320 and 322) configured to perform read operations, write operations, logical operations, vector operations, or any combination thereof, associated with the data stored to the first cache and the one or more memory arrays (as Pohlack’s memory 106 is now part of PIM, memory 106’s data access by processor 102 will be handled by the controllers in the PIM comprising memory 106 and processor 104).
Per claim 20, the analysis and reasoning set forth above in the rejection of claim 2 for the combining of Boyer with the teachings of Pohlack, Shibahara and Beard is similarly applied to the instant claim. In short, Pohlack’s memory 106 and processor 104 would be modified in similar fashion as Boyer’s PIM to improve energy efficiency and performance. As a result, Pohlack, Shibahara and Beard in view of Boyer further teach a first processing resource coupled to the first controller (see Pohlack, Fig. 1, processor cores 108/110 coupled to cache controller 128) configured to access the one or more memory arrays (Pohlack’s memory 106, now included in a PIM by the way of incorporation with Boyer) by communicating with the second controller (see Pohlack, Fig. 1, cache controller 130. Also note that in Fig. 1, cache controller 128 and cache controller 130 are communicatively coupled to each other); and a second processing resource coupled to the second controller (see Pohlack, Fig. 1, processing cores 112/114 coupled to cache controller 130; see Boyer, Fig. 3, controllers 320 and 322) and configured to perform read operations, write operations, logical operations, vector operations, or any combination thereof, associated with the data stored to the first cache and the one or more memory arrays (as Pohlack’s memory 106 is now part of PIM, memory 106’s data access by processor 102 will be handled by the controllers in the PIM comprising memory 106 and processor 104),
wherein the first controller is further configured to cause the system to (Pohlack’s cores 108/110 requests data that’s not found in caches 108/110/124, therefore Pohlack’s cache controller 128 manages the access to memory 106):
communicate, between a host system of the system (see Pohlack, Fig. 1, processor 102) and a memory system of the system (see Pohlack, Fig. 1, when combined with Boyer, the PIM comprising processor 104 and memory 106) via the first processing resource (Pohlack’s cores 108/110 requests data), the second processing resource, or both, an access request utilizing an interface that is used to synchronize the memory system and the host system (see Pohlack paragraph [0024], lines 1-16, cache blocks are loaded from memory 106 into one of the caches, and processor cores 108-114 may operate on the same data loaded from the same locations in memory 106. Here, the loading of data from memory 106 into processor 102 is viewed as synchronizing the memory system and the host system, as processor 102 will store the same data value after the loading. The interfacing/connection between processor 102 and the PIM comprising memory 106 and processor 104 is viewed as the claimed interface).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pohlack, and further in view of Shibahara and Beard, and further in view of Bridge, JR. et al. [Pub.No.: US 2014036734 A1] (hereinafter “Bridge”).
Per claim 4, the combined teachings of Pohlack, Shibahara and Beard do not specifically teach the system is configured to flush the data stored in the first cache to an array of the one or more memory arrays, the flushing responsive to determining that a cache line of the first cache is populated, that the data has not been written to the one or more memory arrays, or both. Bridge teaches “flush the data stored in the first cache to an array of the one or more memory arrays, the flushing responsive to determining that a cache line of the first cache is populated” (see Bridge, paragraph [0033], flush modified cache line from cache to DRAM. Here “modified” is interpreted to mean “populated”. Note that paragraph [0056] of the instant application’s specification states that “a cache line can be populated if the cache line actively stores data”). The combined art of Pohlack, Shibahara and Beard comprises a cache memory system, and cache flushing in cache memory systems to free up cache capacity and ensure data consistency is a well-known operation. It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to incorporate Bridge’s teaching into the combined art of Pohlack, Shibahara and Beard to free up cache capacity and ensure data consistency by flushing data stored in the first cache to a memory array responsive to determining that the first cache has been modified.
Per claim 10, the claim is the method claim corresponding to the system claim 4, as such it is rejected on the same grounds mutatis mutandis.
Response to Arguments
Applicant’s arguments filed on 10 July 2026 regarding the 35 U.S.C. 103 rejections of claims 1-20 have been considered but are moot in view of the new grounds of rejection set forth above. The Applicant’s arguments regarding the 35 U.S.C. 103 rejections are based on the previously cited Bridge reference. As this reference has been replaced by the newly cited Beard reference, the Applicant should refer to the new ground of rejections set forth above for a response to the arguments.
Applicant’s argument regarding the 35 U.S.C. 112(a) rejections are respectfully traversed. Applicant’s argument states the specification discloses one-to-one relationship between the controllers 212 and the cache units corresponding to the cache 214 and between the cache line address registers 213 of each of the controllers 212 and the cache lines of each of the cache units. Applicant concludes that preventing access to a cache line is equivalent to preventing access to a corresponding cache “if there were a one-to-one relationship between the two”. The Examiner fails to understand which entities are “the two” referred to by the Applicant, or why a one-to-one relationship between them necessarily equates a cache line to an entire cache. Therefore the rejection of claims 1-20 on the grounds of 35 U.S.C. 112(a) stands.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
10 September 2026
Prosecution Insights