DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 6/26/26, which has been entered.
1. REJECTIONS NOT BASED ON PRIOR ART
a. DEFICIENCIES IN THE CLAIMED SUBJECT MATTER
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11416395 and claims 1-20 of US Patent # 12386742. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1, as an example, of both patents anticipate claim 1 of the instant application and thus would be obvious. The dependent claims and other independent claims would be obvious for similar reasons as claim 1 noted above.
Claim Rejections - 35 USC ' 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea (i.e. mental processes) without significantly more. The claim(s) recite(s) (e.g. claim 1) abstract idea to monitor usages of the first memory and the second memory; and adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory. This judicial exception is not integrated into a practical application because the limitations above are merely directed towards mental processes. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the claimed invention is directed towards generic computing components (e.g. a module, host interface, memory components, and processor device) to perform the abstract ideas; and wherein the processing device stores an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; and monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory. The Examiner notes the generic computing components and the storing an address map are well-understood, routine, conventional computer device(s)/function. The Examiner further notes to monito usages of the first memory and the second memory and to adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory. Therefore, the claimed invention is directed to an abstract idea without significantly more for the reasons set forth above. The Examiner notes the dependent claims 2-16 and claims 17-20 do not recite any further limitations that overcome the rejections above as they merely discuss in further detail the computing components or abstract idea(s) noted above.
2. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 13, and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nathuji (US 2012/0047312 A1).
With respect to claim 1, the Nathuji reference teaches a computing system, comprising:
a module (see fig. 8, computing device 800) comprising:
a host interface; (paragraph 46, where computing device 800 also includes an input interface 810 that allows external devices to communicate with the computing device 800. For instance, the input interface 810 may be used to receive instructions from an external computer device, from a user, etc) and
a plurality of memory components, comprising first memory and second memory, wherein the first memory and the second memory have different speeds when accessed through the host interface via at least one bus; (see fig. 2 and 8; and paragraph 20, where there is a near and far memories with different speeds; and paragraphs 45-46) and
a processing device, operatively coupled with the plurality of memory components through the at least one bus to access the first memory and the second memory via the host interface; (see fig. 2 and 8, processor 802; and paragraph 46, where computing device 800 also includes an input interface 810 that allows external devices to communicate with the computing device 800. For instance, the input interface 810 may be used to receive instructions from an external computer device, from a user, etc))
wherein the processing device is configured via instructions (see fig. 2; where the virtual machines and its corresponding virtual address space; and paragraph 22) configured to:
store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; (paragraph 22, where specifically, each of the virtual machines 206-208 has a contiguous virtual address space assigned thereto, and such contiguous virtual address space can map to portions of the near memory 202 and the far memory 204)
monitor usages of the first memory and the second memory; (paragraph 44, where the near and far memories are monitored for accesses/usage) and
adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory. (paragraph 20, where the processing device in memory access involves the first memory and the second memory [Note the dynamic/adjustment of allocated memory pages for the near and far memories]; and paragraph 26, where the predictor can move data that is predicted to be accessed soon into the near memory).
With respect to claim 2, the Nathuji reference teaches the computing system of claim 1, wherein the first memory is faster than the second memory; (paragraph 20, where the lower latency and higher bandwidth of the first/near memory, thus being faster than the second/far memory) and
the processing device accesses the second memory over the at least one bus without accessing the first memory for a portion of memory access requests in the computing system. (fig. 1 and paragraph 20, where the processor accesses the second/far memory over one bus and access the first/near memory using a different bus as shown in Fig. 1)
With respect to claim 3, the Nathuji reference teaches the computing system of claim 1, wherein the first memory is faster than the second memory; (paragraph 20, where the lower latency and higher bandwidth of the first/near memory, thus being faster than the second/far memory) and the first memory and the second memory share a common physical host interface to the bus. (see fig. 8, where memory 802 is connected to processor 802 via common bus 802; and paragraph 45, where memory 804 may be or include RAM, ROM, EEPROM, Flash memory, or other suitable memory. Additionally, the memory 804 may be asymmetric memory that comprises different pools, wherein the pools have different performance characteristics with respect to the processor 802.)
With respect to claim 13, the Nathuji reference teaches the computing system of claim 1, wherein the first memory and the second memory are in a same memory module; (paragraph 45, where memory 804 may be or include RAM, ROM, EEPROM, Flash memory, or other suitable memory. Additionally, the memory 804 may be asymmetric memory that comprises different pools, wherein the pools have different performance characteristics with respect to the processor 802) and at least a portion of the second memory is not directly addressable on the at least one bus. (paragraph 22, where each of the virtual machines 206-208 has a contiguous virtual address space assigned thereto, and such contiguous virtual address space can map to portions of the near memory 202 and the far memory 204 [i.e. there is a translation to access the physical memory])
With respect to claim 15, the Nathuji reference teaches the computing system of claim 1, wherein the first memory and the second memory are in separate memory modules that are coupled to a central processing unit via a same memory bus. (see fig. 8, where memory 802 is connected to processor 802 via common bus 802; and paragraph 45, where memory 804 may be or include RAM, ROM, EEPROM, Flash memory, or other suitable memory. Additionally, the memory 804 may be asymmetric memory that comprises different pools, wherein the pools have different performance characteristics with respect to the processor 802.)
With respect to claim 16, the Nathuji reference teaches the computing system of claim 1, wherein the first memory and the second memory are in separate memory systems that are coupled to a central processing unit via separate communication channels. (see fig. 1, where the near memory and far memory are attached via different channels)
Claim 17 is the method implementation of claim 1, and rejected under a similar rationale as above.
With respect to claim 18, the Nathuji reference teaches the method of claim 17, further comprising generating, by a hypervisor, information that is used to predict the usages of the first memory and the second memory. (paragraph 27, where the memory management system 214 may be implemented as a portion of a hypervisor)
With respect to claim 19, the Nathuji reference teaches the method of claim 18, wherein the information comprises at least one of: a sequence of pages being used in a period of time; instances of requests to load pages from the second memory to the first memory; content attributes of the pages loaded from the second memory to the first memory; ownership attributes of the pages loaded from the second memory to the first memory; identifications of users of the pages loaded from the second memory to the first memory; identifications applications loaded from the second memory to the first memory; an identification of pages that are accessed in a sequential mode in a virtual machine; an identification of pages that pages are accessed in a sequential mode in a user account; and an identification of page accesses that are in a steady state. (paragraph 23, where system 200 further comprises a monitor component 210 that monitors accesses to the near memory 202 and the far memory 204 by the virtual machines 206-208 over time. For instance, the monitor component 210 can be configured to monitor accesses to each page in the virtual address spaces corresponding to the virtual machines 206-208, which may map to the near memory 202 and the far memory 204)
Claim 20 is the non-transitory computer storage medium implementation of claim 1, and rejected under a similar rationale as above.
Claims 4-6, 10-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of the Nathuji (US 2012/0047312 A1) in view of Smith (US Patent # 8,930,647).
With respect to claim 4, the Nathuji reference explicitly teach the computing system of claim 3, wherein the first memory and the second memory are disposed in a same memory module.
The Smith reference teaches it is conventional to have wherein the first memory and the second memory are disposed in a same memory module. (see fig. 1a, where there is a first and second memory with different classes in the same physical memory; and corresponding text to the figure; and column 22, line 1-24, where the memory management systems (e.g. VMM in CPU, MMU in CPU, software in OS, combinations of these possibly with new hardware and/or software, etc.) may be used to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Nathuji reference to have wherein the first memory and the second memory are disposed in a same memory module, as taught by the Smith reference.
The suggestion/motivation for doing so would have been to have a multi-class memory apparatus for receiving instructions via a single memory bus (Smith, column 9, lines 6-11); and to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present. (Smith, column 22, line 1-24)
Therefore it would have been obvious to combine the Nathuji and Smith references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 5, the combination of the Nathuji and Smith references teaches the computing system of claim 4, wherein the bus is a memory bus; [Smith, Note Fig. 1a and Col. 2 states a “memory bus”] (See Col. 2 lines 1-3 and Fig. 1a)
and the memory module is a dual in-line memory module (DIMM). [Smith, Note Fig. 59-1B the DIMMS memory module] (See Fig. 59-1B and Col. 81 lines 48-55).
With respect to claim 6, the combination of the Nathuji and Smith references teaches the computing system of claim 5, wherein the memory module includes a controller. (Nathuji, fig. 2 and paragraph 22, where the virtual machines and its corresponding virtual address space; and paragraph 32, where the virtual machine used to balance data between the memories)
With respect to claim 10, the combination of the Nathuji and Smith references teaches the computing system of claim 5, wherein the instructions are configured as a device driver of the memory module running in the processing device. (Smith, see fig. 1a, where there is a first and second memory with different classes in the same physical memory; and corresponding text to the figure; and column 22, line 1-24, where the memory management systems (e.g. VMM in CPU, MMU in CPU, software in OS, combinations of these possibly with new hardware and/or software, etc.) may be used to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present)
With respect to claim 11, the combination of the Nathuji and Smith references teaches the computing system of claim 10, wherein the device driver runs in the processing device to: receive an address of a memory access request to be made by the processing device; (Smith, Col. 71 lines 43-48, where there is a request to allocate memory]) convert the address to a converted address based on the address map; (Smith, Fig. 39 and Col. 57 lines 57-67 and Col. 58 lines 1-2) and make the memory access request on the bus according to the converted address. (Smith, Fig. 39 and Col. 57 lines 57-67 and Col. 58 lines 1-2).
With respect to claim 13, the Nathuji reference teaches the computing system of claim 1, wherein at least a portion of the second memory is not directly addressable on the at least one bus. [Nathuji, fig. 1, where the near and far memories are not directly accessible as they have to operate through a processor via a bus]
However, the Nathuji reference does not explicitly teach that the computing system of claim 1, wherein the first memory and the second memory are in a same memory module.
The Smith reference teaches it is conventional to have wherein the first memory and the second memory are disposed in a same memory module. (see fig. 1a, where there is a first and second memory with different classes in the same physical memory; and corresponding text to the figure; and column 22, line 1-24, where the memory management systems (e.g. VMM in CPU, MMU in CPU, software in OS, combinations of these possibly with new hardware and/or software, etc.) may be used to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Nathuji references to have wherein the first memory and the second memory are disposed in a same memory module, as taught by the Smith reference.
The suggestion/motivation for doing so would have been to have a multi-class memory apparatus for receiving instructions via a single memory bus (Smith, column 9, lines 6-11); and to allow the main memory to hide (either partially or completely from the CPU and/or OS) the fact that there are multiple memory classes present. (Smith, column 22, line 1-24)
Therefore it would have been obvious to combine the Nathuji and Smith references for the benefits shown above to obtain the invention as specified in the claim.
Claims 7-9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of the Nathuji (US 2012/0047312 A1) in view of Smith (US Patent # 8,930,647), and further view of Yoo (US 2013/0152086).
With respect to claim 7, the combination of the Nathuji and Smith references does not teach the computing system of claim 6, wherein in response to a request to access a memory location currently in the second memory, the controller swaps data content between a portion of the first memory and a portion of the second memory, in response to a determination that data content in the portion of the first memory is accessed less frequently than the portion of the second memory.
The Yoo reference teaches it is conventional to wherein in response to a request to access a memory location currently in the second memory, the controller swaps data content between a portion of the first memory and a portion of the second memory, in response to a determination that data content in the portion of the first memory is accessed less frequently than the portion of the second memory. (paragraph 53, where at step 550, the swap-in/swap-out operation may be performed. For example, data stored at the logical address of the virtual swap device may be transferred to the virtual system memory (swap-in), or data stored in the virtual system memory may be transferred to the virtual swap device having the logical address (swap-out). Accordingly, through the swap-in operation, the virtual machine may have, for example, frequently-accessed data stored in the virtual swap device (e.g., an external memory) transferred into the virtual system memory (e.g., an internal memory) having a higher access speed)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Nathuji reference to swap data wherein in response to a request to access a memory location currently in the second memory, the controller swaps data content between a portion of the first memory and a portion of the second memory, in response to a determination that data content in the portion of the first memory is accessed less frequently than the portion of the second memory, as taught by the Yoo reference.
The suggestion/motivation for doing so would have been to have frequently-accessed data stored in the virtual swap device (e.g., an external memory) transferred into the virtual system memory (e.g., an internal memory) having a higher access speed. (Yoo, paragraph 53)
Therefore it would have been obvious to combine the Nathuji, Smith, and Yoo references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 8, the combination of the Nathuji, Smith, and Yoo references teaches the computing system of claim 7, wherein swapping of the data content between the portion of the first memory and the portion of the second memory is performed within the memory module without going through the bus. (Nathuji, see fig. 8, where memory 804 is connected to processor 802 via common bus 802; and paragraph 45, where memory 804 may be or include RAM, ROM, EEPROM, Flash memory, or other suitable memory. Additionally, the memory 804 may be asymmetric memory that comprises different pools, wherein the pools have different performance characteristics with respect to the processor 802 [i.e. the swap occurs within memory 804])
With respect to claim 9, the combination of the Nathuji, Smith, and Yoo references teaches the computing system of claim 7, wherein the swapping of the data content between the portion of the first memory and the portion of the second memory is performed after accessing the memory location in the second memory. (Yoo, paragraph 53, where at step 550, the swap-in/swap-out operation may be performed. For example, data stored at the logical address of the virtual swap device may be transferred to the virtual system memory (swap-in), or data stored in the virtual system memory may be transferred to the virtual swap device having the logical address (swap-out). Accordingly, through the swap-in operation, the virtual machine may have, for example, frequently-accessed data stored in the virtual swap device (e.g., an external memory) transferred into the virtual system memory (e.g., an internal memory) having a higher access speed)
With respect to claim 12, the combination of the Nathuji and Smith references does not teach the computing system of claim 10, wherein the device driver is configured to adjusts the address map to place first data in the first memory and second data in the second memory based on a determination that first data is accessed more frequently in a time period than the second data.
The Yoo reference teaches it is conventional to have wherein the device driver is configured to adjusts the address map to place first data in the first memory and second data in the second memory based on a determination that first data is accessed more frequently in a time period than the second data. (paragraph 53, where at step 550, the swap-in/swap-out operation may be performed. For example, data stored at the logical address of the virtual swap device may be transferred to the virtual system memory (swap-in), or data stored in the virtual system memory may be transferred to the virtual swap device having the logical address (swap-out). Accordingly, through the swap-in operation, the virtual machine may have, for example, frequently-accessed data stored in the virtual swap device (e.g., an external memory) transferred into the virtual system memory (e.g., an internal memory) having a higher access speed)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Nathuji and Smith references to have wherein the device driver is configured to adjusts the address map to place first data in the first memory and second data in the second memory based on a determination that first data is accessed more frequently in a time period than the second data, as taught by the Yoo reference.
The suggestion/motivation for doing so would have been to have frequently-accessed data stored in the virtual swap device (e.g., an external memory) transferred into the virtual system memory (e.g., an internal memory) having a higher access speed. (Yoo, paragraph 53)
Therefore it would have been obvious to combine the Nathuji, Smith, and Yoo references for the benefits shown above to obtain the invention as specified in the claim.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Nathuji and Smith as shown in the rejections above, and further in view of Hurst (US 20020196659 A1).
With respect to claim 14, the combination of the Nathuji and Smith references teaches the computing system of claim 13, wherein the first memory is volatile dynamic random-access memory. (Nathuji, par. [0021], where “…the near memories 106-108 may be DRAM…”)
Nathuji and Smith are silent on teaching that the second memory is non-volatile cross-point memory.
Hurst discloses a second memory is non-volatile cross-point memory [Note Hurst shows a memory module that is a non-volatile cross point memory] (See par. [0021]).
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the teachings of Nathuji and Smith with a second memory that is non-volatile cross-point memory as taught by Hurst.
The motivation for doing so would have been to reduce current density (Hurst, See par. [0107]).
Therefore it would have been obvious to combine the Nathuji, Smith, and Yoo references for the benefits shown above to obtain the invention as specified in the claim.
3. ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Double Patenting
Applicant's arguments with respect to claims 1-20 have been considered and have been noted.
Rejections - USC 101
Applicant's arguments and amendments with respect to claims 1-20 have been considered and not persuasive. The Examiner notes the Applicant’s arguments merely argues that is “significantly more than mental processes”, which is not persuasive. The Examiner notes the reasoning set forth above as to why the rejections have been maintained.
4. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments and amendments (see pages 1-2 of the remarks) with respect to claims 1-20 have been considered but are not persuasive. The Examiner notes the citations have been updated to show how the Nathuji reference teaches the limitation. Particularly, the Nathuju reference teaches a module (see fig. 8, computing device 800) comprising: a host interface; (paragraph 46, where computing device 800 also includes an input interface 810 that allows external devices to communicate with the computing device 800. For instance, the input interface 810 may be used to receive instructions from an external computer device, from a user, etc) and a plurality of memory components, comprising first memory and second memory, wherein the first memory and the second memory have different speeds when accessed through the host interface via at least one bus; (see fig. 2 and 8; and paragraph 20, where there is a near and far memories with different speeds; and paragraphs 45-46) and a processing device, operatively coupled with the plurality of memory components through the at least one bus to access the first memory and the second memory via the host interface; (see fig. 2 and 8, processor 802; and paragraph 46, where computing device 800 also includes an input interface 810 that allows external devices to communicate with the computing device 800. For instance, the input interface 810 may be used to receive instructions from an external computer device, from a user, etc)). Therefore, based on the citations above, the Nathuji reference teaches the claimed invention as argued by the Applicant and thus the rejections have been maintained as shown above.
5. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights