Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 12 May 2026.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: processing device in claim 1, support for which was taken as subject matter disclosed in [0018] of the Specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-14 of U.S. Patent No. 11023166. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present case are broader than and encompass the subject matter of the parent case.
Claims 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of copending Application No. 17321354 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present case are broader than and encompass the subject matter of the parent case.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8, 11-14,18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated DeRosa (US Pat No. 10310923).
As per claim 1, a memory system (see DeRosa FIG 2: 240), comprising:
a plurality of memory components (see DeRosa FIG 2: 209 and COL 6 LINES 19-20); and
a processing device (see DeRosa FIG 2: 206), operatively coupled with the plurality of memory components, to:
receive read requests from a host system to retrieve data from the memory components (see DeRosa COL 3 LINES 55-60);
store the read requests in a buffer (see DeRosa FIG 2: 212 and COL 6 LINES 5-10);
track ages of the read requests (see DeRosa FIG 3: 302 and COL 7 LINES 5-10); and
schedule execution of a first read request from the buffer based on an age of the first read request and a threshold time period (see DeRosa FIG 9: 914 and COL 15 LINES 1-10).
As per claim 2, the memory system of claim 1,
wherein the processing device is further to: determine that the age of the first read request has reached a threshold time period, wherein a second read request is in the buffer at a time when the age of the first read request has reached the threshold time period, and wherein the host system specifies a priority for the second read request that is higher than a priority of the first read request; and cause the first read request to be executed prior to the second read request in the buffer, in response to a determination that the age of the first read request has reached the threshold time period (see DeRosa COL 5 LINES 1-5).
[DeRosa discloses prioritizing discloses a time out age adjustment in the scheduling algorithm based on an age threshold (see COL 13 LINES 50-60).]
As per claim 3, the memory system of claim 2,
wherein the processing device is further to: determine an execution priority of the first read request based on the priority of the first read request specified by the host system and the age of the first read request relative to the threshold time period (see DeRosa COL 13 LINES 20-25).
As per claim 4, the memory system of claim 3,
wherein the processing device is further to: determine the threshold time period for the first request based on the priority of the first read request specified by the host system (see DeRosa COL 13 LINES 20-25).
As per claim 8, the memory system of claim 1,
wherein the processing device is further to: transmit a response signal to the host system; and in response to a send command from host system, transmit data retrieved for the first read request to the host system (see DeRosa COL 4 LINES 20-30).
As per claim 11, the memory system of claim 8,
wherein the execution of the first read request is scheduled to limit, according to the threshold time period, elapsed time between receiving the first read request in the memory system and transmitting the response signal for the first read request (see DeRosa COL 5 LINES 1-5).
As per claim 12, a method, comprising:
receiving, in a memory system, read requests from a host system to retrieve data from memory components of the memory system (see DeRosa COL 3 LINES 55-60);
storing the read requests in a buffer (see DeRosa FIG 2: 212 and COL 6 LINES 5-10);
tracking ages of the read requests (see DeRosa FIG 3: 302 and COL 7 LINES 5-10); and
scheduling execution of the read requests based the ages of the read requests (see DeRosa FIG 9: 914 and COL 15 LINES 1-10).
As per claim 13, the method of claim 12, further comprising:
causing a first read request to be executed in response to a determination that an age of the first read request has reached a threshold time period (see DeRosa COL 5 LINES 1-5).
As per claim 14, the method of claim 13,
wherein first read request is executed before a second read request that is in the buffer when the age of the first read request has reached the threshold time period; and wherein the host system specifies a higher priority for the second read request than the first read request (see DeRosa COL 5 LINES 1-5).
[DeRosa discloses prioritizing discloses a time out age adjustment in the scheduling algorithm based on an age threshold (see DeRosa COL 13 LINES 50-60).]
As per claim 18, a non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to:
receive, in a memory system, read requests from a host system to retrieve data from memory components of the memory system (see DeRosa COL 3 LINES 55-60);
store the read requests in a buffer (see DeRosa FIG 2: 212 and COL 6 LINES 5-10);
track ages of the read requests buffer (see DeRosa FIG 2: 212 and COL 6 LINES 5-10); and
schedule execution of the read requests based at least in part on whether pendency periods of the read requests in the memory system have exceeded a threshold (see DeRosa FIG 9: 914 and COL 5 LINES 1-5).
As per claim 19, the non-transitory computer-readable storage medium of claim 18,
wherein the instructions that, when executed by the processing device, further cause the processing device to: elevate priority of a first read request for execution in response to a determination that a pendency period of the first read request in the memory system has exceeded the threshold (see DeRosa COL 5 LINES 1-5).
[DeRosa discloses prioritizing discloses a time out age adjustment in the scheduling algorithm based on an age threshold (see DeRosa COL 13 LINES 50-60).]
As per claim 20, the non-transitory computer-readable storage medium of claim 18,
wherein the instructions that, when executed by the processing device, further cause the processing device to: add a first read request in a queue in response to a determination that a pendency period of the first read request in the memory system has exceeded the threshold (see DeRosa COL 5 LINES 1-5)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5-7,15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over DeRosa (US Pat No. 10310923) in view of Jain (US PG PUB No. 2006/0136659).
As per claim 5, the memory system of claim 1,
However, DeRosa does not expressly disclose but in the same field of endeavor Jain discloses
wherein the processing device is further to: cause the first read request to be executed prior to the second read request in the buffer by moving the first read request to a queue of read commands, wherein commands in the queue are executed in an order of commands in the queue (see Jain FIG 4: 116 and [0036])
[Jain discloses placing scheduled commands in a read fifo and a write fifo respective.]
It would have been obvious before the effective filing date of the invention to modify DeRosa to further implement a read fifo and a write fifo for schedule commands as taught by Jain.
The suggestion/motivation for doing so would have been for the benefit of coherency management (see Jain [0048]).
Therefore it would have been obvious before the effective fling date of the invention to further queue commands in a read fifo and a write fifo as taught by Jain for the benefit of coherency management to arrive at the invention as specified in the claims.
As per claim 6, the memory system of claim 5,
wherein the processing device is further to: move the first read request to a top of the queue (see DeRosa FIG 9: 914 and COL 13 LINES 20-25).
As per claim 7, the memory system of claim 5,
wherein the processing device is further to: move the first read request to the queue from a lower priority queue (see Jain FIG 4: 116 and [0036])
As per claim 15, the method of claim 12,
However, DeRosa does not expressly disclose but in the same field of endeavor Jain discloses
wherein the scheduling includes: moving the first read request to a queue of read commands in response to a determination that the age of the first read request has reached a threshold time period (see Jain FIG 4: 116 and [0036])
[Jain discloses placing scheduled commands in a read fifo and a write fifo respective.]
It would have been obvious before the effective filing date of the invention to modify DeRosa to further implement a read fifo and a write fifo for schedule commands as taught by Jain.
The suggestion/motivation for doing so would have been for the benefit of coherency management (see Jain [0048]).
Therefore it would have been obvious before the effective fling date of the invention to further queue commands in a read fifo and a write fifo as taught by Jain for the benefit of coherency management to arrive at the invention as specified in the claims.
As per claim 16, the method of claim 15,
wherein the first read request is moved to a top of the queue (see DeRosa FIG 9: 914 and COL 13 LINES 20-25).
As per claim 17, the method of claim 15,
wherein the queue is a first queue; and the first read request is moved to a bottom of the second queue; wherein commands in the second queue are scheduled for execution after the first queue is emptied (see Jain FIG 4: 120 and [0038]).
Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over DeRosa (US Pat No. 10310923) in view of FARMAHINI FARAHANI (US PG PUB No. 2019/0189210).
As per claim 9, the memory system of claim 8,
However, DeRosa does not expressly disclose but in the same field of endeavor FARMAHINI FARAHANI
wherein the read requests, the response signal, and the send command are in accordance with a communication protocol for non-volatile dual in-line memory modules (see FARMAHINI FARAHANI [0009]).
It would have been obvious before the effective filing date of the invention to modify DeRosa to implement a host interface in accordance with NVDIMM-P.
The suggestion/motivation for doing so would have been for the benefit of of improving memory access operations (see FARMAHINI FARAHANI [0008]).
Therefore it would have been obvious before the effective filing date of the invention to modify DeRosa to implement a host interface in accordance with NVDIMM-P as taught by FARMAHINI FARAHANI for the benefit of improving memory access operations to arrive at the invention as specified in the claims.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over DeRosa (US Pat No. 10310923) in view of FARMAHINI FARAHANI (US PG PUB No. 2019/0189210) as applied to claim 9 above and further in view of Bonen (US PG PUB No. 20160092307).
As per claim 10, DeRosa discloses the memory system of claim 9,
wherein the memory components include non- volatile memory (see DeRosa FIG 2: 209 and COL 6 LINES 35-40);
a communication channel (see DeRosa FIG 2:206) between the host system (see DeRosa FIG 2: 202) and the memory sub-system (see DeRosa FIG 2: 209) includes:
However, DeRosa does not expressly disclose but in the same field of endeavor Bonen discloses
a command bus to transmit the read command (see Bonen FIG 4: 442 and [0038]);
a data bus to transmit the data retrieved for the first read request (see Bonen FIG 4: 444 and [0038]); and
a transaction bus to transmit, from the memory system to the host system bus (see Bonen FIG 4: 446 and [0038]) and , the response signal (see Bonen [0040]: “For example, DQ interface 424, 444 can include one or more additional pins and signal lines for transferring metadata.”).
It would have been obvious before the effective filing date of the invention to further implement parallel busses as taught by Bonen.
The suggestion/motivation for doing so would have been for the benefit of a more dynamic bus configuration (see Bonen [0044])
Therefore it would have been obvious before the effective filing date of the invention to further implement parallel bus configuration as taught by Bonen for the benefit of a more dynamic bus configuration to arrive at the invention as specified in the claims.
RESPONSE TO ARGUMENTS
1st ARGUMENT:
DeRosa discloses a probabilistic approach to sort commands for execute in a data storage device (DSD). FIG. 2 of DeRosa shows a data storage device (DSD) 200 having components in a casing 240, including a host interface 204. Col. 5, lines 54-60, of DeRosa states: "The interface 204 may comprise any interface that allows communication between a host 202 and a DSD 200, either wired or wireless, such as USB, IEEE 1394, Compact Flash, SATA, eSATA, PATA, SCSI, SAS, PCIe, Fibre Channel, Ethernet, or Thunderbolt, among others." Thus, a person of ordinary skills in the relevant fields would understand that the data storage device 200 is designed as a computer peripheral device, and thus not suitable to function a memory module. There is no indication that the interface 204 of DeRosa is operable to communicate with the host 202 according to a protocol of memory module in general and more specifically, a protocol of non-volatile dual in-line memory module (NVDIMM).
The claims do not recite or otherwise require a memory module or a protocol of non-volatile dual in-line memory module (NVDIMM).
2nd ARGUMENT:
In contrast, claim 18 recites "receive, in a memory system, read requests from a host system according to a protocol for non-volatile dual in-line memory module (NVDIMM) to retrieve data from memory components of the memory system", which feature is not found in DeRosa. Thus, DeRosa cannot anticipate claim 18 and its dependent claims.
Claim 18 does not recite “receive, in a memory system, read requests from a host system according to a protocol for non-volatile dual in-line memory module (NVDIMM) to retrieve data from memory components of the memory system.”
3rd ARGUMENT:
Claim 1 recites "schedule execution of a first read request from the buffer based on an age of the first read request", which feature is not found in DeRosa. For example, FIG. 2 of the present application shows the parallel buses 121, 123, 125, and 127. There is no indication that the host interface 204 of DeRosa can support schedule execution of a first read request from the buffer based on an age of the first read request. Thus, DeRosa cannot anticipate claim 1 and its dependent claims.
DeRosa discloses the system may track an age for each command (see DeRosa COL 7 LINES 5-10) and further discloses commands may have a designated timeout age threshold, where the command may be executed regardless of its position in the Command Queue (see COL 7 LINES 15-20). DeRosa discloses the argued subject matter to the extent required by the claims.
4th ARGUMENT:
DeRosa does not disclose scheduling execution of read requests based on 1) the priority levels specified by the host for the read requests; and 2) the ages of the read requests. Thus, DeRosa cannot anticipate claims 12 and 18.
Claims 12 and 18 do not recite priority levels specified by the host for the read request as argued. As noted in response to the 3rd ARGUMENT, DeRosa discloses tracking an age of the requests and scheduling based on if the pendency periods of the read request have exceeded a threshold.
5th ARGUMENT:
As discussed above, the probabilistic approach of DeRosa appears to be computationally intensive (e.g., involving calculating estimated access times, probability of reaching a time-out age threshold, and determining time out-adjusted access time) and thus slow. Thus, a person of ordinary skills in the relevant fields would not apply the probabilistic approach of DeRosa to a memory module, as indicated by the fact that DeRosa did not suggest using the probabilistic approach for a memory module. As a result, Jain is insufficient to cure the deficiencies of DeRosa. Thus, the pending claims are seen allowable.
The argument does not appear to be drawn to a specific claim limitation and argues the reference generally. DeRosa discloses tracking an age of commands and scheduling the commands based on pendency period and therefore discloses claimed subject matter to the extent required by the claims.
CONCLUSION
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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