DETAILED ACTION
Reissue
The present reissue application is directed to US 10,607,995 B2 (“995 Patent”). 995 Patent issued on March 31, 2020 with claims 1-34 from application 15/973,697 filed on May 8, 2018, and claims priority to 62/502,999 filed on May 8, 2017.
This application was filed on January 15, 2025. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the first inventor to file provisions of the AIA .
This application is a continuation reissue of reissue application 18/243,035, which is a continuation reissue of reissue application 17/463,420 (now US RE49,715 E).
This application presents broadened claims, which are permitted because Applicant filed these claims and demonstrated an intent to broaden within two years of the issue date of 995 Patent (see claims filed on August 31, 2021 in parent reissue application 17/463,420).
The most recent amendment was filed on January 15, 2025. The status of the claims is:
Claims 1, 4, 11, 17, 23, and 24: Amended
Claims 2, 3, and 6: Original (claim 3 will be treated as pending, not canceled; see 35 U.S.C. 112(b) rejection below)
Claims 5, 7-10, 12-16, 18-22, and 25-34: Canceled
Claims 35-45: New
This is a first, non-final action.
References and Documents Cited in this Action
995 Patent (US 10,607,995 B2)
Ikeda (US 9,698,272 B1)
US RE49,715 E
18/243,035 (parent application of the present application)
Summary of Rejections and Objections in this Action
Examiner objects to the specification amendment and the reissue declaration.
Claims 1-4, 6, 11, 17, 23, 24, and 35-45 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251.
Claims 1-4, 6, 11, 17, 23, and 24 are rejected under 35 U.S.C. 251 because the reissue application is not correcting an error in the original patent.
Claims 1-4, 6, 11, 17, 23, and 24 are rejected under 35 U.S.C. 112(b) as being indefinite.
Claims 1-4, 6, 11, 17, 23, 24, and 35-45 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ikeda.
Claims 1-4, 6, 11, 17, 23, 24, and 35-38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2-4, 6, 11, 17, 18, and 22-24 of U.S. Patent No. US RE49,715 E.
Claims 1-4, 6, 11, 17, 23, and 35 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 37-43 of copending Application No. 18/243,035.
Summary of the Claims
995 Patent is directed to a memory array including tiers of memory cells. Claim 35 is representative:
35. A memory structure, comprising:
multiple tiers of memory cells, the memory cells individually comprising:
a transistor comprising a semiconductor structure extending along a first direction and comprising a first source drain region, a channel region and a second source/drain region, the channel region being oriented for current flow along the first direction, and comprising a gate operatively proximate the channel region; and
a data storage element comprising first and second electrodes having an insulator there-between;
a conductive structure extending through the multiple tiers along a second direction that crosses the first direction, individual of the second source/drain regions of individual of the transistors being electrically coupled to the conductive structure.
Claims 1, 23, and 35 are the independent claims. Claim 1 further recites alternating tiers of insulative material and memory cells. Claim 23 further recites alternating tiers of insulative material and memory cells; and a capacitor-electrode structure.
Certificate of Correction in Parent Reissue
This reissue application is a continuation reissue of US RE49,715 E and 18/243,035. The prior reissue patents have issued without the cross reference to this reissue application of the family which is required pursuant to 37 CFR 1.177(a). Accordingly, Applicant must request a Certificate of Correction in the prior reissue patents to insert language in the first sentence of the specification, such as:
“Notice: More than one reissue application has been filed for the reissue of patent US 10,607,995 B2. The reissue applications are US RE49,715 E, 18/243,035, and 19/022,987.”
Specification
Examiner objects to the amendment to the specification filed on January 15, 2025 because it does not comply with 37 CFR 1.173. Matter to be omitted by reissue must be enclosed in brackets, not strikethrough.
Oath/Declaration
The reissue oath/declaration filed with this application is defective because the statement of error is insufficient (see 37 CFR 1.175 and MPEP § 1414):
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For an application filed on or after September 16, 2012 that seeks to enlarge the scope of the claims of the patent, the reissue oath or declaration must identify a claim that the application seeks to broaden in the identification of the error that is relied upon to support the reissue application. A general statement, e.g., that all claims are broadened, is not sufficient to satisfy this requirement. In specifically identifying the error as required by 37 CFR 1.175(a), it is sufficient that the reissue oath/declaration identify the claim being broadened and a single word, phrase, or expression in the specification or in an original claim, and how it renders the original patent wholly or partly inoperative or invalid. For example, Applicant may state that patent claim 1 is broadened and identify a word or phrase in patent claim 1 that is not recited in the new claims.
Examiner notes that this reissue application is a continuation reissue of prior reissues. The declaration in the present reissue application may identify a new error; or if the same error corrected in the parent is also being corrected in this continuation reissue application, but the error is being corrected in a different way, a statement is needed to explain compliance with 37 CFR 1.175(f)(2) for a reissue application filed on or after September 16, 2012. For example, Applicant should further explain how a same error is being corrected in a different way in this reissue application.
Furthermore, the three inventors are currently named on three separate sheets each labeled “Page 1 of 2,” which is improper. Instead, after the first inventor named on page 1, the second and third inventors should be named in a “Supplement Sheet for Declaration” (PTO/AIA /10).
Applicant must submit a new reissue declaration (rather than merely correct the error statement in remarks) because no proper reissue declaration has been yet entered in this reissue application. Examiner reminds Applicant that any subsequent reissue declarations should also note on page 1 that the specification was already filed on January 15, 2025 in this reissue 19/022,987 instead of being attached hereto:
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Claim Rejections - 35 USC § 251
Claims 1-4, 6, 11, 17, 23, 24, and 35-45 are rejected as being based upon a defective reissue declaration under 35 U.S.C. 251 as set forth above. See 37 CFR 1.175.
The nature of the defect(s) in the declaration is set forth in the discussion above in this Office action.
Claims 1-4, 6, 11, 17, 23, and 24 are rejected under 35 U.S.C. 251 because the reissue application is not correcting an error in the original patent. Claims 1-4, 6, 11, 17, 23, and 24 of 995 Patent have been superseded by the previous reissue US RE49,715 E. Once a claim in the patent has been reissued, it does not exist in the original patent; thus, it cannot be reissued from the original patent in another reissue application. Applicant should cancel claims 1-4, 6, 11, 17, 23, and 24. The subject matter recited in claims 1-4, 6, 11, 17, 23, and 24 may be presented as additional new claims. See MPEP 1451 I for further details (the discussion therein of numbering claims in a divisional reissue application applies also to this continuation reissue).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6, 11, 17, 23, and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-4, 6, 11, 17, 23, and 24 are indefinite because the inventions of claims 1-4, 6, 11, 17, 23, and 24 are not particularly pointed out and distinctly claimed. Claims 1-4, 6, 11, 17, 23, and 24 present one coverage in previous reissue US RE49,715 E and another in the present reissue application. This is inconsistent. Once a claim in the patent has been reissued, it does not exist in the original patent; thus, it cannot be reissued from the original patent in another reissue application. See MPEP 1451 I for further details (the discussion therein of numbering claims in a divisional reissue application applies also to this continuing reissue).
Claim 3 is also indefinite because the amendment filed January 15, 2025 states “Cancel 3” and it is unclear whether this claim is canceled or pending:
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In this Office action, claim 3 is treated as a pending claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 11, 17, 23, 24, and 35-45 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ikeda.
Regarding independent claim 1, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses a memory array (Figures 3, 4, 5A-B, 6A-B, 21 and 22), comprising:
alternating tiers of insulative material (i.e., interlayer insulating layers 17) and memory cells (column 10, lines 22-67; column 11, lines 1-37; Figures 3, 21, and 22), the memory cells individually comprising:
a transistor (i.e., transistor Tij) comprising first and second source/drain regions (i.e., regions above and below channel region 15), a channel region 15 and a gate G operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current (Ikeda’s “Third Direction,” which is up/down in Figures 5A-B and 6A-B, is the claimed horizontal direction; column 2, lines 44-52; column 5, lines 26-64); and
a capacitor (i.e., capacitor Cij) comprising first and second electrodes (electrodes 12 and 14) having a capacitor insulator 13 there-between, the first electrode being electrically coupled to the first source/drain region (column 5, lines 26-64; Figures 5A-B and 6A-B); and
a conductive line structure (i.e., bit lines BL0-3) extending through the alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the conductive line structure (i.e., bit lines BL0-3 extend in Ikeda’s “First Direction” that is orthogonal to Ikeda’s “Third Direction” as shown in Figure 3 and 4, and is the unlabeled direction going through the page in Figures 5A-B and 6A-B; column 4, lines 31-66; column 5, lines 1-64; see also bit lines BL extending in Ikeda’s “First Direction” in Figures 23 and 24A-B; column 11, lines 60-67; column 12, lines 1-39).
Again, Ikeda’s Third Direction is the claimed horizontal direction and the conductive line structure (i.e., bit lines BL) extends in Ikeda’s First Direction:
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Regarding claim 2, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that all of the channel region is horizontally-oriented for horizontal current flow there-through (again, Ikeda’s “Third Direction,” which is up/down in Figures 5A-B and 6A-B, is the claimed horizontal direction; column 2, lines 44-52; column 5, lines 26-64).
Regarding claim 3, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that the first electrode (of capacitor C) is directly electrically coupled to the first source/drain region (of transistor T; Figures 5A-B and 6A-B; column 5, lines 26-64).
Regarding claim 4, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that individual of the second source/drain regions of individual of the transistors T that are in different memory cell tiers are electrically coupled to the conductive line structure BL (Figures 3 and 4; again, bit lines BL0-3 extend in Ikeda’s “First Direction” as shown in Figure 3 and 4, and is the unlabeled direction going through the page in Figures 5A-B and 6A-B; column 4, lines 31-66; column 5, lines 1-64; see also bit lines BL extending in Ikeda’s “First Direction” in Figures 23 and 24A-B; column 11, lines 60-67; column 12, lines 1-39.
Regarding claim 6, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that the second capacitor electrodes of the multiple capacitors are directly electrically coupled with one another (i.e., electrodes 12 are in different memory cells; Figures 3, 5A-B, and 6A-B).
Regarding claim 11, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that the channel-region comprises two channel-region segments spaced apart relative one another in a straight-line cross-section (i.e., channel regions 15 of memory cells are segments spaced apart relative one another in a straight-line cross-section; Figure 3, 5A-B, and 6A-B).
Regarding claim 17, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses the channel region comprises an annulus (Figures 5A-B, 6A-B, and 23).
Regarding independent claim 23, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses a memory array (Figures 3, 4, 5A-B, 6A-B, 21 and 22), comprising:
alternating tiers of insulative material (i.e., interlayer insulating layers 17) and memory cells (column 10, lines 22-67; column 11, lines 1-37; Figures 3, 21, and 22), the memory cells individually comprising:
a transistor (i.e., transistor Tij) comprising first and second source/drain regions having a channel region there-between (i.e., channel region 15 and regions above and below it) and a gate G operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow (Ikeda’s “Third Direction,” which is up/down in Figures 5A-B and 6A-B, is the claimed horizontal direction; column 2, lines 44-52; column 5, lines 26-64); and
a capacitor (i.e., capacitor Cij) comprising first and second electrodes (electrodes 12 and 14) having a capacitor insulator 13 there-between, the first electrode being electrically coupled to the first source/drain region (column 5, lines 26-64; Figures 5A-B and 6A-B);
a capacitor-electrode structure extending through the alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the capacitor-electrode structure (i.e., electrodes 12 are in different memory cells; Figures 3, 5A-B, and 6A-B); and
a conductive line structure (i.e., bit lines BL0-3) electrically coupled to multiple of the second source/drain regions of individual of the transistors (i.e., bit lines BL0-3 extend in Ikeda’s “First Direction” that is orthogonal to Ikeda’s “Third Direction” as shown in Figure 3 and 4, and is the unlabeled direction going through the page in Figures 5A-B and 6A-B; column 4, lines 31-66; column 5, lines 1-64; see also bit lines BL extending in Ikeda’s “First Direction” in Figures 23 and 24A-B; column 11, lines 60-67; column 12, lines 1-39).
Regarding claim 24, as well as the claim may be understood with respect to 35 U.S.C. 112(b) as discussed above, Ikeda discloses that the capacitor-electrode structure is directly electrically coupled to an elongated capacitor-electrode construction that is above or below the vertically-alternating tiers (Figure 3).
Regarding independent claim 35, Ikeda discloses a memory structure (Figures 3, 4, 5A-B, and 6A-B), comprising:
multiple tiers of memory cells, the memory cells individually comprising:
a transistor (i.e., transistor Tij) comprising a semiconductor structure extending along a first direction (i.e., Ikeda’s “Third Direction,” which is up/down in Figures 5A-B and 6A-B, is the claimed first direction) and comprising a channel region 15 and first and second source/drain regions above and below channel region 15 , the channel region being oriented for current flow along the first direction (Ikeda’s “Third Direction,” which is up/down in Figures 5A-B and 6A-B, is the claimed first direction; column 2, lines 44-52; column 5, lines 26-64), and comprising a gate G operatively proximate the channel region; and
a data storage element (i.e., capacitor Cij) comprising first and second electrodes (electrodes 12 and 14) having an insulator 13 there-between (column 5, lines 26-64);
a conductive structure (i.e., bit lines BL0-3) extending through the multiple tiers along a second direction that crosses the first direction, individual of the second source/drain regions of individual of the transistors being electrically coupled to the conductive structure (i.e., Ikeda’s First Direction is the claimed second direction; bit lines BL0-3 extend in Ikeda’s “First Direction” that is orthogonal to Ikeda’s “Third Direction” as shown in Figure 3 and 4, and is the unlabeled direction going through the page in Figures 5A-B and 6A-B; column 4, lines 31-66; column 5, lines 1-64; see also bit lines BL extending in Ikeda’s “First Direction” in Figures 23 and 24A-B; column 11, lines 60-67; column 12, lines 1-39).
Regarding claim 36, Ikeda discloses that the second direction is orthogonal to the first direction (i.e., Ikeda’s First Direction is the claimed second direction and Ikeda’s Third Direction is the claimed first direction).
Regarding claim 37, Ikeda discloses that the first source/drain region comprises an annulus (Figures 5A-B, 6A-B, and 23).
Regarding claim 38, Ikeda discloses that the gate comprises an annulus (Figures 5A-B, 6A-B, and 23).
Regarding claim 39, Ikeda discloses that the gate is part of an access line (i.e., gate equalizing line GEQ; column 7, lines 51-67; column 8, lines 1-12).
Regarding claim 40, Ikeda discloses an electrode structure extending along the second direction, second electrodes of multiple of the capacitors being electrically coupled to the electrode structure (again, Ikeda’s First Direction is the claimed second direction; electrodes 12 are in different memory cells extending in that direction; Figures 3, 5A-B, and 6A-B).
Regarding claim 41, Ikeda discloses that the electrode structure comprises a pillar (Figures 3, 5A-B, and 6A-B).
Regarding claim 42, Ikeda discloses that the electrode structure is electrically coupled to an elongated electrode construction disposed above or below the multiple tiers of memory cells (Figure 3).
Regarding claim 43, Ikeda discloses that the elongated electrode construction has a line configuration, at least in the sense that electrodes 12 are in different memory cells extending in a line; Figures 3, 5A-B, and 6A-B)
Regarding claim 44, Ikeda discloses that the elongated electrode construction has a plate configuration, at least in the sense that electrodes 12 are plate electrodes (Figures 5A-B, 6A-B, 24A, and 24B; column 5, lines 26-57; column 12, lines 1-35)
Regarding claim 45, Ikeda discloses that the gate is a first gate and wherein the transistor further comprises a second gate operatively proximate the channel region (Figures 6A-B).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6, 11, 17, 23, 24, and 35-38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2-4, 6, 11, 17, 18, and 22-24 of U.S. Patent No. US RE49,715 E. Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding independent reissue claims 1 and 35, although the recited elements are not identical to the elements of claim 1 of US RE49,715 E, they are not patentably distinct from each other because they are of the same scope of invention with claim 1 of US RE49,715 E anticipating the instant claims. Reissue claims 1 and 35 and claim 1 of US RE49,715 E are directed to a memory array/structure including tiers of memory cells, the memory cells comprising: a transistor comprising first and second source/drain regions, a channel region oriented along a first/horizontal direction and a gate operatively proximate the channel region; a data storage element (or capacitor) comprising first and second electrodes having an insulator there-between; and a conductive structure extending through the tiers in a second/vertical direction. Dependent reissue claim 36 further recites that the second direction is orthogonal to the first direction, which is also recited in claim 1 of US RE49,715 E as orthogonal “horizontal” and “vertical” directions. Given claim 1 of US RE49,715 E, it would have been obvious to create reissue claims 1, 35, and 36 by slightly changing the wording of limitations and/or removing limitations.
Dependent reissue claims 2-4, 6, 11, and 17, which depend on reissue claim 1, recite limitations that substantially correspond to limitations recited in dependent claims 2-4, 6, 11, and 17 of US RE49,715 E and are also rejected on the ground of nonstatutory double patenting as being unpatentable over those claims respectively.
Dependent reissue claims 37 and 38, which depend on reissue claim 35, recite limitations that substantially correspond to limitations recited in dependent claims 18 and 22 of US RE49,715 E and are also rejected on the ground of nonstatutory double patenting as being unpatentable over those claims respectively.
Regarding independent reissue claim 23, although the recited elements are not identical to the elements of claim 23 of US RE49,715 E, they are not patentably distinct from each other because they are of the same scope of invention with claim 23 of US RE49,715 E anticipating the instant claims. Reissue claim 23 and claim 23 of US RE49,715 E are directed to a memory array including tiers of memory cells, the memory cells comprising: a transistor comprising first and second source/drain regions, a channel region oriented along a horizontal direction and a gate operatively proximate the channel region; a capacitor comprising first and second electrodes having an insulator there-between; a capacitor-electrode structure extending through the alternating tiers; and a conductive line structure extending through the tiers in a second/vertical direction. Given claim 23 of US RE49,715 E, it would have been obvious to create reissue claim 23 by slightly changing the wording of limitations and/or removing limitations.
Dependent reissue claim 24, which depends on reissue claim 23, recite limitations that substantially correspond to limitations recited in dependent claim 24 of US RE49,715 E and is also rejected on the ground of nonstatutory double patenting as being unpatentable over that claim.
Claims 1-4, 6, 11, 17, 23, and 35 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 37-43 of copending Application No. 18/243,035 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding independent reissue claims 1 and 35, although the recited elements are not identical to the elements of claim 37 of 18/243,035, they are not patentably distinct from each other because they are of the same scope of invention with claim 37 of 18/243,035 anticipating the instant claims. Reissue claims 1 and 35 and claim 37 of 18/243,035 are directed to a memory array/structure including tiers of memory cells, the memory cells comprising: a transistor comprising first and second source/drain regions, a channel region oriented along a first/horizontal direction and a gate operatively proximate the channel region; a data storage element (or capacitor) comprising first and second electrodes having an insulator there-between; and a conductive structure extending through the tiers in a second/vertical direction. Dependent reissue claim 3 further recites that the first electrode is directly electrically coupled to the first source/drain region, which is also recited in claim 37 of 18/243,035. Dependent reissue claim 36 further recites that the second direction is orthogonal to the first direction, which is also recited in claim 37 of 18/243,035 as orthogonal “horizontal” and “vertical” directions. Given claim 37 of 18/243,035, it would have been obvious to create reissue claims 1, 3, 35, and 36 by slightly changing the wording of limitations and/or removing limitations.
Dependent reissue claims 2, 4, 6, 11, and 17, which depend on reissue claim 1, recite limitations that substantially correspond to limitations recited in dependent claims 38-42 of 18/243,035 and are also rejected on the ground of nonstatutory double patenting as being unpatentable over those claims respectively.
Regarding independent reissue claim 23, although the recited elements are not identical to the elements of claim 43 of 18/243,035, they are not patentably distinct from each other because they are of the same scope of invention with claim 43 of 18/243,035 anticipating the instant claims. Reissue claim 23 and claim 43 of 18/243,035 are directed to a memory array including tiers of memory cells, the memory cells comprising: a transistor comprising first and second source/drain regions, a channel region oriented along a horizontal direction and a gate operatively proximate the channel region; a capacitor comprising first and second electrodes having an insulator there-between; a capacitor-electrode or conductive structure extending through the alternating tiers; and another conductive line structure extending through the tiers in a second/vertical direction. Given claim 43 of 18/243,035, it would have been obvious to create reissue claim 23 by slightly changing the wording of limitations and/or removing limitations.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
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Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992
/Patricia L Engle/SPRS, Art Unit 3991
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