DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6 and 8 of U.S. Patent No. 12,074,599. Although the claims at issue are not identical, they are not patentably distinct from each other because they essentially teach similar subject matter.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/815,521 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of ‘512 teaches substantially similar subject matter as that of claims 1-20 of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Muralimanohar (US 2012/0017065).
With respect to claim 1,
Figure 2 of Muralimanohar discloses a device, comprising:
a first integrated circuit die (202); and
the first integrated circuit die (202) connected to a second integrated circuit die (201) by at least one through-silicon via (224).
With respect to claim 2,
Muralimanohar further teaches wherein the first integrated circuit die comprises a first plurality of functional block of memory elements (see MATs on 202 – such as 225) and the second integrated circuit die comprises a second plurality of functional block of memory elements (see MATs on 201 – such as 207-222).
With respect to claim 3,
Muralimanohar further teaches wherein the first plurality of functional block of memory elements comprises a first block of memory elements and a second block of memory elements (see 225 and neighboring MAT on 202).
With respect to claim 4,
Muralimanohar further teaches wherein the first block of memory elements is connected to the second block of memory elements by an interconnect (Paragraph 23 – where similar to 201, 202 has a center bus connecting each of the MATs).
With respect to claim 5,
Muralimanohar further teaches wherein the second plurality of functional block of memory elements (see MATs on 201 – such as 207-222) comprises a third block of memory elements (219) and a fourth block of memory elements (215).
With respect to claim 6,
Muralimanohar further teaches wherein the first block of memory elements is connected to the third block of memory elements by a first through-silicon via of the at least one through-silicon via (see Figure 2 – where 225 is connected to 219 with TSV 224).
With respect to claim 7,
Muralimanohar further teaches wherein the second block of memory elements is connected to the fourth block of memory elements by a second through-silicon via of the at least one through-silicon via (see Figure 2 – where 215 is connected to the neighboring block of 225 with TSV 224).
With respect to claim 8,
Muralimanohar further teaches wherein the first integrated circuit die comprises a first non- volatile memory die and the second integrated circuit die comprises a second non-volatile memory die (Paragraph 18).
With respect to claim 9,
Muralimanohar further teaches wherein the first integrated circuit die comprises a non- volatile memory die and the second integrated circuit die comprises a processing logic die (Paragraphs 17-18).
With respect to claim 10,
Muralimanohar further teaches wherein the first integrated circuit die comprises a processing logic die and the second integrated circuit die comprises a volatile memory die (Paragraphs 17-18).
With respect to claim 11,
Muralimanohar further teaches wherein the at least one through-silicon via comprises a first at least one through-silicon via (see 224 of Figure 2), and wherein the device further comprises a third integrated circuit die stacked on top of the second integrated circuit die, wherein the second integrated circuit die is connected to the third integrated circuit die by a second at least one through-silicon via (see Figure 1 – where stacked memory 104 includes four die that are stacked).
With respect to claim 12,
Muralimanohar further teaches wherein the first integrated circuit die comprises a volatile memory die, the second integrated circuit die comprises a processing logic die,and the third integrated circuit die comprises a non-volatile memory die (Paragraphs 17-18 and 22).
With respect to claim 13,
Muralimanohar further teaches wherein the first integrated circuit die comprises a processing logic die, the second integrated circuit die comprises a first non-volatile memory die, and the third integrated circuit die comprises a second non-volatile memory die (Paragraphs 17-18 and 22).
With respect to claim 14,
Muralimanohar further teaches wherein the device is partitioned into a plurality of columns each comprising a respective functional block of each of the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die (Paragraph 16 – where dies are layered in a one to one configuration).
With respect to claim 17,
Figure 2 of Muralimanohar discloses a device, comprising:
a first integrated circuit die (202); and
a second integrated circuit die (201) stacked on top of the first integrated circuit die (see Figure 2), wherein:
a first functional block (225) of the first integrated circuit die (202) is connected to a first functional block (219) of the second integrated circuit die (201) by a first through-silicon via (224 – see Figure 2).
With respect to claim 18,
Muralimanohar further teaches a second functional block (MAT adjacent to 225 on the left) of the first integrated circuit die (202) is connected to a second functional block (215) of the second integrated circuit die (201) by a second through-silicon via (another 224 – see Figure 2), wherein
the first functional block (225) of the first integrated circuit die is connected to the second functional block (MAT adjacent to 225 on the left) of the first integrated circuit die by a first interconnect (223 of 202),
the first functional block (219) of the second integrated circuit die is connected to the second functional block (215) of the second integrated circuit die by a second interconnect (223 of 201), and
the first interconnect is connected to the second interconnect by a third through-silicon via (where the center bus of each memory die is electrically connected by 224).
With respect to claim 19,
Muralimanohar further teaches wherein the first functional block (225) of the first integrated circuit die is connected to five to eight other functional blocks (see Figure 2) of the first integrated circuit die via interconnects (223).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cordero et al. (US 2013/0275823).
With respect to claim 20,
Figure 4 of Cordero discloses a method comprising:
receiving, at a volatile memory die of an integrated circuit device, a request from a controller (see Figure 4 and Paragraph 8); and
receiving, from the volatile memory die at a processing logic die of the integrated circuit device, the request, wherein the request is transmitted through a first through-silicon via connecting the volatile memory die and the processing logic die (see Figure 4 and Paragraphs 8 and 10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jany Richardson whose telephone number is (571)270-5074. The examiner can normally be reached Monday - Friday, 7:00am to 3:00pm.
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/JANY RICHARDSON/Primary Examiner, Art Unit 2844