DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 7/29/2026.
Withdrawn objections and rejections
The specification objection has been withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-17 of U.S. Patent 11,481,221. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent 11,481,221 contains every element of claims 1-20 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
U.S. Patent 11,481,221
1. A computing device, comprising:
1. A computing device, comprising:
a processor having a first branch target buffer and a second branch target buffer;
a processor having a plurality of branch target buffers, the plurality of branch target buffers including a first branch target buffer and a second branch target buffer;
wherein the processor is configured to:
wherein the processor is configured to:
store first branch prediction information execution of a set of instructions in the first branch target buffer, the set of instructions including a call to a subroutine;
perform branch prediction during execution of a set of instructions using first branch prediction information stored in the first branch target buffer;
perform branch prediction during execution of a set of instructions using the first branch prediction information stored in the first branch target buffer; and
and in response to a call to a subroutine, perform prediction information for execution of the instructions of the subroutine using second prediction information stored in the second branch target buffer.
in response to the call to the subroutine: the execution of the set of instructions in the process transfers to execution of the subroutine routine and stops execution of the set of instructions; allocate the second branch target buffer; store second branch prediction information for execution of instructions of the subroutine; perform prediction information for execution of the instructions of the subroutine using the second branch prediction information stored in the second branch target buffer; and
in response to execution of the set of instructions returning from execution of the subroutine, perform branch prediction during further execution of the set of instructions using the first branch prediction information stored in the first branch target buffer and stops the execution of the subroutine; wherein the execution of the instructions of the subroutine is blocked from accessing the first branch prediction information stored in the first branch target buffer.
Independent claims 11 and 17 are read upon by the independent claims 10 and 15 of U.S. Patent 11,481,221. Dependent claims 2-10, 12-16, and 18-20 are read upon by the claims 1-17 of U.S. Patent 11,481,221.
Claims 1-2, 4-11, and 13-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 3-11, 13-17, and 19-20 of U.S. Patent Application 17/948,098. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent Application 17/948,098 contains every element of claims 1-2, 4-11, and 13-20 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
Copending Application 17/948,098
1. A computing device, comprising:
1. A computing device, comprising:
a processor having a first branch target buffer and a second branch target buffer;
a processor having a first branch target buffer and a second branch target buffer;
wherein the processor is configured to:
wherein the processor is configured to:
store first branch prediction information in the first branch target buffer;
perform branch prediction during execution of a set of instructions using first branch prediction information stored in the first branch target buffer;
perform a first branch prediction, during execution of a set of instructions, using the first branch prediction information stored in the first branch target buffer;
and in response to a call to a subroutine, perform prediction information for execution of the instructions of the subroutine using second prediction information stored in the second branch target buffer.
allocate, in response to the set of instructions being executed to call to a subroutine, the second branch target buffer for execution of the subroutine; store second branch prediction information; and perform a second branch prediction, during the execution of the subroutine, using the second branch prediction information stored in the second branch target buffer;
in response to execution of the set of instructions returning from execution of the subroutine, perform branch prediction during further execution of the set of instructions using the first branch prediction information stored in the first branch target buffer; wherein the processor is further configured to block the execution of the subroutine from accessing the first branch prediction information stored in the first branch target buffer.
Independent claims 11 and 17 are read upon by the independent claims 11 and 17 of copending U.S. Patent Application 17/948,098. Dependent claims 2, 4-10, 13-16, and 18-20 are read upon by the dependent claims 3-10, 13-17, and 19-20 of U.S. Patent No./copending U.S. Patent Application 17/948,098.
This is a provisional obviousness-type double patenting rejection.
Claim 3 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending U.S. Patent Application 17/948,098 in view of Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720).
This is a provisional obviousness-type double patenting rejection.
Claim 12 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of copending U.S. Patent Application 17/948,098 in view of Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720), in view of Official Notice.
This is a provisional obviousness-type double patenting rejection.
Maintained Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163).
As per claim 1:
Scott and Kranich disclosed a computing device, comprising:
a processor having a first branch target buffer and a second branch target buffer (Scott: Figures 1 and 4 elements 28-30, 62, and 66, paragraphs 11-12, 15-16, and 23)(The CPU includes a first and second BTB used by multiple threads.);
wherein the processor is configured to:
perform branch prediction during execution of a set of instructions using first branch prediction information stored in the first branch target buffer (Scott: Figures 1 and 4-5 elements 28-30, 66-68, and 82-86, paragraphs 15, 20, 23, and 28)(Branch instruction addresses are sent to the BTBs for branch prediction purposes.); and
in response to a call to a subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Paragraph 18)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions.), perform prediction information for execution of the instructions of the subroutine using second prediction information stored in the second branch target buffer (Kranich: Figure 3B element 338, column 10 line 67 continued to column 11 lines 1-2 and column 12 lines 3-14)(Scott: Figures 1 and 4-5 elements 28-30, 66-68, and 82-86, paragraphs 15, 20, 23, and 28)(The combination allows for the threads of Scott to include fork instructions to create new threads of execution. Branch instruction addresses for the new second thread are sent to the second private BTB for branch prediction purposes.).
The advantage of including fork instructions in thread code is that multiple threads of code can be created to allow for parallel execution and/or the hiding of execution latency. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the fork instruction of Kranich in the processor of Scott for the advantage of increased processor performance from execution of multiple threads at once.
Claims 2-3, 7-8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720).
As per claim 2:
Scott and Kranich disclosed the computing device of claim 1.
Scott and Kranich failed to teach wherein the execution of the instructions of the subroutine is blocked from accessing the first branch prediction information stored in the first branch target buffer.
However, Alexander combined with Scott and Kranich disclosed wherein the execution of the instructions of the subroutine is blocked from accessing the first branch prediction information stored in the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1 for branch prediction.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
As per claim 3:
Scott, Kranich, and Alexander disclosed the computing device of claim 2, wherein the execution of the set of instructions is blocked from accessing the second branch target buffer (Alexander: Figure 3B element 316, paragraph 36) (Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn't explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
As per claim 7:
Scott and Kranich disclosed the computing device of claim 1.
Scott and Kranich failed to teach wherein the execution of the instructions of the subroutine is prevented from accessing branch prediction information stored in the plurality of branch target buffers other than the second branch target buffer.
However, Alexander combined with Scott and Kranich disclosed wherein the execution of the instructions of the subroutine is prevented from accessing branch prediction information stored in the plurality of branch target buffers other than the second branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
As per claim 8:
Scott and Kranich disclosed the computing device of claim 1.
Scott and Kranich failed to teach wherein the execution of the set of instructions is prevented from accessing branch prediction information stored in the plurality of branch target buffers other than the first branch target buffer.
However, Alexander combined with Scott and Kranich disclosed the wherein the execution of the set of instructions is prevented from accessing branch prediction information stored in the plurality of branch target buffers other than the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
As per claim 11:
Scott and Kranich disclosed a method implemented in a computing device, the method comprising:
executing in a program in a processor, wherein the processor has a plurality of branch target buffers, and the program has a plurality of routines (Scott: Figures 1 and 4 elements 28-30, 62, and 66, paragraphs 11-12, 15-16, and 23)(The CPU includes a first and second BTB used by multiple threads.), and the program has a plurality of routines (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Paragraph 18)(Kranich disclosed a single thread including fork instructions that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Each of the threads read upon a routine.); and
allocating the plurality of branch target buffers to execution of the plurality of routines respectively (Kranich: Figure 3B element 334 and 344-346, column 10 lines 56-67 continued to column 11 lines 1-16 and column 12 lines 1-14, table 1)(Scott: Figure 4 element 62, paragraphs 23 and 25)(Kranich disclosed a single thread including fork instructions that create a new thread of execution at a target address. Kranich disclosed the single thread being incomplete due to a later joining of threads and continued execution. The combination allows for the threads of Scott to include fork instructions. Enabling a second thread in Scott allocates the shared or non-used BTB to the second thread for private use. Starting execution of the initial thread allocates a thread BTB for use.);
storing branch prediction information of each respective routine in a respective branch target buffer (Kranich: Figure 3B element 338, column 10 line 67 continued to column 11 lines 1-2 and column 12 lines 3-10)(Scott: Figures 2 and 4-5 elements 48, 52, 62, 66, and 100, paragraphs 16, 18, 23, and 31)(Thread 1 branch prediction information is stored only in BTB1 when both threads are enabled or when no BTB sharing is enabled while thread 0 is disabled. The combination allows for the threads of Scott to include fork instructions to create new threads of execution. Execution of the new second thread in Scott allows for population of the private BTB.).
The advantage of including fork instructions in thread code is that multiple threads of code can be created to allow for parallel execution and/or the hiding of execution latency. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the fork instruction of Kranich in the processor of Scott for the advantage of increased processor performance from execution of multiple threads at once.
Scott and Kranich failed to teach executing the respective routine by accessing branch prediction information only in the respective branch target buffer allocated to the respective routine.
However, Alexander combined with Scott and Kranich disclosed executing the respective routine by accessing branch prediction information only in the respective branch target buffer allocated to the respective routine (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
Claims 4-6, 9-10, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720), further in view of Official Notice.
As per claim 4:
Scott, Kranich, and Alexander disclosed the computing device of claim 3, wherein the second branch target buffer is cleared before the execution of the instructions of the subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 5:
Scott, Kranich, and Alexander disclosed the computing device of claim 3, wherein the second branch target buffer is cleared after returning from the subroutine and before the second branch target buffer is used for execution of a third subroutine called from the set of instructions (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 6:
Scott, Kranich, and Alexander disclosed the computing device of claim 5, wherein the set of instructions is one of:
a subroutine; and
a main routine of a program (Kranich: Figure 3B element 330, column 10 lines 56-67)(Scott: Paragraph 18)(Kranich disclosed a single thread (i.e. main routine) including fork instructions that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions.).
As per claim 9:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the second branch target is cleared after or upon returning from the subroutine to the set of instructions (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 10:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein when the branch target buffers are in use at a time of the call to the subroutine, the second branch target buffer is selected from the plurality of branch target buffers and cleared the second branch target for allocation to the execution of the subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 12:
Scott, Kranich, and Alexander disclosed the method of claim 11, further comprising, in response to returning from the respective routine to a calling routine that calls the respective routine:
de-allocating the respective branch target buffer (Kranich: Figure 3B elements 340-344, column 11 lines 2-6)(Scott: Figure 4 elements 62 and 66, paragraphs 18 and 23)(The combination allows for the threads of Scott to include fork and join instructions. Upon combining the multiple threads, the second thread is disabled and the private BTB is no longer allocated to it.); and
clearing the respective branch target buffer before the respective branch target buffer is allocated to a further routine called by the calling routine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn't incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 13:
Scott, Kranich, and Alexander disclosed the method of claim 11, wherein the processor has a further branch target buffer (Scott: Figure 1 element 28, paragraphs 11 and 15)(The processor includes N BTBs for N threads.); and when a further routine is called while execution of each of the plurality of routines is still incomplete (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Paragraph 18)(Kranich disclosed a single thread including fork instructions that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Each of the threads read upon a routine. Official notice is given that nested thread creation can occur for the advantage of reusing code. Thus, it would have been obvious to one of ordinary skill in the art to implement fork nesting in Kranich.),
allocating the further branch target buffer for execution of the further routine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 element 62, paragraphs 11, 23, and 25)(Kranich disclosed a single thread including fork instructions that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. In view of the above official notice, nested fork calls result in additional threads being created and additional BTBs being allocated to the threads.); and
blocking execution of the further branch target from accessing the plurality of branch target buffers (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraphs 11 and 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for multiple enabled threads (e.g. three plus) to only access their corresponding BTBs.).
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 9. Therefore, claim 14 is rejected for the same reason(s) as claim 9.
As per claim 15:
Scott, Kranich, and Alexander disclosed the method of claim 11, wherein the processor has no further branch target buffer; and when a further routine is called while execution of each of the plurality of routines is still incomplete:
selecting a first branch target buffer from the plurality of branch target buffers, the first branch target buffer being allocated to a first routine in the plurality of routines (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can occur for stalled threads for the advantage of increased performance. Thus, it would have been obvious to implement thread switching in Scott.);
de-allocating the first branch target buffer from the first routine (Scott: Figure 4 elements 62 and 66, paragraph 23)(In view of the above official notice, the newly added thread is assigned the previous thread’s BTB.);
clearing the first branch target buffer (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.);
re-allocating the first branch target buffer for execution of the further routine (Scott: Figure 4 elements 62 and 66, paragraph 23)(In view of the above official notice, the newly added thread is assigned the previous thread’s BTB.); and
blocking execution of the further branch target from accessing the plurality of branch target buffers other than the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraphs 11 and 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for multiple enabled threads (e.g. three plus) to only access their corresponding BTBs.).
As per claim 16:
Scott, Kranich, and Alexander disclosed the method of claim 15, wherein the first routine is the last routine to complete in execution of the plurality of routines (Kranich: Figure 3B element 346)(Scott: Figure 2 element 48)(The combination allows for a main thread to fork additional threads. The main thread is the last to complete.).
As per claim 17:
Scott and Kranich disclosed a processor, comprising:
at least one execution unit (Scott: Figure 2 element 48, paragraph 16); and
an instruction fetch stage having a first branch target buffer and a second branch target buffer (Scott: Figures 1-2 elements 28 and 40, paragraphs 15-16)(Scott disclosed the processor including a plurality of BTBs outside of the fetch unit. Official notice is given that BTBs can be included within a fetch stage for the advantage of performing branch prediction earlier in the pipeline. Thus, it would have been obvious to one of ordinary skill in the art to implement the BTBs in the fetch stage of the processor of Scott.);
wherein during execution of a program having a first routine and a second routine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Paragraph 18)(Kranich disclosed a single thread (i.e. first routine) including fork instructions that create a new thread of execution (i.e. second routine) at a target address. The combination allows for the threads of Scott to include fork instructions.):
the first branch target buffer stores branch prediction information of the first routine (Scott: Figure 4 elements 66-68, paragraph 23)(Thread 1 branch prediction information is stored only in BTB1 (i.e. first BTB) when both threads are enabled or when no BTB sharing is enabled while thread 0 is disabled.);
the second branch target buffer stores branch prediction information of the second routine (Kranich: Figure 3B element 338, column 10 line 67 continued to column 11 lines 1-2 and column 12 lines 3-10)(Scott: Figures 2 and 4-5 elements 48, 52, 62, and 100, paragraphs 16, 18, 23, and 31)(The combination allows for the threads of Scott to include fork instructions to create new threads of execution. Execution of the new second thread in Scott allows for population of the private BTB.).
The advantage of including fork instructions in thread code is that multiple threads of code can be created to allow for parallel execution and/or the hiding of execution latency. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the fork instruction of Kranich in the processor of Scott for the advantage of increased processor performance from execution of multiple threads at once.
Scott and Kranich failed to teach execution of the first routine only accesses the first branch target buffer; and execution of the second routine only accesses the second branch target buffer.
However, Alexander combined with Scott and Kranich disclosed execution of the first routine only accesses the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.); and
execution of the second routine only accesses the second branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 14. Therefore, claim 18 is rejected for the same reason(s) as claim 14.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 13. Therefore, claim 19 is rejected for the same reason(s) as claim 13.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 13. Therefore, claim 20 is rejected for the same reason(s) as claim 13.
Response to Arguments
The arguments presented by Applicant in the response, received on 7/29/2026 are not considered persuasive.
Applicant argues regarding claims 1, 11, and 17:
“Scott discloses the allocation of different branch target buffers (BTB) to different threads. Although two threads may be generated from a single thread via a fork instruction (e.g., as in Kranich), such a fork instruction is seen an instruction to duplicate the current thread and thus not an instruction to call another routine. At the time of a fork instruction, the single thread is duplicated; and the duplicated threads are configured to execute the same instruction. Subsequently, different conditions to be evaluated by the duplicated threads separately can lead to different paths of executions. To execute a routine, a call instruction would be used in a thread. Thus, a fork instruction is not a call instruction. It is possible to use a fork instruction to generate two duplicated threads to perform the same computations, at least for the execution of a number of instructions, without calling a routine. Further, Scott and Kranich do not disclose and/or suggest how such forking is to be handled in the allocation and use of branch target buffers (BTB). Thus, no combination of Scott and Kranich would lead to the feature of “allocate, in response to the set of instructions being executed to call to a subroutine, the second branch target buffer for execution of the subroutine” recited in claim 1 and similar features recited in claims 11, and 17.”
This argument is not found to be persuasive for the following reason. Kranich makes no mention that the thread 2 code involves replicated/duplicated code execution. The terms “duplicat*” or “replicat*” have zero hits in Kranich. In fact, figure 5 shows an example where this isn’t the case. Additionally, no citations were given for this assertion in Kranich.
Instead, Kranich allows for forking to a second thread of execution that allows for parallel execution of a first and second thread. The results of the second thread of execution are returned back to the first thread upon execution of the join instructions. The fork instruction functions as a call instruction in that it’s an unconditional branch to the start of a set of instructions to execute. Thus, reading upon the claimed limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
