DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 07/15/2022. It is noted, however, that applicant has not filed a certified copy of the CN202210833730.4 application as required by 37 CFR 1.55.
Election/Restrictions
Applicant's election with traverse of Specie V (Figure 9) in the reply filed on 05/19/26 is acknowledged. The traversal is on the ground(s) that “the present application realizes logical control of the entire circuit based on the first MOS transistor, the second MOS transistor, the third MOS transistor and the output circuit. The difference lies in: 1. Specific settings for the internal components of the output circuit; 2. Specific settings are made for the control of the first MOS transistor and the control of the first clock signal CLK and the second clock signal CLKND. Therefore, we believe that these modifications are interrelated and will not result in a serious search burden”.
This is not found persuasive because the constructions for each of the identified species are different from each other because each specific identify specie requires the specific first MOS to third MOS transistors Q1-Q3 to be a PMOS transistor or an NMOS transistor, and the specific clock CLK and delayed clock CLKND and the feedback from the output of the various of “Output circuit” 10 to the control terminal of the specific first to third MOS transistors Q1-Q3; and thus the species are distinct from each other
The requirement is still deemed proper and is therefore made FINAL.
Applicant identified that claims 1-4, 7-9 and 13 are read on the elected Specie V (Figure 9). However, upon reconsideration, claims 3-4 are not read on the elected Specie V (Figure 9) because claims 3-4 each requires “the first MOS transistor is an NMOS transistor, the second and third MOS transistors are PMOS transistors” while the specie V (Figure 9) discloses the first MOS transistor (Q1) is an PMOS transistor, the second and third MOS transistors (Q2 and Q3) are NMOS transistors. Thus, only claims 1-2, 7-9 and 13 are read on the elected Specie V (Figure 9) because claims 3-4, as discussed above, are not readable on the elected specie V (Figure 9).
Claim 3-6, 10-12 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Specie, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 05/19/26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ebergen et al. (US 2007/0115040).
For claims 1 and 13, Figure 7B of Ebergen et al. teaches a logic control circuit, comprising: a first MOS transistor (120-1), a second MOS transistor (112-1), a third MOS transistor (112-2), and an output circuit (116-4); a first end of the first MOS transistor (120-1) is connected to a power supply (power supply at source of 120-1), and a second end of the first MOS transistor (120-1) is connected to a first end of the second MOS transistor (112-1); a second end of the second MOS transistor (112-1) is connected to a first end of the third MOS transistor (112-2), and a second end of the third MOS transistor (112-2) is grounded; the second end of the first MOS transistor (120-1) is further used to connect to a first end of the output circuit (input end of 116-4), a second end of the output circuit (output end of 116-4) serves as an output terminal (118-1) of the logic control circuit, and the second end of the output circuit (output end of 116-4) is further used to connect to a control terminal of the first MOS transistor (120-1), so as to control on/off of the first MOS transistor (120-1) through a pulse signal at the second end of the output circuit (116-4); a control terminal of the second MOS transistor (112-1) is used to receive a first clock signal (110-1), and a control terminal of the third MOS transistor (112-2) is used to receive a second clock signal (output of 116-3 to gate of 112-2), a waveform of the second clock signal (output of 116-3 to gate of 112-2) is the same as that of the first clock signal (110-1), and the second clock signal (output of 116-3 to gate of 112-2) is delayed by a preset duration relative to the first clock signal (110-1); when the first MOS transistor (120-1) is switched on, the second end of the first MOS transistor (120-1) is in a high level, and when level of the first clock signal (110-1) is different from that of the second clock signal (output of 116-3 to gate of 112-2), the second MOS transistor (112-1) or the third MOS transistor (112-2) is switched off, so as to keep the second end of the first MOS transistor (120-1) in a high level; and when the first MOS transistor (120-1) is switched off, and when the level of the first clock signal (110-1) is the same as that of the second clock signal (112-2), the second MOS transistor (112-1) and the third MOS transistor (112-2) are both switched on, so as to set the second end of the first MOS transistor (120-1) to a low level.
For claim 7, Figure 7B of Ebergen et al. teaches wherein the first MOS transistor (120-1) is a PMOS transistor (120-1), and the second and third MOS transistors (112-1 and 112-2) are NMOS transistors (112-1 and 112-2); the output circuit (116-4) further comprises: a first inverter (116-4), an input terminal of the first inverter (116-4) is connected to the second end of the first MOS transistor (120-1), and an output terminal of the first inverter (116-4) serves as the second end of the output circuit (116-4); the second end of the output circuit (116-4) is further used to connect to the control terminal of the first MOS transistor (120-1) to control the on/off of the first MOS transistor (120-1) through a pulse signal (118-1) at the second end of the output circuit (116-4), which comprises the control terminal of the first MOS transistor (120-1) receives an inverting signal of the pulse signal (118-1) at the second end of the output circuit (116-4), so as to control the on/off of the first MOS transistor (120-1) through the inverting signal of the pulse signal (118-1) at the second end of the output circuit (116-4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ebergen et al. (US 2007/0115040) in view of Hwang et al. (US 2022/0166427).
For claim 2, Figure 7B of Ebergen et al. teaches all the limitations of this claim (as discussed in claim 1 above), wherein the output circuit (116-4) comprising an inverter (116-4). Ebergen does not teach “wherein the output circuit comprises: a fourth MOS transistor, a control terminal of the fourth MOS transistor serves as a control terminal of the output circuit and is used to receive an enable signal, a first end of the fourth MOS transistor is connected to the power supply, and a second end of the fourth MOS transistor is connected to the second end of the first MOS transistor”. However, Figure 4 of Hwang et al. teaches a logic control circuit wherein the output circuit (C3a) comprising an inverter (I31a) and a fourth MOS transistor (P31a) that has its gate connected to an enable signal (SIG1). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the logic control circuit in Figure 7B of Ebergen so that the output circuit also includes a fourth MOS transistor (P31a) as taught in Figure 4 of Hwang et al. for the purpose of controlling/setting the output of the circuitry to a specific state in response to the enable signal and thus would improve the performance of the circuitry. Thus, the combination/modification now meets all the limitations of claim 2 such that the output circuit, in addition to the inverter (116-4) now also comprising a fourth MOS transistor (P31a), a control terminal of the fourth MOS transistor serves as a control terminal of the output circuit and is used to receive an enable signal (SIG), a first end of the fourth MOS transistor is connected to the power supply (VDD power supply), and a second end of the fourth MOS transistor is connected to the second end of the first MOS transistor (120-1 at the input of inverter 116-4).
For claim 8, Figure 7B of Ebergen et al. in the above combination teaches wherein the first MOS transistor (120-1) is a PMOS transistor (120-1), and the second and third MOS transistors (112-1 and 112-2) are NMOS transistors (112-1 and 112-2); the output circuit (116-4) further comprises: a first inverter (116-4), an input terminal of the first inverter (116-4) is connected to the second end of the first MOS transistor (120-1), and an output terminal of the first inverter (116-4) serves as the second end of the output circuit (116-4); the second end of the output circuit (116-4) is further used to connect to the control terminal of the first MOS transistor (120-1) to control the on/off of the first MOS transistor (120-1) through a pulse signal (118-1) at the second end of the output circuit (116-4), which comprises the control terminal of the first MOS transistor (120-1) receives an inverting signal of the pulse signal (118-1) at the second end of the output circuit (116-4), so as to control the on/off of the first MOS transistor (120-1) through the inverting signal of the pulse signal (118-1) at the second end of the output circuit (116-4).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowed because the closet prior art, Ebergen et al. (US 2007/0115040), Figure 7B teaches, as applied in the rejections above, fails to teach or suggest the logic control circuit further comprising a second inverter, a six MOS transistor which is a PMOS transistor, a seventh MOS transistor and an eighth MOS transistor which are NMOS transistors with the connections and operations as recited in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ijisu (US 7,446,589) disclose pulse generating circuit including first to third transistors Tr1-Tr3, delay circuit, and output circuit keeper circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights