DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The Information Disclosure Statement filed on 17 March 2026 has been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 14 of U.S. Patent 11,099,789 contains every element of claim 1 of the instant application and as such anticipates claim 1 of the instant application.
Claim Correspondence
Instant Application
U.S. Patent No. 11,099,789
1
14
Claim 9 of U.S. Patent No. 11,977,787 contains every element of claim 1 of the instant application and as such anticipates claim 1 of the instant application.
Claim Correspondence
Instant Application
U.S. Patent No. 11,977,787
1
9
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-12, and 14-20 of copending Application No. 18/645,761.
This is a provisional nonstatutory double patenting rejection.
Claim Correspondence
Instant Application
U.S. Patent Application No. 18/645,761
1
1
2
2
3
3
4
1
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
11
14
14
15
15
16
16
17
17
18
18
19
19
20
20
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 11, and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cayton et al. (Pub. No. US 2019/0102287).
Claim 1:
Cayton et al. disclose a device, comprising:
a remote direct memory access network interface card configured to transfer data between a remote apparatus connected to a computer network and a memory module configured on a memory bus in response to a command received via a peripheral interconnect [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. The write data may be stored in the Local NVM. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)].
Claim 2 (as applied to claim 1 above):
Cayton et al. disclose the device, further comprising:
the memory bus [fig. 1 – connection to local NVM]; and
a memory module connected to the memory bus [fig. 1 – local NVM].
Claim 3 (as applied to claim 2 above):
Cayton et al. disclose the device, further comprising:
the peripheral interconnect [fig. 1; par. 0021 - System interface. (“To read/write to the system memory 86, the RPDMA device 50 may need to utilize system interface 84. The system interface 84 may be a PCIe interface which may transmit and receive data over a PCIe bus, or a double-data-rate interface.”)]; and
a host system connected to the memory bus and connected to the peripheral interconnect to send the command [fig. 1; par. 0021 - “The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.”].
Claim 11:
Cayton et al. disclose a method, comprising:
receiving, in a remote direct memory access network interface card via a peripheral interconnect, a command [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)]; and
transferring, in response to the command, data between a remote apparatus connected to a computer network and a memory module configured on a memory bus [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. The write data may be stored in the Local NVM. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)].
Claim 12 (as applied to claim 11 above):
Cayton et al. disclose,
wherein a host system connected to the memory bus and connected to the peripheral interconnect is configured to send the command [fig. 1; par. 0021 - “The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.”].
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al. (Pub. No. US 2019/0102287) as applied to claim 3 and 12 above, respectively, and further in view of Makhervaks et al. (Pub. No. US 2018/0032249).
Claim 4 (as applied to claim 3 above):
Cayton et al. disclose all the limitations above but do not specifically disclose,
wherein the host system is configured to run a driver programmed for the remote direct memory access network interface card and configured to generate the command.
In the same field of endeavor, Makhervaks et al. disclose,
wherein the host system is configured to run a driver programmed for the remote direct memory access network interface card and configured to generate the command [fig. 13; par. 0091 – “The host computer 400 includes an RNIC driver 476, RNIC queues 477, MSIX 478 and an RNIC device interface 479.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cayton et al. to include device drivers, as taught by Makhervaks et al., in order to allow the host to communicate with the device by translating the commands into instructions that the device can understand.
Claim 13 (as applied to claim 12 above):
Claim 13, directed to a method, is rejected for the same reasons set forth in the rejection of claim 4 above.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al. (Pub. No. US 2019/0102287) in view of Makhervaks et al. (Pub. No. US 2018/0032249) as applied to claim 4 above, and further in view of Schmidt et al. (Pub. No. US 2013/0332696).
Claim 5 (as applied to claim 4 above):
Cayton et al. and Makhervaks et al. disclose all the limitations above but do not specifically disclose,
wherein the remote direct memory access network interface card is configured to implement single root input/output virtualization to provide a physical function and a plurality of virtual functions.
In the same field of endeavor, Schmidt et al. disclose,
wherein the remote direct memory access network interface card is configured to implement single root input/output virtualization to provide a physical function and a plurality of virtual functions [par. 0003 – “The existing solution allows the hypervisor to exploit the virtualization provided by the RNIC adapter vendor (referred to as Single Root-I/O Virtualization or SR-IOV). The adapter virtualization requires that the hypervisor use the hardware adapter and the PCIe interface for connectivity within a single platform. This solution can become costly and induce bottlenecks within the platform.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Cayton et al. and Makhervaks et al. to include single root input/output virtualization, as taught by Schmidt et al., in order to enable efficient sharing of a PCIe resource.
Response to Arguments
Applicant's arguments filed April 28, 2026 have been fully considered but they are not persuasive.
Applicant argues that the claimed memory module is distinct from, and is reached by a different connection than, the peripheral interconnect over which the triggering command is received.
Examiner submits that the claimed memory corresponds to the local NVM 70 of Cayton. This memory is reached by a different connection than the peripheral interconnect. Data may be written from the system memory of a remote server to the local NVM 70 of the RPDMA device.
Applicant argues that Cayton does not disclose “in response to a command received via a peripheral interconnect”.
Examiner submits that Cayton discloses that the RDMA network logic may receive a write request from a device of the network storage architecture. This request is received via the system interface.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LARRY T. MACKALL
Primary Examiner
Art Unit 2131
23 July 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
Prosecution Insights