DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment filed 06/03/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: paragraph [0012], [0050] and [0051].
Applicant is required to cancel the new matter in the reply to this Office Action.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a first capacitive load and a second capacitive load which connected together must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Drawings
The drawings filed 06/03/2026 introduced new matter. Specifically, the newly added drawings fig. 11 and fig. 12 shows a buffer circuit driving first capacitive load (such as a small capacitive load CLP), that is operating in the first capacitive load driving mode and second capacitive load (such as a large capacitive load CLN), that is operating in the second capacitive load driving mode was not disclosed in the application as originally filed. The original drawings figs. 3A-3C and 4-10 and the specification contain no written description support for a buffer that drives CLP and CLN.
Applicant is required to cancel the new matter in the reply to this Office Action
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein the buffer is configurable to operate in : “a first capacitive-load driving mode…, and a second capacitive-load driving mode” but does not specify show the structural relationship between the buffer output node and the respective first and second capacitive loads, the disclose shown driving a first capacitive load in one drawing and second capacitive load in another drawing, nor does it define how the first and second capacitive loads are connected relative to each other.
It is also unclear how the buffer can be considered to drive the first capacitive load versus the second capacitive load when the claim requires the buffer output connected to both loads without specifying any selective coupling, switching between the buffer output and first and second capacitive load. Because the claim does not clearly specify the structural and functional relationship among buffer output, and the first and second capacitive loads, the metes and bounds of the claim of the claim cannot be determined with reasonable certainty.
Claims 2-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 11 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2011/0187457 and Hsu hereinafter) in view of Fukuo (US 6496175) and HASHIGAKI (JP 2010008981A and HASHIGAKI hereinafter) further in view of Sasai et al. (US 10817114 and Sasai hereinafter).
Regarding claim 1, Hsu discloses a buffer [30, fig. 3] comprising: an operational amplifier [31], whose non-inverting (+ terminal of 31) or inverting input terminal (- terminal of 31); a voltage-voltage feedback [feedback (-) terminal to OUT] for the operational amplifier, whose first end is coupled to the inverting input terminal of the operational amplifier; and a first set of switches [PSW1/PSW2] and a second set of switches [NSW1/NSW2], wherein the buffer is configurable to operate in: a first capacitive-load [Cload] driving mode in which the first set of switches is closed and the second set of switches is opened [fig. 4]; and in the first capacitive-load driving mode, an output terminal [OUT terminal] of the operational amplifier is coupled to the output terminal of the buffer [node at Cload] via at least one switch in the first set of switches [32], and a second end of the voltage-voltage feedback [end connected to OUT node] is coupled to the output terminal of the buffer via at least one switch in the first set of switches without passing through the isolation resistor. Hsu does not explicitly disclose whose non-inverting or inverting input terminal receives an output of a pre-stage circuit, feedback network, an isolation resistor whose first end is coupled to an output terminal of the buffer and the isolation resistor is used as a feedback resistor for the operational amplifier; a second capacitive-load driving mode in which the first set of switches and the second set of switches is closed; and the second capacitive load driving mode, the output terminal of the operational amplifier is connected to the second end of the isolation resistor via at least one switch in the second set of switches without passing through the isolation resistor or directly connected to a second end of the isolation resistor.
In the same field of endeavor , Fukuo discloses [fig. 3] an isolation resistor [4], whose first end is coupled to an output terminal of the buffer [node at 5] and a second capacitive load [the lower 5]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Hsu by incorporating isolation resistor and a second capacitive load as taught in Fukuo to connect the first set of switches and close the second set of switches in the case where the buffer drives a second capacitive load and in the case where the buffer drives the second capacitive load, the output terminal of the operational amplifier is coupled to the second end of the isolation resistor via at least one switch in the second set of switches. Hsu in view of Fukuo does not explicitly disclose the operational amplifier is connected to the second end of the isolation resistor via at least one switch in the second set of switches without passing through the isolation resistor or directly connected to a second end of the isolation resistor, whose non-inverting or inverting input terminal receives an output of a pre-stage circuit, feedback network
In the same field of endeavor , HASHIGAKI discloses [figs. 3-4] an isolation resistor [R1], whose first end is coupled to an output terminal of buffer [node at Vout] and a second capacitive load [C, fig. 4], an output terminal of the operational amplifier [output AMP1] is connected to the second end of the isolation resistor via at least one switch in the second set of switches [SW1] without passing through the isolation resistor or directly connected to a second end of the isolation resistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Hsu/Fukuo by incorporating isolation resistor and capacitive load as taught in HASHIGAKI to connect tthe output terminal of the operational amplifier is coupled to the second end of the isolation resistor via at least one switch in the second set of switches. Hsu in view of Fukuo and HASHIGAKI does not explicitly disclose whose non-inverting or inverting input terminal receives an output of a pre-stage circuit.
In the same field of endeavor , Sasai discloses [see fig. 2] non-inverting (+ terminal of OP1) receives an output of a pre-stage circuit [21/22], operational amplifier [OP1] voltage-voltage feedback network [Rag, in 23]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Hsu in view of Fukuo and HASHIGAKI by incorporating a pre-stage circuit and feedback network as taught in Sasai in order to connect second end of the voltage-voltage feedback network is coupled to the output terminal of the operational amplifier via at least one switch in the second set of switches in order to improve the buffer circuit.
Regarding claim 2, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses wherein, the first set of switches includes a first switch [PSW1] and a second switch [PSW2], the second set of switches includes a third switch [NSW1] and a fourth switch [NSW2], wherein, the first switch is coupled between the output terminal of the operational amplifier and the output terminal of the buffer, and the second switch is coupled between the second end of the voltage-voltage feedback network and the output terminal of the buffer, and the third switch is coupled between the output terminal of the operational amplifier and the second end of the isolation resistor, and the fourth switch is coupled between the second end of the voltage-voltage feedback network and the output terminal of the operational amplifier.
Regarding claim 5, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses [fig. 2] wherein, the non-inverting input terminal of the operational amplifier receives a fixed voltage [V2, see fig. 2 of ref. Sasai]; the inverting input terminal of the operational amplifier receives the output of the pre- stage circuit and is coupled to the first end of the voltage-voltage feedback network; the voltage-voltage feedback network comprises a first feedback resistor [Rag] coupled between the first and second ends of the voltage-voltage feedback network.
Regarding claim 11, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses [fig. 3], wherein, the first switch, the second switch, the third switch, and the fourth switch are all CMOS transmission gates [par. 0021].
Regarding claim 16, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses an integrated circuit [LCD devises, para. 0004 and fig. 1] comprising: a buffer [14] according to claim 1.
Regarding claim 17, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses further comprising: a pre-stage circuit, whose output terminal is coupled to the buffer, wherein, the pre-stage circuit is a circuit module that can be equivalent to a voltage source with output resistance [cl. 15, ln. 3-10 ].
Regarding claim 18, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses [fig. 3] wherein, the first set of switches [PSW1/PWS2] and the second set of switches [NSW1/NSW2] are controlled by at least one signal from outside of the integrated circuit [33]; or the first set of switches and the second set of switches are controlled by configuring at least one register bit inside the integrated circuit.
Regarding claim 19, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses [fig. 3] wherein, wherein, the pre-stage circuit is a DAC [13].
Regarding claim 20, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses [fig. 3] wherein, the DAC is a resistive DAC [13].
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. in view of Fukuo and HASHIGAKI further in view of Sasai et al.
Regarding claim 6, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses all the features with respect to claim 5 as outlined above. Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses does not explicitly disclose wherein, the resistance of the first feedback resistor is equal to the output resistance of the pre- stage circuit. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 15, Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses all the features with respect to claim 1 as outlined above. Hsu in view of Fukuo and HASHIGAKI further in view of Sasai discloses does not explicitly disclose wherein, the capacitance value of the second capacitive load is greater than that of the first capacitive load. One of ordinary skill in the art would have been motivated to have used the claimed range since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection.
Allowable Subject Matter
Claims 3-4, 7-10 and 12-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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