DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 recites the limitation “the frequency/phase estimation circuit” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Clarification or correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,231,145. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced in a table below for comparison.
Claim No.: __ of USP 12,231,145
Claim No.: __ of application 19/023,171
5. A broadband modulator comprising: a stable symbol clock (CLK); a variable frequency sample clock; an OFDM modulator circuit that operates at the stable symbol CLK to generate OFDM symbols; a frequency/phase estimation circuit that receives as inputs the stable symbol CLK and the variable frequency sample clock and estimates a frequency error and a phase error; a variable interpolator/decimator (VID) circuit that uses the frequency error and the phase error to generate a codeword; and a digital-to-analog converter (DAC) that receives the codeword from the VID and generates an analog output.
Or
1. A digital frequency generator comprising: a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; and a frequency control word (FCW); wherein the DAC is sampled by the variable frequency sample clock; wherein the DDFS is clocked by the variable frequency sample clock; wherein the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; wherein the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, wherein the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock; and wherein the DAC converts the digital sine codeword to an analog waveform.
8. A broadband modulator comprising: a stable clock; a variable frequency sample clock; a frequency estimation circuit configured to receive as inputs the stable clock and the variable frequency sample clock and estimate a frequency error; a codeword generator circuit configured to generate a codeword using at least the frequency error; a digital-to-analog converter (DAC) configured to generate an analog output from the codeword.
2. The digital frequency generator of claim 1, wherein the variable frequency sample clock is at least one variable frequency sample clock selected from the group consisting of a frequency ramp generator, a pseudo random (PN) modulated frequency source, and a frequency modulation source.
9. The broadband modulator of claim 8, wherein the variable frequency sample clock is at least one variable frequency sample clock selected from the group consisting of a frequency ramp generator, a pseudo random (PN) modulated frequency source, and a frequency modulation source.
3. The digital frequency generator of claim 1, wherein the frequency/phase estimation circuit estimates a frequency error by comparing edges of the REF CLK and the variable frequency sample clock, wherein the frequency error is filtered with a loop filter to generate the FCW for the DDFS.
10. The broadband modulator of claim 8, wherein the frequency/phase estimation circuit is configured to estimate a frequency error by comparing edges of the stable clock and the variable frequency sample clock, wherein the frequency error is filtered with a loop filter to generate the codeword.
4. The digital frequency generator of claim 1, wherein the FCW is a ratio of a desired frequency (fc) and the variable frequency sample clock (fs) wherein j denotes an index of the sample frequency.
11. The broadband modulator of claim 8, wherein the codeword is a ratio of a desired frequency (fc) and the variable frequency sample clock (fsj) wherein j denotes an index of the sample frequency.
6. The broadband modulator of claim 5, wherein the analog output is filtered by a filter to provide a filtered analog output.
12. The broadband modulator of claim 8, wherein the analog output is filtered by a filter to provide a filtered analog output.
7. The broadband modulator of claim 5, wherein the VID circuit converts a modulated signal from the stable symbol CLK domain to the variable frequency sample clock domain, wherein the VID circuit generates a corrected codeword that is provided to the DAC.
13. The broadband modulator of claim 8, wherein the codeword generator circuit is configured to convert a modulated signal from the stable clock domain to the variable frequency sample clock domain, wherein the codeword generator is configured to generate a corrected codeword that is provided to the DAC.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon E. Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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