DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements submitted on 15 Jul 2026 and 27 Oct 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-23 are objected to because of the following informalities:
Claim 1, line 9-10: the limitation "second terminal" is a generic term that is used as part of the resonant element, first resistor, and second resistor. These terminals should have specific names, rather than repeat the exact same terminal name to make it clear that each terminal is distinct.
Claim 13 suffers from the same defect.
Claims 2-12 depend from Claim 1 and thus have at least the same defect(s).
Claims 14-23 depend from Claim 13 and thus have at least the same defect(s).
Claim 1, line 11: the limitation "a second terminal of the resonant terminal" is used for the second time. This makes it unclear whether this is a new claim element or the same one already in introduced in lines 9-10.
Claim 8, line 20: the limitation “drops to a fourth voltage value” should be changed to “drops below a fourth voltage value” to match [0034] of the specification, which says “when the voltage value VD at the connection node ND drops below the fourth voltage value, the controller 110 turns off the second voltage switch SB2”. “Drops to” would also encompass the value 0, which is not what is described in the specification.
Claim 13, line 4-5: recites the limitation “power terminal”. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether this refers to the “power supply terminal”, “power terminal”, or both of those terminals in claim 13.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 14-15 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Holveck (US 11671031 B1).
Regarding Claim 1, Holveck discloses an auxiliary resonant commutated pole device (S5, S6, Ln, 308, 310, 212, 216, Fig 3), comprising: a first resonant capacitor connected between a power terminal and a connection node (308 connected between 212/DC_Bus+ and connection node between 308/310, Fig 3); a second resonance capacitor connected between the connection node and a reference voltage terminal (310 connected between connection node between 308/310 and 216/DC_Bus-, Fig 3); a resonant element (Ln, Fig 3), wherein a first terminal of the resonant element is connected to the connection node (right side of Ln connected to node between 308/310, Fig 3); a first voltage switch connected between the power terminal and a second terminal of the resonant element (S5 connected between DC_Bus+ and the left side of Ln connected to node between 308/310, Fig 3); a second voltage switch connected between a-the second terminal of the resonant element and the reference voltage terminal (S6 connected between the left side of Ln connected to node between 308/310 and DC_Bus-, Fig 3); and a controller connected to a control terminal of the first voltage switch and a control terminal of the second voltage switch (S5 and S6 are controlled by a controller, Fig 3, Col 9[50-61]) and configured to control a switching operation of the first voltage switch and the second voltage switch according to a voltage value at the connection node so that the voltage value at the connection node is within a set range ("if an imbalance is detected between the voltages across the split DC link capacitors, the switches (S5 and S6) are controlled to move charge from one DC link capacitor to the other DC link capacitor until their voltages are balanced. For example, if there is any imbalance, the switches are controlled to allow current to flow between the capacitors until they have the same measured voltage.", Fig 3, Col 10[16-24]).
Regarding Claim 2, Holveck discloses all of the limitations of claim 1, and further discloses wherein when the voltage value at the connection node exceeds the set range, the controller turns on one of the first voltage switch and the second voltage switch ("the switches of the balancing leg (S5 and/or S6) are turned on or off, facilitating active charge transfer from one DC link capacitor to the other DC link capacitor.", Fig 3, Col 11[1-3]).
Regarding Claim 3, Holveck discloses all of the limitations of claim 1, and further discloses wherein when the voltage value at the connection node is within the set range, the controller turns off the first voltage switch and the second voltage switch (S5 and S6 actively control imbalance between the DC Link capacitors until the voltage difference is zero or within a threshold, and then they are off, Fig 3, Col 10[65-67]).
Regarding Claim 4, Holveck discloses all of the limitations of claim 1, and further discloses wherein: there is a power supply voltage value between the power terminal and the reference voltage terminal ("the DC link voltage across the DC bus is controlled to be 400V", Fig 3, Col 5[66-67]), the set range is between +a% of an intermediate value of the power supply voltage value, and a is a real number ("the balancer leg is used to hold the midpoint of the DC link at half of the DC link voltage." and "DC link capacitor voltages are balanced (e.g., the same or within a threshold).", Fig 3, Col 10[29-30] and Col 11[6-7]).
Regarding Claim 9, Holveck discloses all of the limitations of claim 1, and further discloses wherein the resonant element is implemented by an inductor element (Ln, Fig 3).
Regarding Claim 13, Holveck discloses an operating method for an auxiliary resonant commutated pole device (S5, S6, Ln, 308, 310, 212, 216, Fig 3), wherein the auxiliary resonant commutated pole device comprises a first resonant capacitor (308, Fig 3), a second resonant capacitor (310, Fig 3), a resonant element (Ln, Fig 3), a first voltage switch (S5, Fig 3), and a second voltage switch (S6, Fig 3), the first resonant capacitor is connected between a power supply terminal and a connection node (308 connected between 212/DC_Bus+ and connection node between 308/310, Fig 3), the second resonant capacitor is connected between the connection node and a reference voltage terminal (310 connected between connection node between 308/310 and 216/DC_Bus-, Fig 3), a first terminal of the resonant element is connected to the connection node (right side of Ln connected to node between 308/310, Fig 3), the first voltage switch is connected between a power terminal and a second terminal of the resonant element (S5 connected between DC_Bus+ and the left side of Ln connected to node between 308/310, Fig 3), the second voltage switch is connected between the second terminal of the resonant element and the reference voltage terminal (S6 connected between the left side of Ln connected to node between 308/310 and DC_Bus-, Fig 3), and the operating method comprises: detecting a voltage value at the connection node ("the inverter is configured to detect its input voltage. For example, the inverter is configured to determine the voltage across the DC bus, as well as the voltage between the positive DC bus and neutral (which is the voltage across the “upper side” DC link capacitor”) and the voltage between neutral and the negative DC bus (which is the voltage across the “lower side” DC link capacitor”). The difference between the DC link capacitor voltages is determined.", Fig 3, Col 10[59-66]); and turning on one of the first voltage switch and the second voltage switch when the voltage value at the connection node exceeds a set range so that the voltage value at the connection node is within the set range ("if an imbalance is detected between the voltages across the split DC link capacitors, the switches (S5 and S6) are controlled to move charge from one DC link capacitor to the other DC link capacitor until their voltages are balanced.", Fig 3, Col 10[17-21]).
Regarding claim 14, it is rejected for the same reasons as stated above for claim 3.
Regarding claim 15, it is rejected for the same reasons as stated above for claim 4.
Regarding claim 20, it is rejected for the same reasons as stated above for claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Holveck (US 11671031 B1) in view of Mueller (US 20220385188 A1).
Regarding Claim 5, Holveck discloses all of the limitations of claim 4, and further discloses wherein: when the voltage value at the connection node is lower than a first voltage value ("if an imbalance is detected between the voltages across the split DC link capacitors, the switches (S5 and S6) are controlled to move charge from one DC link capacitor to the other DC link capacitor until their voltages are balanced. For example, if there is any imbalance, the switches are controlled to allow current to flow between the capacitors until they have the same measured voltage.", Fig 3, Col 10[16-24]).
Holveck does not disclose the controller turns on the first voltage switch, and the first voltage value is a lowest voltage value of the set range.
Mueller teaches a conventional capacitor balancing technique for use in a circuit with split capacitors (see Fig 10) including the controller turns on the first voltage switch (because Vpos and Vneg are the voltages across the two capacitors across Mueller's DC voltage terminals, Vpos rises exactly as Vneg falls and vice versa at any instant, so S01 checks Vpos-Vneg > V1, which is equivalent to the voltage across Vneg dropping below a first threshold, and then S04 turns on T1, Fig 9-10, [0071-2]), and the first voltage value is a lowest voltage value of the set range ("the first threshold value can also be selected to be smaller", Fig 10, [0034]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the capacitor balancing technique in Holveck, as taught by Mueller, as it provides the advantage of preventing unnecessary activation from ordinary voltage ripple fluctuations ([0033] of Mueller).
Regarding Claim 6, the combination of Holveck and Mueller discloses all of the limitations of claim 5, and further discloses wherein: when the voltage value at the connection node rises higher than a second voltage value (because Vpos and Vneg are the voltages across the two capacitors across Mueller's DC voltage terminals, Vpos rises exactly as Vneg falls and vice versa at any instant, so S12 checks Vpos-Vneg<V2, which is equivalent to the voltage across Vneg rising above a fixed value, Fig 9-10, [0075]), the controller turns off the first voltage switch (S03 turns off all of the switches if it is determined that Vpos-Vneg falls below V2 which is the same event as Vneg rising above a fixed value, Fig 10, [0075] of Mueller), and the second voltage value is higher than the first voltage value (since Vpos-Vneg is a decreasing function of Vneg, a smaller difference threshold (V2<V1) corresponds to a larger Vneg threshold, so the Vneg value that trips turn-off is higher than the Vneg value that trips turn-on, Fig 10, [0076]) and lower than the intermediate value (the turn-off threshold is a value between the turn on threshold and the balance point where Vpos=Vneg by construction of the hysteresis band, Fig 10, [0033] of Mueller).
Regarding Claim 7, Holveck discloses all of the limitations of claim 4, and further discloses wherein: when the voltage value at the connection node is higher than a third voltage value ("if an imbalance is detected between the voltages across the split DC link capacitors, the switches (S5 and S6) are controlled to move charge from one DC link capacitor to the other DC link capacitor until their voltages are balanced. For example, if there is any imbalance, the switches are controlled to allow current to flow between the capacitors until they have the same measured voltage.", Fig 3, Col 10[16-24] of Holveck).
Holveck does not disclose the controller turns on the second voltage switch, and the third voltage value is a highest voltage value of the set range.
Mueller teaches a conventional capacitor balancing technique for use in a circuit with split capacitors (see Fig 10) including wherein: when the voltage value at the connection node is higher than a third voltage value (because Vpos and Vneg are the voltages across the two capacitors across Mueller's DC voltage terminals, Vpos rises exactly as Vneg falls and vice versa at any instant, so S02 checks Vneg-Vpos<V1, which is equivalent to the voltage across Vneg rising above a third fixed value that mirrors the first value, Fig 9-10, [0071] of Mueller), the controller turns on the second voltage switch (S13 turns on T4, Fig 9-10, [0077] of Mueller), and the third voltage value is a highest voltage value of the set range (V1 is the outer boundary of the two-sided band, consistent with the hysteresis structure used for the low side, Fig 9-10, [0033] of Mueller).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the capacitor balancing technique in Holveck, as taught by Mueller, as it provides the advantage of preventing unnecessary activation from ordinary voltage ripple fluctuations ([0033] of Mueller).
Regarding Claim 8, the combination of Holveck and Mueller discloses all of the limitations of claim 7, and further discloses wherein: when the voltage value at the connection node drops to a fourth voltage value (because Vpos and Vneg are the voltages across the two capacitors across Mueller's DC voltage terminals, Vpos rises exactly as Vneg falls and vice versa at any instant, so S21 checks Vneg-Vpos<V2, which is equivalent to the voltage across Vneg dropping below a fourth fixed value, Fig 9-10, [0080] of Mueller), the controller turns off the second voltage switch (S03 turns off all switches, Fig 9-10, [0080] of Mueller), and the fourth voltage value is higher than the intermediate value and lower than the third voltage value (the smaller difference hysteretic threshold V2 for turn off corresponds to a Vneg value that is closer to 0/balanced than the larger difference threshold V1 for turn on, Fig 9-10, [0033, 0076] of Mueller).
Regarding claim 16, it is rejected for the same reasons as stated above for claim 5.
Regarding claim 17, it is rejected for the same reasons as stated above for claim 6.
Regarding claim 18, it is rejected for the same reasons as stated above for claim 7.
Regarding claim 19, it is rejected for the same reasons as stated above for claim 8.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Holveck (US 11671031 B1) in view of Hong (US 20170288573 A1).
Regarding Claim 10, Holveck discloses all of the limitations of claim 1.
Holveck does not disclose a detection circuit connected to the connection node and the controller, configured to receive a voltage value at the connection node to generate a detection signal, and provide the detection signal to the controller, wherein the controller determines whether the voltage value at the connection node is within the set range according to the detection signal.
Hong teaches a conventional control unit for use in a power converter with DC link capacitors (see Fig 5/7) including further comprising: a detection circuit connected to the connection node and the controller (51 detects the neutral point voltage and is connected to 52, Fig 5), configured to receive a voltage value at the connection node to generate a detection signal (51 receives the voltage of the neutral point and generates an output, Fig 5), and provide the detection signal to the controller (51's output goes to 52, which controls the switches, Fig 5), wherein the controller determines whether the voltage value at the connection node is within the set range according to the detection signal (52 determines if the voltage is between +REF and -REF, Fig 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the control unit in Holveck, as taught by Hong, as it provides the advantage of triggering charge transfer when the voltage of the reference point and neutral point are different using simple, low-cost analog comparator hardware ([0012] of Hong).
Regarding Claim 21, it is rejected for the same reasons as stated above for Claim 10.
Claims 11-12 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Holveck (US 11671031 B1) in view of Hong (US 20170288573 A1) and further in view of Oda (US 20240250679 A1).
Regarding Claim 11, the combination of Holveck and Hong discloses all of the limitations of claim 10.
The combination of Holveck and Hong does not disclose wherein the detection circuit comprises: a first resistor, wherein a first terminal of the first resistor is connected to the connection node, and a second terminal of the first resistor is connected to the controller; and a second resistor, wherein a first terminal of the second resistor is connected to the second terminal of the first resistor, and a second terminal of the second resistor is connected to the reference voltage terminal.
Oda teaches a conventional detection circuit for use in a power circuit (see Fig 2) including wherein the detection circuit comprises: a first resistor (Rd1, Fig 2), wherein a first terminal of the first resistor is connected to the connection node (Rd1's top terminal is connected to Holveck's node between the capacitors, Fig 2), and a second terminal of the first resistor is connected to the controller (Rd1's bottom terminal is connected to controller/microcomputer 26, Fig 2); and a second resistor (Rd2, Fig 2), wherein a first terminal of the second resistor is connected to the second terminal of the first resistor (the top terminal of Rd2 is connected to the bottom terminal of Rd1, Fig 2), and a second terminal of the second resistor is connected to the reference voltage terminal (Rd2's bottom terminal is connected to ground conductor G, Fig 2, [0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the detection circuit in Holveck, as taught by Oda, as it provides the advantage of low cost, passive sensing device.
Regarding Claim 12, the combination of Holveck, Hong, and Oda discloses all of the limitations of claim 11, and further discloses a wherein the second terminal of the first resistor outputs the detection signal (Rd1 sends the detection signal to controller/microcomputer 26, Fig 2 of Oda).
Regarding Claim 22, it is rejected for the same reasons as stated above for Claim 11.
Regarding Claim 23, it is rejected for the same reasons as stated above for Claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 9/03/2026
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