DETAILED ACTION
Notice of Pre-AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This action is responsive to the following communications: the Amendment filed July 30, 2026.
Claims 1-4 are pending. Claim 1 is amended. Claim 5 is canceled. Claim 1 is independent.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 13/491,377, filed on June 13, 2012.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Warren et al. (U.S. 2011/0060886; hereinafter “Warren”) in view of Oh et al. (U.S. 2016/0231941; hereinafter “Oh”).
Regarding independent claim 1, Warren teaches a memory device (Fig. 1), comprising:
a flash memory module comprising a plurality of data blocks (Fig. 1: 140); and
a flash memory controller (Fig. 1: 120), configured to access the flash memory module (Fig. 1: 140);
wherein the flash memory controller is configured to receive data from a host device (Fig. 1: Data 105), and to determine if the data received from the host device is cold data or hot data (“characteristic of the received data set…For example where the data type is a document, it may be considered to be more likely to be frequently accessed than if it was a very large document,” see pages 6-7, par. 0036); and if the data is determined as the cold data, the flash memory controller uses a two-bit-per-cell mode or a three-bit-per-cell mode to write the data into one of the plurality of data blocks (“less frequently accessed may be written as three bits per cell” see pages 6-7, par. 0036); and if the data is determined as the hot data, the flash memory controller uses a one-bit-per-cell mode to write the data into another one of the plurality of data blocks (“frequently accessed data may be written as one bit per cell,” see pages 6-7, par. 0036).
However, Warren is silent with respect to the flash memory controller determines if the data received from the host device is the cold data or the hot data according to a logical address of the data.
Oh teaches a flash memory controller determines if the data received from the host device is the cold data or the hot data according to a logical address of the data (see page 3, par. 0049).
Since Oh and Warren are from the same field of endeavor, the teachings described by Oh would have been recognized in the pertinent art of Warren.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Oh with the teachings of Warren for the purpose of cost savings and increase the overall storage capacity, see Oh’s page 3, par. 0040.
Regarding claim 2, Warren in combination with Oh teaches the limitations with respect to claim 1.
Furthermore, Warren teaches wherein the plurality of data blocks are realized by triple-level cells (TLCs) (see page 2, par. 0020), and the blocks supports eight plurality of program threshold voltage intervals (see page 2, par. 0020).
Regarding claim 3, Warren in combination with Oh teaches the limitations with respect to claim 1.
Furthermore, Warren teaches wherein the flash memory controller determined if the data received from the host device is the cold data or the hot data according to a file type (see pages 7-8, par. 0040-0041).
Regarding claim 4, Warren in combination with Oh teaches the limitations with respect to claim 1.
Furthermore, Warren teaches wherein the flash memory controller determines if the data received from the host device is the cold data or the hot data according to a file extension (see pages 6-7, par. 0036).
Response to Arguments
Applicant’s arguments, see pages 5-6, filed July 30, 2026, with respect to the rejection(s) of claim(s) 1-4 under 35 U.S.C. 102(a) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 103(a) as being unpatentable over Warren in view of Oh.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
