DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in present Application No. 19/023,360 filed on 01/16/2025.
Acknowledgment is made of applicant's claim for provisional priority under 35 U.S.C. 119(e). The provisional application being filed 01/30/2024, as Application No. 63/626,542.
Information Disclosure Statement
The information disclosure statements filed 01/16/2025 and 09/17/2025 have been submitted for consideration by the Office. They have been placed in the application file and the information referred to therein have been considered.
Allowable Subject Matter
Claims 4, 5, 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 2016/0049359).
Regarding claim 1, Chiang discloses (in Fig. 2F, 2G, 2H) a circuit substrate [2], comprising: a glass substrate [20] (See paragraph 0044: “In the present embodiment, the substrate body 20 is a silicon-containing plate, for example, a silicon wafer or a glass substrate.”) having a through hole [200] (See Fig. 2B and paragraph 0050: “a plurality of conductive posts 25 are formed in the through holes 200.”); a conductive post [25] located in the through hole [200] (See paragraph 0050: “a plurality of conductive posts 25 are formed in the through holes 200.”); and a dielectric layer [22] (See paragraph 0048: insulating layer 22) located in the through hole [200], wherein the conductive post [25] is separated from the glass substrate [20] by the dielectric layer [22].
Regarding claim 2, Chiang, as applied to claim 1, further discloses (in Fig. 2F) wherein the dielectric layer [22] comprises: a first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 22 that is contacting the conductive post 25 inside the through hole 200] located in the through hole [200] (See Fig. 2B and paragraph 0050: “a plurality of conductive posts 25 are formed in the through holes 200.”) to separate the conductive post [25] and the glass substrate [20]; and a second dielectric portion [The second dielectric portion is the horizontal portion of dielectric layer 22 that is disposed between the glass substrate 20 and the conductive pad 26] covering a top surface of the first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 22 that is contacting the conductive post 25 inside the through hole 200] and a top surface of the glass substrate [20].
Regarding claim 3, Chiang, as applied to claim 2, further discloses (in Fig. 2F, 2G, 2H) wherein a height of the conductive post [25] is greater than a thickness of the glass substrate [20].
Regarding claim 6, Chiang, as applied to claim 1, further discloses (in Fig. 2F, 2G, 2H) wherein the dielectric layer [22] comprises a first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 22 that is contacting the conductive post 25 inside the through hole 200], and the first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 22 that is contacting the conductive post 25 inside the through hole 200] is located in the through hole (See Fig. 2B and paragraph 0050: “a plurality of conductive posts 25 are formed in the through holes 200.”) to separate the conductive post [25] and the glass substrate [20].
Regarding claim 12, Chiang discloses a method for fabricating a circuit substrate (See Fig. 1H), comprising: forming a through hole [100] in a glass substrate [10], wherein the glass substrate [10] has a crack (See paragraph 0017: “Further, since the conductive pads 16 and the conductive posts 15 are fabricated in different processes, an interface will be formed between the conductive pads 16 and the conductive posts 15. As such, delamination or cracking easily occurs between the conductive pads 16 and the conductive posts 15.”) located around the through hole [100]; forming a conductive layer [13] in the through hole [100] of the glass substrate [10] to repair the crack; and forming a first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 12 that is contacting the conductive layer 13 inside the through hole 100] in the through hole [100] of the glass substrate [10].
Regarding claim 13, Chiang, as applied to claim 12, further discloses (in Fig. 1H) forming a first surface conductive layer [13’], wherein the first surface conductive layer [13’] covers a top surface of the first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 12 that is contacting the conductive layer 13 inside the through hole 100] and a top end of the conductive layer [13]; and forming a second dielectric portion [The second dielectric portion is the horizontal portion of dielectric layer 12 that is disposed between the glass substrate 10 and the conductive layer 13’] on the top surface of the first dielectric portion [The second dielectric portion is the horizontal portion of dielectric layer 12 that is disposed between the glass substrate 10 and the conductive layer 13’] and a top surface of the glass substrate [10].
Regarding claim 14, Chiang, as applied to claim 13, further discloses (in Fig. 1H) further comprising: forming a second surface conductive layer [The conductive portion of the RDL structure 11], wherein the second surface conductive layer [The conductive portion of the RDL structure 11] covers a bottom surface of the first dielectric portion [The first dielectric portion is the vertical portion of dielectric layer 12 that is contacting the conductive layer 13 inside the through hole 100] and a bottom end of the conductive layer [13]; and forming a third dielectric portion [The insulating portion of the RDL structure 11] on a bottom surface of the glass substrate [10].
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERMAN NG whose telephone number is (571)270-3131. The examiner can normally be reached Mon-Fri 10AM-6PM.
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/SHERMAN NG/Primary Examiner, Art Unit 2847
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